lecture1 - california state university, bakersfield · title: lecture1 author: vida created date:...

ECE 3220 Digital Design with VHDL

Course Information Lecture 1

California State University

Course Information

u Course #: ECE 3220u Course Name: Digital Design with VHDLu Course Instructor: Dr. Vida Vakilian

u Email: [email protected]

u Course Objective:u To analyze and design combinational and

sequential logic circuits.u To write VHDL code to describe and

synthesize both types of logic circuits.


Course Information

Textbooksu Main book: Fundamental of Digital Logic with VHDL Design, 3thedition, Stephen Brown and Zvonko Vranesic, McGraw-Hill, 2008u Supplementary books:1) Digital systems design using VHDL, Charles H. Roth, JR 2) Digital Electronics a Practical Approach with VHDL, 9thedition, William Kleitz


u Labs performed weekly.u In our Labs, we use Altera DE2 board

Lab Information


Homework

u Homework will be assigned on a weekly basis.u Homework is due at the beginning of class on the date specified.

u No late submissions accepted.u You can discuss the homework problems with one another.

u However, you must submit your own work.u Copying solutions is considered cheating.

u Homework is essential to the learning process!


Exams

u One midterm exam.u Midterm and final exams are closed-book.u No make-up exams.

u In the case of an emergency, see me.u Notify me in advance (whenever possible) if a

conflict or problem exists.


Grading

u The final grade will be calculated as follows:

u Homework 10%u Lab 20%u Midterm 30%u Final Exam 40%

Digital Hardware Design


First Integrated Circuit (IC)

u In 1958, Jack Kilby made the first IC when he was woking at Texas Instruments . He successfully interconnected several transistors, resistors and capacitors by hand on a single substrate.


First Integrated Circuit (IC)


First Microprocessor: Intel 4004

u In November 1971, Intel introduced the world's first single chip microprocessor, called “the Intel 4004”.


Development Process

Required product

Design specifications

Initial design

Simulation

Design correct?

Redesign

Prototype implementation

Testing

Meets specifications?

Finished product

Minor errors?

Make corrections

No

Yes

No

Yes

Yes

No

u The development process begins with the definition of product specifications. The most obvious requirements are that the product must function properly. ü Meet an expected level of

performance ü Its cost should not exceed a

given target

u In the case of large errors in testing, it is necessary to redesign the product and repeat all the steps.

u When the prototype passes all the tests, then the product is deemed to be successfully designed and it can go into production.


Digital Hardware System

u A chip comprises a number of subcircuits, which are interconnected to build the complete circuit.

u Each of these subcircuits is a logic circuit, comprises a network of connected logic gates.

u Logic gates are built with transistors, implemented by fabricating various layers of material on a silicon chip.


• designs must be sentfor expensive and timeconsuming fabricationin semiconductor foundry

• bought off the shelfand reconfigured bydesigners themselves

ASICApplication SpecificIntegrated Circuit

FPGAField Programmable

Gate Array

• designed all the wayfrom behavioral descriptionto physical layout

• no physical layout design;;design ends witha bitstream usedto configure a device

Two design methodologies


FPGA vs. ASIC


ASICs FPGAs

High performanceOff-the-shelf

Short time to the market

Low development costs

Reconfigurability

Low power

High cost

FPGA vs. ASIC


What is FPGA?

Block RAMs

Block RAMs

ConfigurableLogicBlocks

I/OBlocks

BlockRAMs


What is FPGA?


Library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity RC5_core isport(

clock, reset, encr_decr: in std_logic;data_input: in std_logic_vector(31 downto 0);data_output: out std_logic_vector(31 downto 0);out_full: in std_logic;key_input: in std_logic_vector(31 downto 0);key_read: out std_logic;

);end AES_core;

Specification / Pseudocode

VHDL description (Your Source Files)Functional simulation

Post-synthesis simulationSynthesis

On-paper hardware design (Block diagram & ASM chart)

FPGA Design Process (1)


Implementation

Configuration

Timing simulation

On chip testing

FPGA Design Process (2)

lecture1 - california state university, bakersfield · title: lecture1 author: vida created date:...

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