lecture12annotat backup

8/9/2019 Lecture12annotat Backup

1/17

6.012 - Microelectronic Devices and Circuits - Fall 2005 Lecture 12-1

Lecture

12

- Digital

Circuits

(I)

The inverter

October20,2005

Contents:

1.Introductiontodigitalelectronics: theinverter

2.

NMOS

inverter

with

resistor

pull

up

Reading assignment:

Howe

and

Sodini,

Ch.

5,§§5.1-5.3.2


2/17


Key questions

•Whatarethekeyfiguresof meritof logiccircuits?

•How can one make a simple inverter using a singleMOSFET?


3/17

v


1. Introduction to digital electronics: the in-verter

In

digital

electronics,

digitally-encoded

information

is

rep-resented

by

means

of

two

distinct

voltage

ranges:

V

VMAX

VOH

VOL

VMIN

logic1

logic0

undefinedregion

•logic 0 : V MIN ≤V ≤V OL

•

logic

1:

V OH ≤V ≤V M AX

•undefined logic value: V OL ≤V ≤V OH .

Logic

operations

are

performed

using

logic

gates .

Simplest

logic

operation

of

all:

inversion ⇒in erterinverter


4/17

threshold


2Ideal inverter:

IN OUT

1OUT=IN 0

1

IN

0

Circuit

representation

and

ideal

transfer

function:

VOUTv+

V+ VOUT=VIN

V++ + 2

VIN VOUT

- -00 VM=

V+ V+ VIN2

Defineswitching point orlogic :logic threshold :

V M ≡ inputvoltageforwhichV OU T =V IN

-for

0≤V IN ≤V M ⇒ V OU T =V

+

-for

V M ≤V IN ≤V + ⇒ V OU T = 0


5/17

re ation

v


Key

property

of

ideal

inverter:

signal

gener signal regeneration

VOUTv+

V+ VOUT

=VIN

V++ + 2

VOUTVIN

--00 VM=

V+ V+ VIN2

Ideal inverter returns well defined logical outputs (0 orV

+)

even

in

the

presence

of

considerable

noise

in

V IN (from

voltage

spikes,

crosstalk,

etc.)

VIN VOUT

V+ V+

VM VM

0 0

logicle elrestorationlogiclevelrestoration

noisesuppressionnoisesuppression

VIN VOUT

V+ V+

VM VM

0 0

VIN VOUT

V+ V+

VM VM

0 0

pulseedgesharpeningpulseedgesharpening


6/17


2”Real” inverter:

VOUT

VOUT

0

slope=-1

VOH

VOL

VMIN

VMAXlogic1

logic0

undefinedregion

|Av|>1

V+

v+

+ +

- -

VIN

0V+ VIN

Ina realinverter,validlogic levelsdefinedasfollows:

•logic 0 :

V M IN ≡

output

voltage

when

V IN =

V

+

V OL ≡smallestoutputvoltagewhereslope=-1

•logic 1:

V OH ≡largestoutputvoltagewhereslope=-1

V M AX ≡

output

voltage

when

V IN = 0


7/17


Two

other

important

voltages:

|Av|1

noisesuppressedVOUT

logic1

logic0

undefinedregion

VMAX slope=-1VOH

edgessharpened

|Av|

range

of

valid

logic

values

Key

to

signal

regeneration

in

inverter:

high

voltage

gain high voltage gain


8/17

mar


Quantify

signal

regeneration

through

noise

gins .noise margins .

Consider

chain

of

two

inverters:

noiseM N

VOH

VMAX

VMIN VMIN

VMAX

VOUT VIN

NMH

NMLVOL

VIH

VIL

inverterM inverterN

output input

Define

noise

margins :

N M H = V OH −V IH noisemarginhigh

N M L = V IL −V OL noisemarginlow

Whensignaliswithinnoisemargins:

•logic1output fromfirst inverter interpretedas logic1

input

by

second

inverter

•logic0output fromfirst inverter interpretedas logic0

input

by

second

inverter


9/17


Simplifications

for

hand

calculations

Hard

to

compute

Av =−1pointsintransferfunction.

Approximate

calculation:

VOUT

VOH=VMAX

VM

VOL=VMIN0

VOUT=VIN

slope=Av(VM)

0 VIL VMVIH V+ VIN

• AssumeV OL V M IN andV OH V MAX

• Tracetangentof transferfunctionatV M (slope=smallsignalvoltagegainatV M )

• V IL intersectionof tangentwithV OU T =V MAX

• V IH intersection

of

tangent

with

V OU T =

V MIN

• toenhancenoisemargin: |Av(V M )| ↑


11/17


2Transient characteristics

Look

at

inverter

switching

in

the

time

domain:

V OL

90%

50%

10%

t PHL

t PLH

V OH

t R

t CYCLE

50%

90%

10%

0 t

V IN

V OUT

0 t

t R

t F

V OH

V OL

t F

IN OUT

tR ≡risetimebetween10%and90%of totalswing

tF ≡ fall timebetween90%and10%of totalswing

tP HL ≡propagation delay from high-to-low between50%

points

tP LH ≡propagation delay from low-to-high between

50%

points

Propagation delay: tP =1

2(t +t )P HL P LH


12/17


13/17


2. NMOS inverter withresistor pull up

V+=VDD

VIN

VOUT

IR

IDCL

R

loadcapacitance(fromfollowingstages)

Features:

•

V BS =

0

(typically

not

shown)

•C L summarizescapacitiveloadingof followingstages(other

logic

gates,

interconnect

lines)

Basic

operation:

•

if

V IN < V T ,

MOSFET

OFF

⇒

V OU T =

V DD•if V IN > V T ,MOSFETON⇒V OU T small(valueset

by

resistor/nMOS

divider)


14/17


VDD

VIN

VR

VOUT

IR

ID

R

+

-

Transfer

function

obtained

by

solving:

I R =I D

Can solve graphically: I-V characteristics of pull-up re-sistor

on

I D vs.

V OU T transistor

characteristics:

IR=ID

0

1/R

IR=ID

1/R

IR=ID

1/R

VDD

R

VDD

R

0 VR=VDD-VOUT-VDD VR-VDD=-VOUT

0 VDD VOUT

0


15/17


Overlap

I-V

characteristics

of

resistor

pull-up

on

I-V

char-acteristics

of

transistor:

loadline

VGS=VDD

VGS=VIN

VGS=VT

0 VDD VDS=VOUT

0

IR=ID

VDD

R

Transfer

function:

VOUT=VDS

VDD

00 VT VDD VIN=VGS


16/17


Logic

levels:

VOUT=VDS

VMAX=VDD

VM

VMIN0

VOUT=VIN

0 VT VM VDD VIN=VGS

For

V M AX ,transistor iscut-off,I D = 0:

V MAX =V DD

For V M IN ,transistor isinlinearregime;solve:

W V MIN V DD−V MINI D = µnC ox(V DD− −V T )V MIN =I R =

L 2 R

For V M ,transistor isinsaturation;solve:

W I D = µnC ox(V M −V T )

2 =

I R =V DD−V M

2L R

Will

continue

next

lecture

with

analysis

of

noise

margin

and

dynamics...


17/17


Key conclusions

•Logic circuits must exhibit noise margins in whichthey

are

inmune

to

noise

in

input

signal.

•Logic circuits must be regenerative: able to restoreclean

logic

values

even

if

input

is

noisy.

•Propagation delay : timeforlogicgatetoperformitsfunction.

•

Concept

of

load

line:

graphical

technique

to

visualize

transfercharacteristicsof inverter.

•First-order solution (by hand) of inverter figures of merit

easy

if

regimes

of

operation

of

transistor

are

correctly

identified.

•

For

more

accurate

solutions,

use

SPICE

(or

other

cir-cuit

CAD

tool).

lecture12annotat backup

Documents