lecture13 settling 2up
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EECS240 – Spring 2012
Lecture 13: Settling
Elad AlonDept. of EECS
EECS240 Lecture 13 2
Settling
• Why interested in settling?
• Oscilloscope: track input waveform without
ringing
• ADC (switched-cap amplifier): gain a signal up
by a precise amount within Tsample
2
Cf
1
1
Cs
2
Vi
Vo
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EECS240 Lecture 13 3
Step Response
Vi
-Vo/A
v
time
• Two types of settling “errors”:
• Static
• Finite gain, capacitor mismatch
• Dynamic
• Takes time to reach final value
EECS240 Lecture 13 4
Static Error
Vi
-Vo/A
v
time
static error
oT
vo
i
o
FA
c
V
V
11
KCL
f
f s i
s
f
C F
C C C
C cC
with
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EECS240 Lecture 13 5
Static Error (cont.)
• Example:
• Closed loop gain: c = -4, Cf = 1pF, Cs = 4pF, Ci = 1pF
• F = 1/6 (Ci hurts!)
• Error specification: <0.1%• FAvo > 1000
• Avo > 6000 over output range
relative error
11
11
o
i vo
vo
V cc
V FA
FA
EECS240 Lecture 13 6
Dynamic Errors• Many possible dynamic effects that impact
settling error:• Finite bandwidth
• Feedforward zero
• Non-dominant poles
• Doublets
• Slewing
• Approximate analysis approach:• Decompose each error source, isolate interactions
• Add all errors together
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EECS240 Lecture 13 7
Single Time Constant Linear Settling
• For dynamic settling (and
for T0 >> 1), can generally
ignore r oGm
Cf
Cs
Vi
VoCi
Vx
CL
m
f L
m
f
i
o
FG
C F C s
G
C s
cV
V
1
1
1
EECS240 Lecture 13 8
Time Domain Step Response
,
1
1
step
o step
V s zV c
s p s
Frequency domain: Time domain:
Note: For p=z the error is zero and the
circuit has infinite bandwidth.
Applications?
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EECS240 Lecture 13 9
Time Domain Step Response
,
, ,
input step:
output step:
1
1
1
1
step
i step
o step i step
step
V V
s
s zV c V
s p
V s zc
s p s
Frequency domain: Time domain:(inverse Laplace transform)
,
ideal response in itial error (feedforward)
exponentially decaying error
1 1 pt
stepo step
pv t V c e
z
EECS240 Lecture 13 10
Case 1: |p/z| << 1Relative settling error:
ln
t o o s
o
s
v t v t t e
v t
t
t
stepstepo ecV t v 1
responseideal
,
• Easiest number to remember: 2.3
per decade
• Example: 1% settling, 4.6ns clock cycle: = 1ns• CL,eff usually set by noise – use settling todetermine required gm
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EECS240 Lecture 13 11
Case 2: |p/z| not negligible
Relative settling error :
1
ln1
t o o s
o
s
f Leff
v t v t t pe
v t z
t
F C C
t
stepstepo e z
pcV t v 11
responseideal
,
• Example:
• c = 0.25, Cf = 1pF, Cs = 250fF, Ci = 250fF, CL = 1pF
• F = 0.67, CL,eff = 1.33pF
• ε = 0.1%:• ts (no feedforward) = 6.9
• ts (with feedforward) = -ln[1e-3/(1+0.67*0.75)]=7.3
EECS240 Lecture 13 12
Non-Dominant Pole• Ignore feed-forward zero for simplicity
• (Just increases final swing by 1+FCf /CL,eff )
• Model for non-dominant pole:
m
Leff in
o
FG
C s
cV
V s H
1
1
0
2
2
1
is unity gain bandwidth of
m
m
u
u
G
G s s p
p K
T s
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EECS240 Lecture 13 13
Step Response
EECS240 Lecture 13 14
Non-Dominant Pole (cont.) ),(-1 :error Relative K t vs
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EECS240 Lecture 13 15
Settling Time
1 ,10forK :timeSettling 3 st
• Optimum at K=3.3
EECS240 Lecture 13 16
Non-Dominant Pole vs.
• Optimum K actually depends on required accuracy
• Still, always want to avoid K<~2
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EECS240 Lecture 13 17
Doublets
• Amplifier model:
• Closed-loop gain (ignore feedforward zero):
1( )
1
zm mo
p
sG s G
s
1 h wit1
of bandwidthis , 33
p
z
dBdB p sT
with
3
11
1 1
1
o z
Leff in dB pp
m
V scc
C V s s
s FG s
3mo
dB
Leff
pp p
FG
C
with
EECS240 Lecture 13 18
Doublet Analysis
• Step response
3
, 1 ppdB t t
o step stepv t cV Ae Be
2
1
1 1
B
A B
with
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EECS240 Lecture 13 19
Doublet Example
=1 5
= 3
EECS240 Lecture 13 20
Doublet Conclusions• Case A:
• Doublet settles faster than amplifier
• Has no impact on overall settling time
• Case B:
• Doublet settles more slowly than amplifier
• Determines overall settling time(unless within settling accuracy requirements)
• Avoid “slow” doublets!
1 i.e. 12
12
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EECS240 Lecture 13 21
Final Note on Doublets
EECS240 Lecture 13 22
Slewing• Transconductor ∆I vs. ∆V:
• Model for (nonlinear) slewing amplifier
• Piecewise linear approximation:
• Slewing with constant current, followed by
• Linear settling exponential
• ts = tslew + ts,lin
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EECS240 Lecture 13 23
Slewing Analysis
• Circuit model during slewing:
Cs
Cp
CL
Cf
Vo
Vx
Vi
ISS
EECS240 Lecture 13 24
Slewing Analysis (cont.)
time
Vi
Vx
Votslew
Vi,step
V*
tlin
Vx,step
Vo1,step
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EECS240 Lecture 13 25
Slewing Analysis (cont.)
• Slewing period:
• Linear settling during final V* of swing at Vx:
• Step during linear settling:
• Linear settling time:
, , 2
2
,
with
*
f Ls x step i step i
s f L
x x x step o
x Leff oslew
SS
C C C V V C C
C C C C
V V V V V
F
V C V t
SR FI
*V F
,,ln
*
i steps lin cV F t
V