lecture_18.pdf

ECE 301 Digital Electronics

Latches and Flip-Flops

(Lecture #18)

The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6th Edition, by Roth and Kinney,

and were used with permission from Cengage Learning.

Spring 2011 ECE 301 - Digital Electronics 2

Brief introductionto

Sequential Logic Circuits



The output of a sequential logic circuit is dependent not only on the present inputs, but also on the past sequence of the inputs.

A sequential logic circuit must remember the past history of the inputs.

It does this using basic memory elements. Latches Flip-Flops



CombinationalLogicCircuit Memory

inputs outputs


Basic Memory Elements


Basic Memory Elements Latch

Clock input is level sensitive. Output can change multiple times during a clock

cycle. Output changes while clock is active.

Flip-Flop Clock input is edge sensitive. Output can change only once during a clock cycle. Output changes on clock transition.


Basic Memory Elements

Both latches and flip-flops use feedback to achieve memory.


Feedback Circuit with 2 Stable States

What is the problem with this circuit?


Latches


Set-Reset (SR) Latch A Set-Reset Latch has two inputs

Set (S) input Reset (R) input

It can be constructed from two cross-coupled NOR gates or two cross-coupled NAND gates.

It has three modes of operation Set: Latch output set to 1 (Q+ = 1) Reset: Latch output reset to 0 (Q+ = 0) Store: Latch output does not change (Q+ = Q)


SR Latch: using NOR gatesA B NOR0 X X'1 X 0

Feedback NOR gates


SR Latch: Set (S = 1, R = 0)A B NOR0 X X'1 X 0

1

01

0

P = Q'


SR Latch: Reset (S = 0, R = 1)A B NOR0 X X'1 X 0

0

10

1

P = Q'


SR Latch: Store (S = 0, R = 0)A B NOR0 X X'1 X 0

0

01

0

P = Q'

Initial Condition: P = 0, Q = 1


SR Latch: Store (S = 0, R = 0)A B NOR0 X X'1 X 0

0

00

1

P = Q'

Initial Condition: P = 1, Q = 0


If S = 1 (Set), Q+ = 1

If R = 1 (Reset), Q+ = 0

If S = R = 0, Q+ = Q (no change)

S = R = 1 is not allowed.

SR Latch: BehaviorNextvalue

Presentvalue

S R Q Q+0 0 0 00 0 1 10 1 0 00 1 1 01 0 0 11 0 1 11 1 0 not1 1 1 allowed


P Q

SR Latch: Improper Operation


SR Latch: Symbol

Q'

Q

SRLatch

S

R

Q

Q'

always complementary


SR Latch: Timing Diagramstore set store reset

= propagation delay of the latch

Q'

Q


SR Latch: Characteristic Equation

Characteristic Equation: Q+ = S + R'.Q (S.R = 0)

Q = present stateQ+ = next state


SR Latch: using NAND gatesA B NAND0 X 11 X X'

S' R' Q Q+1 1 0 01 1 1 11 0 0 01 0 1 00 1 0 10 1 1 10 0 0 not0 0 1 allowed


Gated D Latch A Gated D Latch has two inputs

Gate (G) input Data (D) input

It can be constructed from an SR Latch and additional logic gates.

It has the following behavior G = 1: D is passed to Q (Q+ = D) G = 0: Q remains unchanged (Q+ = Q)

Also referred to as a transparent latch.


Gated D Latch: Circuit and Timing

NOR gates


Gated D Latch: Symbol and Truth Table

No invalid inputs!


Gated D Latch: Characteristic Equation

Characteristic Equation: Q+ = G'.Q + G.D

0

1

2

3

6

7

4

5


Gated D Latch: using NAND gates

S'

R'

NAND gates


Flip-Flops


D Flip-Flop A D Flip-Flop has two inputs

Clock (Ck) --- denoted by the small arrowhead Data (D)

The output of the D Flip-Flop changes in response to the clock input only.

not in response to a change in the D input The D Flip-Flop is edge-triggered not level-sensitive

Positive (or rising) edge-triggered: 0 1 Negative (or falling) edge-triggered: 1 0


Q+ = DCharacteristic Equation:

D Flip-Flop


D Flip-Flop: Timing Diagram

Which clock edge is the D flip-flop triggered on?


D Flip-Flop (master-slave)Gated D Latches

Enabled on opposite levels of the clock


D Flip-Flop: Timing Diagram

Which clock edge is the D flip-flop triggered on?


D Flip-Flop: Setup and Hold TimesSetup time Hold time

Propagation delay


D Flip-Flop: Minimum Clock Period


Questions?

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