lecturer 43-overview of ee 334

8/12/2019 Lecturer 43-Overview of EE 334

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Bipolar junction Transistor characteristics

NMOS Inverter

For any IC technology used in digitalcircuit design, the basic circuit element

is the logic inverter. Once the operation and

characterization of the invertercircuits are thoroughly understood, theresults can be extended to the designof the logic gates and other more

complex circuits.


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+

+

VGS=V

RD

=VDD

=VDS

VGS=V

RD

=VDD

=VDS

It should be be noted that the minimum output voltage, or the logic 0 level, for a high

input decreases with increasing load resistance, and the sharpness of the transition

region between a low input and a high input increases with increasing load resistance.

NMOS Inverter with Enhancement

Load

This basic inverterconsist of twoenhancement-onlyNMOS transistorsand is much morepractical than theresister loaded

inverter, which isthousand of timeslarger than aMOSFET.

NMOS Inverter with Enhancement Load

VO,, max= VOH=VDD-VTNL

For good logic 0 required high aspect ratio!

Limitation of NMOS

inverter

Example 16.3


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NMOS Inverter with Depletion Load

This is an alternate form ofthe NMOS inverter that

uses an enhancement-depletion MOSFET loaddevice with gate and sourceterminal connected.

This inverter has theadvantage of VO= VDD, aswell as more abrupt VTCtransition region even thoughthe W/L ratio for the output

MOSFET is small.

The term depletion modemeans that a channel existseven with zero gate voltage.

VT Characteristics of NMOS Inverter with

Depletion Load

The Figure demonstrate in present configuration more abruptVTC transition region can be achieved even though the W/Lratio for the output MOSFET is small.


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1160W 825W200W

All the examples and home work problems related to power dissipation are important!

Transient Analysis of NMOS inverters

The source ofcapacitance CT2 and CT3are the transistor input

capacitances andparasitic capacitancesdue to interconnect linesbetween the inverterstages.

The constant currentover a wide range of VDSprovided by the depletionload implies that thistype of inverter switch a

capacitive load morerapidly than the othertwo types inverterconfigurations.

The rate at

Transient Analysis of NMOS inverters (cont.)

The fall time relativelyshort, because the load

capacitor dischargesthrough the large drivetransistor.

The raise time is longerbecause the loadcapacitor is charged bythe current through the

smaller load transistor.

(W/L)L=1

(W/L)D=4

F-0.5pF

Concept of effective width to length ratios

For the NOR gate the effective

width of the drivers transistorsdoubles. That means the effectiveaspect ratio is increased.

For theNAND gate the effective

length of the driver transistorsdoubles. That means the effective

aspect ratio is decreased..

Parallel combinationSeries combination

NAND gate for more than three inputs is not attractive???


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NMOS NOR gate: Special case when all

inputs are at logic 1When A=B=logic 1Both driver transistors are switched into nonsaturation regionand load transistor is biased in saturation region. We have

iDL=iDA+iDBBy substituting the values of current equation we can write as,

KL(VGSL-VTNL)2 = KDA[2(VGSA- VTNA)VDSA- VDSA

2] + KDB[2(VGSB-VTNB)VDSB- VDSB

2]

Suppose two driver transister are identical, which implies that,KDA=KDB=KDVTNA=VTNB=VTNDAs we know VGSL=0Also from figure VGSA=VGSB=VDDVDSA=VDSB=V0By substituting all these parameters we can write above

equation as,

(-VTNL)2 = 2(KD/KL)[2(VDD-VTND)V0-VO2)Conclusion: The above equation suggested that when the both

the driver are in conducting mode, the effective aspectratioof the NOR gate is double. This further suggestedthat output voltage becomes slightly smaller when bothinputs are high. Because higher the aspect ratio lower theoutput.When all the inputs are high: design consideration!!

MDC

VGSC

iDC

MDCC

Three input

NOR gate

design

considerations

Three input NAND

gate design

considerations

At present, complementary MOS or CMOS has replaced NMOS at alllevel of integration, in both analog and digital applications.

The basic reason of this replacement is that the power dissipation inCMOS logic circuits is much less than in NMOS circuits, which makesCMOS very attractive.

Although the processing is more complicated for CMOS circuits thanfor NMOS circuits.

However, the advantages of CMOS digital circuits over NMOS circuitsjustify their use.

CMOS: the most abundant electronic devices on earth

Full rail-to-rail swing high noise margins

Logic levels not dependent upon the relative device sizes transistors can be minimum size ratio less

Always a path to Vdd or GND in steady state lowoutput impedance (output resistance in k range)large fan-out.

Extremely high input resistance (gate of MOS transistoris near perfect insulator) nearly zero steady-stateinput current

No direct path steady-state between power and ground no static power dissipation

Propagation delay function of load capacitance andresistance of transistors

CMOS properties


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CMOS Inverter:

Steady State Response

VDD

Rn

Vout = 0

Vin = V DD

VDD

Rp

Vout = 1

Vin = 0

VOL = 0

VOH= VDD

NMOS off

PMOS in non sat

NMOS in sat

PMOS in non

sat

NMOS in sat

PMOS in sat

NMOS in non

sat

PMOS in sat

NMOS in

nonsat

PMOS off

CMOS inverter design consideration

The CMOS inverter usually design to have,

(i) VTN =|VTP|

(ii) Kn/2(W/L)=Kp/2 (W/L)

But Kn> Kp (because n>p)

How equation (ii) can be satisfied?

This can achieved if width of the PMOS is made two orthree times than that of the NMOS device. This isvery important in order to provide a symmetricalVTC, results in wide noise margin.

Symmetrical properties of the

CMOS inverter


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CMOS inverter VTC

VCC

VCC

Vin

Vout

kp=kn

kp=5kn

kp=0.2kn

Increase W of PMOS

kp increasesVTC moves to right

Increase W of NMOS

kn increases

VTC moves to left

For VTH = Vcc/2

kn = kpWn 2Wp


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Effects of VIt adjustment

Result from changing kp/k

nratio:

Inverter threshold VIt Vcc/2

Rise and fall delays unequal

Noise margins not equal

Reasons for changing inverter threshold

Want a faster delay for one type of transition

(rise/fall) Remove noise from input signal: increase one

noise margin at expense of the other

Power Dissipation

Although there isn't power dissipation in theCMOS inverter when the output is either atlogic 0 or 1. However, during switching of theCMOS inverter from low logic 0 to logic 1,current flows and power is dissipated.

Usually CMOS inverter and logic circuit areused to drive other MOS devices byconnecting a capacitor across the output of a

CMOS inverter. This capacitor must be charged and

discharged during the switching cycle.

CMOS inverter power

Power has three components

Static power: when input isnt switching

Dynamic capacitive power: due tocharging and discharging of loadcapacitance

Dynamic short-circuit power: directcurrent from VDD to Gnd when bothtransistors are on

CMOS inverter static power

Static power consumption:

Static current: in CMOS there is no static current

as long as Vin < VTN or Vin > VDD+VTP

Leakage current: determined by off transistor

Influenced by transistor width, supply voltage,

transistor threshold voltagesVDD

VI


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Dynamic Power Dissipation and Total

Energy Stored in the CMOS Device

Case II: when the input is high and out put is low:

During switching all the energy stored in the loadcapacitor is dissipated in the NMOS device

because NMOS is conducting and PMOS is in

cutoff mode. The energy dissipated in the NMOS

inverter can be written as,

The total energy dissipated during one switching

cycle is,

The power dissipated in terms pf frquency can bewritten as

2

2

1DDLN VCE =

222

2

1

2

1DDLDDLDDLNPT VCVCVCEEE =+=+=

2

DDLTT

T VfCfEPt

EPtPE ===

This implied that the power dissipation in the CMOS inverter is directly

proportional to switching frequency and VDD2

Dynamic capacitive power

Formula for dynamic power:

Observations

Does not (directly) depend on device sizes

Does not depend on switching delay

Applies to general CMOS gate in which: Switched capacitances are lumped into CL Output swings from Gnd to VDD Input signal approximated as step function

Gate switches with frequency f

fVCP DDLdyn2=

Dynamic short-circuit power Short-circuit current flows from VDD to Gnd

when both transistors are on saturation mode

Plot on VTC curve:

VCC

VCCVin

Vout ID

Imax

Imax: depends onsaturation current

of devices

Inverter power consumption

Total power consumption

fVCPtot

IVftt

IVfVCP

PPPP

CCL

leakCC

fr

CCCCLtot

statscdyntot

2

max

2

~

2+

++=

++=


10/23


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Summary of the noise margin of a symmetrical

CMOS inverter

NML = VIL - VOLU (noise margin for low input)

NMH = VOHU - VIH (noise margin for high input)

Summary of the noise margin of asymmetrical

CMOS inverter

NML = VIL - VOLU (noise margin for low input)

NMH = VOHU - VIH (noise margin for high input)

4

CMOS Logic Circuits

Large scale integrated CMOS logiccircuits such as watched, calculators,and microprocessors are constructed byusing basic CMOS NOR and NANDgates. Therefore, understanding ofthese basic gates is very important forthe designing of very large scaleintegrated (VLSI) logic circuits.

7


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CMOS NOR gate

CMOS NOR gate can be

constructed by usingtwo parallel NMOSdevices and two seriesPMOS transistors asshown in the figure. Inthe CMOS NOR gatethe output is at logic 1when all inputs are low.

For all other possibleinputs, output is low orat logic 0.

8 Design considerations of CMOS NOR and

NAND symmetrical gate? In order to obtained symmetrical

switching times for the high-to-lowand low-to-high output transitions,

the effective conduction (design)parameters of the compositePMOS and composite NMOSdevice must be equal. For theCMOS NOR gate we can write as,

KCN=KCP

By recalling effective channel widthand effective channel lengthconcept we can effectiveconduction parameter for NMOSand PMOS for a CMOS NOR as,

Since Kn~2Kpp

p

N

n

LWK

LWK

=

222

2

pN L

W

L

W

=

2

22

NP L

W

L

W

=

8

or

For asymmetrical case switching time is long

NP L

W

L

W

=

2

1

For NAND gate:

Why we need

symmetrical

Gates?

t

Vout

Vin

input

waveform

output

waveform

tp

= (tpHL

+ tpLH

)/2

Propagation delay

t

50%

tpHL

50%

tpLH

tf

90%

10%

tr

signal slopes

Vin Vout

The propagation delay tp of a gate defines how quicklyit responds to a change at its input(s).

Propagation Delay Definitions


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Switching Time and Propagation

Delay Time The dynamic performance of a

logic circuit family ischaracterized by propagationdelay of its basic inverter. Thepropagation delay time isdefine as the average of low-to-high propagation delay timeand the high-to-low

propagation delay time. The propagation delay time is

directly proportional to theswitching time and increasesas the Fan-out increases.

Therefore, the maximum Fan-out is limited by the maximumacceptable propagation delaytime.

Each additional load gate increases the load capacitance their must be

charge and discharge as the driver gate changes state. This place a

practical limit on the maximum allowable number of load gates.

Switch-level model

For fall delay tphl, V0=Vcc, V1=Vcc/2

Lpplh

Lnphl

p

CC

CCp

CRtCRt

RCt

V

VRC

V

VRCt

69.069.0

)5.0ln(

lnln 21

0

1

==

=

=

=

Standard RC-delay

equations

Transmission Gates

Characteristics of NMOS transmission gate. Dynamicand static conditions.

Characteristics of CMOS Transmission gate.

In CMOS logic gate that a logic 1 istransmitted unattenuated through the CMOStransmission gate in contrast to the NMOStransmission gate.

Sequential Logic circuits; Characteristics of DynamicShift Registers and CMOS dynamic shift register.

7 Characteristics of NMOS transmission gate

If =VDD, VI=VDD, and initially, the output V0is 0and

capacitance CL is fully discharged.

Under these conditions, the terminal a acts as thedrain because its bias is VDD, and terminal bacts as the source because its bias is 0.

The gate to source voltage can be written asVGS=-VO or

VGS= VDD-VOAs CL charges up and Vo increases, the gate to

source voltage decreases. When the gate tosource voltage VGS become equal to thresholdvoltage VTN, the capacitance stop charging andcurrent goes to zero.

This implies that theVO=VO(max) when VGS=VTN

OrVO(max) = VDD-VTN

d S

G

This implies that output voltage never will be equal to VDD. ; rather it will be lower by VTN.

This is one of the disadvantage of an NMOS transmission gate when VI=high


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Why NMOS transmission gate does not remain in

a static condition?

The reverse leakagecurrent due to reverse

bias between terminal

b and ground begins

to discharge the

capacitor, and the

circuit does not

remain in a staticcondition.

VDD-Vt

sourcedrain

gate

CMOS Transmission Gate

A CMOAS transmission

gate can be constructed byparallel combination ofNMOS and PMOStransistors, withcomplementary gate signals.

The main advantage of theCMOS transmission gatecompared to NMOStransmission gate is to allowthe input signal to betransmitted to the outputwithout the thresholdvoltage attenuation.

CMOS

transmission

gate

Characteristics of a CMOS Transmission

gate (Cont.)

When VO=VDD-VTN, VGSN=VTN,

the NMOS transmission gate cutsoff and IDN=0.However, PMOS transistorcontinue to conduct, becauseVGSP of the PMOS is a constant(VGSP=VDD). In PMOS transistorIDP=0, when VSDP=0, which would be

possible only, if,

VO = VI = 5V

This implies that a logic 1 istransmitted unattenuated through

the CMOS transmission gateincontrast to the NMOS transmissiongate.

Drainsource

source Drain

Drainsource

source Drain

d S

G

NMOS transmission gate

CMOS transmission gate remains in a dynamic

condition.

If VO=VDD, then NMOSsubstrate to terminal b pn

junction is reverse biased and

capacitor CL can discharge.

If VO=0, then the PMOS terminalc-to-substrate pn junction isreverse biased and capacitanceCL can be charge to a positivevoltage.

This implies that the outputhigh or low of CMOS

transmission gate circuit donot remain constant with time(dynamicbehavior).


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Sequential Logic circuits

The logic circuits considered thus far are calledcombinational logic circuits. Their output depend onlyon the present value of input. This implies that these

circuit do not have memory.

Another class of the logic circuit that incorporatememory are called sequential logic circuits; that is,their output depend not only the present value of theinput, but also on the previous history of inputs. Shiftregistersand flip-flopsare typical examples of suchcircuits.

NMOS Dynamic Shift Registers

A shift register can beconstructed by thecombination of transmission

gates and inverters. If VI=VDD and 1=VDD, then a

logic 1=VDD-VTN would existat VO1.

The CL charges through MN1.

As VO1 goes high, VO2 goes low.

If 2 is high low will transmittedthrough MN2 and VO4 would

be at logic 1. Thus logic 1shiftedfrom input to output.

In shift register the input signal is

transmitted, or shifted, from theinput to the output during one clockcycle.


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CMOS Dynamic Shift Registers

The operation of this CMOS

shift register is similar tothe NMOS register exceptfor the voltage levels.

For example, when vI=1=VDD.Then vO1=VDD and vO2=0.when 2 goes high, then vo3switch to zero, vo4=vDD.

Thus input signal is shifted

to the output during oneclock cycle.

Figure 16.70

CMOS R-S Flip-Flop

The operation sequence of CMOS R-Sflip flop is same as NMOS.

For example: If S = logic 1 and R =logic 0, then MN1, is turned on, Mp1, iscut off, and

goes low.

With = R = logic 0, then both MN3and MN4 are cut off, both MP3 and Mp4are biased in a conducting state sothat the output Q goes high.

With Q = logic 1, MN2 is biased on,

Mp2 is biased off, and the flip-flop isin a set condition. When S goes low, MN1, turns off, but

MN2 remains conducting, so thestate of the flip-flop does not change.

Q

Q

Static D-type Flip-Flop

A D-type flip-flop is used to provide a delay. The logic bit on theD input is transferred to the output at the next clock pulse.

When the CMOS transmission gate turn off (=0), the pn junctionin the MN1 transmission gate transistor is reverse biased.


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Static vs Dynamic Storage Static storage

preserve state as long as the power is on

have positive feedback (regeneration) with aninternal connection between the output and the

input

useful when updates are infrequent (clock gating)

Dynamic storage

store state on parasitic capacitors

only hold state for short periods of time

(milliseconds)

require periodic refresh

usually simpler, so higher speed and lower power

Bipolar Digital Circuits

There are two major classes of bipolardigital logic circuits:

Emitter Coupled Logic (ECL)

Transister-TransisterLogic (TTL)

ECL is the fastest bipolar technology isused in applications where high speed isrequired such as high speed circuitsutilized in superconductors.

Analysis of ECL logic gate

Case I:If VX=VY=logic 1>VRUnder this condition Q1 and Q2 are

turn on and QR is off and logic 1output voltage is: VOR=VCC

Case II: If VX=Vy=logic 0


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ECL circuit has small Propagation

Delay Time The major advantage of ECL circuit is their

small propagation delay time. The change in voltage in ECL from logic 0 tologic 1 is very small which means that voltageacross the output capacitors do not have tochange up to VDD as changed in CMOScircuits. They are working between cutoff andactive mode.

Trade-offs for the small propagation delaytime are higher power dissipation and smallernoise margins compared to CMOS and TTL.

ECL has Very low

Noise Margin As we know the noise margins

are defined as

NML=VIL- VOL (noise marginfor low input)

NMH=VOH -VIH (noise marginfor high input)

From given figure we have,

VIL= -1.17V and VIH = - 0.93V,which are the point ofdiscontinuity in the VT curves.

Similarly the high logic level is

VOH =- 0.7V and the low logic valueis VOL= - 1.40V.

Using given data we have

NMH= 0.23V and NML=0.23V

The noise margins in ECL logic circuits are considerably

lower than those for NMOS and CMOS.

Diode transistor logic gate (DTL)

The ECL circuits have very low noise margin (i. e. 0.23V). In order toovercome this problem, TTL circuits have been introduced.

The basic building block of transistor transistor logic gate (TTL) isdiode transistor logic gate (DTL). Therefore, it is important to firstunderstand DTL.

Transistor-Transistor Logic (TTL)

In 1965, TTL was introduced. Basically, the usage ofdiodes in DTL was replaced with a transistor.

The main improvement in TTL design over DTL isimproved switching speed due to reduction in thepropagation delay time.

Pull down resister DTL

TTL

Pull down resister RB is no longer necessary, since The

excess minority carrier in the baser of Qo use Q1 as a path

to round


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TTL circuit with three emitter input

transistor.

In Isoplanar integrated circuit technology, the number of inputs can be increaseby diffuse more emitters in the same base region as shown in the above figure. Thisapproach reduce the chip area required for the TTL IC.The above circuit perform same NAND gate operation as its DTL counterpart.

Draw back of the basic TTL NAND gate

In all digital circuits there isalways existing a load capacitor,which is composed of the inputcapacitanceof the load circuitsand the capacitance of theinterconnect lines.

During circuit operation this loadcapacitor must be charged throughcollector pull-up resistor.

It has been estimated that the RCtime constant of a basic TTLcircuit is about 60ns, which islarge enough compared to thepropagation delay time (PDT) of acommercial TTL circuit.

TTL NAND gate: DC current voltage analysis

NAND gate : 0 0 1

1 0 1

0 1 1

1 1 0

Addition of totem pole output stage to

overcome the problem (cont.)

Case II: How the output transistorcharge the load capacitor quickly?

If VX=VY=logic 0

Under this biased mode Q1 is on, andQ2 and QO are in cut off, and

VB3= VCC= 5V, which is sufficient to turnon Q3 and D1

current in the output capacitor canflow through Q3 and D1 andcapacitance can be fully chargedquickly because the internalresistance of Q3 and D1 is very smallin conduction mode, so RC timeconstant of the capacitor will bevery short. In other words, PDT ofthe TTL circuit has been improved.

Totem pole


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FanoutIn digital circuits the main use of a logic

circuit is drive other similar type logic

gates to perform a complex logic

function. The maximum number of

similar type of logic gates that can beconnected to the logic gate output

without effecting proper circuit

operation is known as fanout.

For a given value of there is always

maximum allowable load current and

load circuits.

An another condition is the load current

iLL that Qo must sink from the load asshown in the figure.

The above concept will be explored by

following example.

How can we estimate maximum fanout for the output low

condition?: Example 17.10

How can we estimate maximum fanout for the output low

condition?: Example 17.10 (cont.) Schottky Transister-Transister Logic

(short storage time)

The speed of the TTL circuits thus far studied is limited bytwo mechanism:

i) All the transistors are in saturation mode while conducting,which limits the switching speed because the amount of timerequired to remove the storage charge from the base of thesaturated transistor is longer. The obvious solution of thisproblem is to use a BJTs in such a way that do not saturate.

ii) The resistances in the circuit, together with the varioustransistors and wiring capacitances, results relatively longertime constant which slow the speed of TTL circuit. The

solution of this prblem is to reduced all resistances.


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Characteristics of Schottky Clamped Transistor

Case I: When the transistor is inits active region, the basecollector junction is in reversebiased, which means thatSchottky diode is reverse biasand out of the circuit.

Case II: when the transistor istrying to switch into saturationregion, the base collector

junction become forward biased.Under this condition the basecollector voltage become equal

to diode turn on voltage (0.3V),which prevent the npn transistordeep into saturation by shuntingbase current through the diode.

3

11++= CBC iii

Schottky TTL NAND Circuit

As compared to standard TTL circuit aSchottky TTL circuit reveals a numberof variations.

i) Schottky clamped has been added toall transistors excerpt Q3 , which will,

never saturate because,

VCE3=VCE4+VBE3=0.3 + 0.8=1.1V

ii) All the resisters have been reducedalmost half the values used in thestandard circuit.

The above two new feature result in a

much shorter gate delay., which is theorder of 2 to 5ns, compared to 10 to 15ns for standard TTL circuits.

Advance Low Power Schottky TTL Inverter

Circuits (ALSTTL)

In ALSTTL the

propagation delaytime was reduceddown to 1.5ns, whilestill maintaining thelow power dissipation.The dimension of thestandard IC was alsoreduced from 5m to3m


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Problem 17.29aGiven that =50, refer figure 17.35(a)Calculate power dissipation in the circuit

when the input is at logic zero.(b) When the input is at logic 1

Sol: For TTL circuit for low logic VX = 0.4V andfor high logic Vx=3.6V

VE1 = Vx + VBE(Q1) = 0.4 + 0.7 = 1.1V

iE1

= (VCC

- VE1

)/R1

= (5-1.1)/40 = 0.0975mA. Thisis the total current flowing through thecircuit because all other transistors are incutoff mode.

P = iE1 . VCC= (0.0975)(5) = 0.487mW

Problem 17.29b

b) When the input is at logic 1

b) : VE1=VBE(Q2)+VBE(Q3)+VBE(Q5)=(0.7)(3)=2.1V

iR1=(VCC-VB1)/R1 =(5-2.1)/40 =0.0725mA

VC2=VCE(Q2)+VBE(Q3)+VBE(Q5)=0.4+0.7+0.7=1.8V

IR2=(VCC-VC2)/R2=(5.1.8)/R2 =0.065mA

VC3= VCE(Q3)+VBE(Q5)=0.4+0.7=1.1V

IR3= (VCC-VC3)/R3=(5-1.1)/1.5=0.26mA

P=VCC(IR1+iR2+iR3)=1.98mW

8

Introduction of BiCMOS Digital Circuits

BiMOS is a VLSI technology that combines bipolar and CMOSdevices into single integrated circuit.

By combining the two technologies BiMOS offers thefollowing advantage:

i) Low power dissipation comparable to CMOS ii) Improved speed comparable to TTL or ECL technology

iii) Large current driving capability comparable to TTL or ECL

iv) large noise margin similar to TTL technology

Disadvantage:

i) Highest cost

ii) Large fabrication cycle time up to thirty mask steps arecommon compared with ten to twenty for bipolar or CMOS.

Improved version of BiCMOS inverter

One serious disadvantage of the previouscircuit we discussed is that the absence ofcircuit path through which base charge canbe removed from the npn transistors (Q1 andQ

2), when they are turn off.

The solution of this problem is addition ofpull down resistors (R1 and R2) as shown inthe figure.

Resistor R2 provides an additional benefit:When VI high and after Q2 cuts off, Vocontinue to fall below VBE2 (on) because asmall current through MN and R2 continue toflow , which pulled the output to groundpotential.

Similarly, when output goes high, a very smallcurrent through Mp and R1 pulled up theoutput to VDD.

4


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lecturer 43-overview of ee 334

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