led mantech 2010 · microfluidic •our different activities: custom analysis (consulting), patents...

© 2012• 1

Copyrights © Yole Développement SA. All rights reserved. © 2012• 1

Copyrights © Yole Développement SA. All rights reserved.

Trends in LED manufacturing:

How to reduce LED

cost of ownership SEMICON Taiwan 2012

Pascal Viaud - CTO

75 cours Emile Zola, F-69100 Lyon-Villeurbanne, France

Tel: +33 472 83 01 80 – Fax: +33 472 83 01 83

Web: http://www.yole.fr

OSRAM OSRAM Aixtron OSRAM CREE Lumileds Verticle Inc Cascade Microtec

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Yole Développement in a nutshell

• Yole Developpement is a market , technology and strategy consulting company, founded in 1998. We are involved in the following areas:

• Our different activities: custom analysis (consulting), patents analysis, reverse engineering & reverse costing, reports publication, media business and Yole Finance services (M&A, due diligence, fund raising)

MEMS &

Imaging sensors

Photovoltaic

Advanced

Packaging

Microfluidic

& Med Tech

Power

Electronics

HB LED, LED & LD Wafers and Substrates

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History LED Industry is Entering its 3rd Growth Cycle

August 2012

http://www.amazon.com/gp/product/B007H7G6IE/ref=as_li_ss_tl?ie=UTF8&camp=1789&creative=390957&creativeASIN=B007H7G6IE&linkCode=as2&tag=oledinfo-20

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Packaged LED Revenue Forecast by Application

August 2012

Increase of penetration rate of LEDs Decrease of aftermarket volume (replacement) due to higher lifetime of LEDs

1

2

1 2

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SSL Upfront Cost:

Sticker Shock*:

<$1 $3-5 $20-$40

*All sources: 60 W equivalent ~ 800 lumens, warm White, tier 1 brand only, typical price in the US

Need to reduce $/lumen !

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The Path to Cost Reduction

Cost =

LED performance:

• Higher Efficiency (lumen/W)

• More light / chip (driving current)

$$

Lumen

Manufacturing Cost:

• Higher equipment throughput

• Higher yields

• Economy of scale

• Materials

> 4x ?

2-3x ?

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Testing and

Binning: Wafer

Level, Higher

throughputs

Thermal

Management:

New materials

for packaging

Encapsulation

Materials and Optics:

Ageing and optical

properties

20 Key Technologies & Research Areas Relative Impact on LED cost of ownership

Contacts/Electrodes:

Transparent

contacts/Electrode

materials and patterns

Contacts &

Electrodes:

p to n layer VIAS

Epitaxy – MOCVD:

Higher yields and

Throughputs - Improved

Material quality

Epitaxy: Cluster tools - New

Epi Technologies

Lithography:

Dedicated tools,

Higher

Throughput

Mirrors: Improve

reflectivity/electrical

properties

Mirrors:

Resonant

Cavities

Phosphors:

Conversion efficiency,

Color Rendering – “IP

free” phosphors

Phosphors:

Quantum dots

Phosphors Substrate

Separation: Laser Lift

Off, other separation

techniques

LED Performance

Manufacturing

Cost

Surface Texturation:

Patterned substrates /

Roughening

Surface Texturation:

Photonic and Quasi

Photonic Crystals

Current Droop

/ Green Gap /

LED Structures

LED on Si

Large

Diameters

Substrates:

4”, 6”, 8”

Other Alternative

substrates: GaN, ZnO,Engineered

substrates

Sources: Yole Développement

Wafer Level

Packaging:

Silicon TSC, Wafer

Level Optics

Die Singulation

Increased

throughputs and

yields

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Luminaire Cost Structure

LED is only one contributor but represents the

single largest opportunity for cost reduction:

Downlight picture: CREE LR6, Cost breakdown from DOE SSL roundtable 2011, Packaged LED pictures: Cree, Everlight, Osram, Philips Lumileds.

LED Component

45%

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Substrates: larger, patterned,…

Better use of reactor real estate + reduced edge

losses = 15 to 65% throughput improvement.

2” to 6” : better use of reactor real estate

(Aixtron)

Benefits of PSS for light extraction

have been extensively demonstrated.

PSS adoption is increasing fast,

despite IP concerns.

2” 6”

Cost / Wafer

(with 5 mask

levels)

$1 $1

Cost/TIE $1 $0.11

Downstream benefits on Lithography (full field):

In million of TIE / y 2010 2011 2012 2013

PSS 5.1 11.6 32.1 41.6

Std. Substrates 18.80 19.24 8.44 9.73

% PSS 21% 38% 79% 81%

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Substrates: LED-on-Silicon?

99.5% of GaN HB LED currently made on Sapphire, SiC but…

“If it can be made on Silicon, it will be made on Silicon”

Popular saying from the Semiconductor industry

Si wafers are less expensive than sapphire

Is this where the cost savings come from?

Example of a high power 1W HB-LED cost structure

(Source: Yole, System plus consulting)

~ 5-10%

depending on

type of LED

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LED-on-Si: Potential Cost Benefits

Benefit of Si would stem from switching to 8” and using fully

depreciated & highly automated CMOS fabs.

Assumptions:

• Identical yields

• 200 mm Silicon processed in fully

depreciated CMOS fab

- 60% at the die level?

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Is Silicon Taking Over (yet)?

Silicon 2” 4” 6”

Sapphire, SiC ?

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LED-On-Si: Some Players:

Bridgelux 8” LED Epiwafer Osram 6” LED Epiwafer Lattice Power Led-On-Si chip

• Most LED makers have LED on Si research programs:

Osram, Samsung, Lumileds, Epistar…

• Bridgelux + Toshiba committed to Si transition in Oct. 2012,

Lattice Power already in production.

http://i.bnet.com/blogs/gan_on_silicon_8_inch_wafer_610x456.jpeg

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LED-On-Si: Potential Benefits

CMOS processing Wafer Price Higher Thermal

Conductivity

Non Transparent

Material

• Highly automated,

efficient

• Large process

toolbox

Silicon is cheaper

than sapphire and

will likely remain so.

(Sapphire = hard

material + high

melting point)

Better

Temperature

Homogeneity

More accurate

Surface

Temperature

Measurement

• Low cost: 10x

improvement vs.

2” sapphire (!?)

• New LED

structures ?

• Low wafer price

• 200 mm available

• But not semi

standard (yet?)

Improved

Binning Yield ?

Improved

Run/Run

repeatability ?

Direct manufacturing cost Potential yield benefits

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LED-On-Si: Main Challenges

Lattice

Mismatch

Thermal Expansion

Coefficient Mismatch Melt Back

Blue Light

Absorption by Wafer

Impact Epitaxial

Defect

• Wafer Bow

• Inhomogeneity

• Layer Cracking

Poor

epitaxy Poor light output

Sapphire

Bad Bad No No

Silicon

Worse Much worse Yes Yes

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LED-On-Si: Conditions for Success

• #1: Must equal LED on Sapphire

performance.

• #2: Must reach similar manufacturing

yields: the major issue.

• #3: Must be compatible with CMOS,

ideally on 200 mm wafers: some

problems (gold contamination, testing,

dicing…)

?

?

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Will LED-on-Si Happen?...

• It’s a cost game: $/lumen rules.

• Si enables 200 mm in CMOS fabs

• Sapphire/SiC = moving targets!

– Price, PSS…

Price

declining

8” possible (?)

(Yole Developpement)

Monocrystal

If technology hurdles are cleared, LED-

On-Si will be adopted by some LED

manufacturers but not necessarily

become the standard.

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LED Manufacturing Yields

50% of LED chips going into the trash ?

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The Cost of Yields

Bad dies have to be processed all the way through singulation...

Front end Level 1: - Lithography - Etching - Metallization

Front End Level 0: - - Epitaxy Back End Level 0: - Bonding

Back End Level 0: - Epitaxial substrate removal

Back End Level 0: - Dicing

Back End Level 0: - Testing and binning

Stretchable tape

“Bad” areas

Defective die

Bin #1

Bin #2

Bin #3

Bin #n

Defective &

Rejected

Dice

Pick and Place

… and carry the same cost as good die!

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Yields: MOCVD

Direct Saving (Yield + Throughput improvement) + Downstream savings!

Aixtron G5HT 2” x 56 configuration Veeco Maxbright Cluster tools: 2 to 4 reactors for high capacity,

throughput, footprint and capital efficiency.

The single largest opportunity for HB LED cost reduction?

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MOCVD Cost of Ownership Trends

Cost reduction will be achieved through a combination of

increased reactor throughput, automation, better yields,

improved reliability (uptime) and utilization of precursors.

Aixtron: 2011 – 2016

LED Epitaxy cost reduction roadmap

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Dedicated Tools for LED:

LED industry still using lots of old refurbished semiconductor

tools Low yields / performance

X Dry etching for

PSS and GaN

(Corial)

Evaporator for ITO and metal

LED deposition (SNTEK) Suss MA100/150e

Gen2 Litho system

EVG LED wafer

bonder

LED industry now large enough to justify development of

dedicated tools!

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Single Large

Die (1 die, typical dimension: 0.5

to 1.5 mm)

Packages Designs

Single or Multi

“Jumbo Die” 1 to 6 dice, typical dimension

2 to 5 mm each)

Small/medium

COB Array (20 to 100 dice, typical

dimension: 250 to 500 um each)

Lumileds

Cree

Osram

Lumileds

Cree

Osram

Osram

Luminus

Device

Luminus

Device

Luminus

Device

Multiple Large

Dice (3 to 25 dice, typical

dimension: 0.5 to 1.5 mm each)

Edison Opto

Sharp

Mid Power

(1-2 die, typical

dimension: 0.3 to 0.8

mm)

http://www.cree.com/press/enlarge.asp?i=1317907138192

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Standardization can reduce cost:

• Mid-power LED price decreased dramatically in

2011 under the combined effects of:

– Package standardization

– Very large volumes.

– High level of competition (over supply)

Highly competitive $/lumen ratio

2 Chip 5630 packages

(Seoul Semiconductor)

5630 package for lighting

(Philips Lumileds )

Lighting applications require high power packages, right?…

Linear Lighting

(Senslite Corporation) Retrofit bulb

Mid power packages crossing over from display to lighting

http://www.ledsmagazine.com/news/9/4/4/Philipsmidpower04112012

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System Design Choice

• Design choice are often application dependant.

• But in some cases, multiple designs and choice of package

are possible for a single application:

Package design can improve yield and reduce LED cost of ownership



















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Conclusion: The Path to Cost Reduction

System approach:

• Chips performance impacts package cost of ownership.

• Package design impacts chip yields.

Equipment:

• Tools designed specifically for LED manufacturing offer

improved throughputs and cost of ownership.

Substrates:

• Larger wafers, LED-On-Si have potential … but still

yield/technology limitations.

• And Sapphire performance are improving (PSS).

Manufacturing Philosophy

• Semiconductor “Best Practices” now entering LED industry:

automation, cassette/cassette, MES…

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THANK YOU!

Please visit our booth #1327

www.i-micronews.com

Contacts Asia:

• Taiwan/China: Mei-Ling TSAI ([email protected])

• Korea: Hailey YANG ([email protected])

• Japan: Yutaka KATANO ([email protected])

led mantech 2010 · microfluidic •our different activities: custom analysis (consulting), patents...

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