lesson 2 - isa - ulisboa · memory technologies slides by: pedro tomás additional reading:...

MEMORY

TECHNOLOGIESSlides by: Pedro Tomás

Additional reading: Computer Architecture: A Quantitative Approach”, 5th edition, Chapter 2 and Appendix B, John L. Hennessy and David A. Patterson, Morgan Kaufmann, 2011

ADVANCED COMPUTER ARCHITECTURESARQUITECTURAS AVANÇADAS DE COMPUTADORES (AAC)

Advanced Computer Architectures, 2014

Outline

2

Memory technologies:

SRAM

DRAM

SDRAM

DDR / DDR2 / DDR3

FLASH


Random Access Memory (RAM)

Organization3

(row,column) addressing

Column decode

Ro

w d

eco

de

n/2

Sense amplifiers and I/O Data

2n/2 x 2n/2 Memory elements

n-bit address

n/2


Random Access Memory (RAM)

Memory elements4

Static RAM (SRAM)

Fast memory used on caches

Dynamic RAM (DRAM)

Larger capacity, but slower

Requires refreshing (around 1% of time)

Synchronous DRAM (SDRAM)

Synchronous DRAM memories

Double Data Rate SDRAM (DDR)

Synchronous Data Ram with read/write on both clock edges


Memory Elements

Static RAM (SRAM)5

Static Random Access RAM (SRAM)

Random access memories that can statically retain information

CMOS circuit for a SRAM cell (1 bit storage)

Total of 6 transistors

BLBL

WL

VDD

QQ


Memory Elements

SRAM control signals6

ADDRESS ADDRESS ADDRESS

DOUT DOUT DIN

tAA tHZ

tAA

tOE

tACS

tDS

tcw

END

CS

OE

DOUT/IN

WE_L = HIGH

WE

Tcycle = Taccess


Memory Elements

Dynamic RAM (DRAM)7

Single transistor + capacitor per cell

Less area per cell larger capacity

Limited charge on the CS capacitor

reduces the cell output current, which

leads to longer reading times, i.e., to a

slower memory

Leakage current drains the capacitor and

may lead to information losses

imposes periodic refreshing of the memory

element

Reading the element reduces the charge

DRAM memory controllers use reading times

to refresh the contents of the cell

CS

WL

CL

BL

11

)(1

max'0'

max

'1'

VVV

C

CVVV

CC

CVCVV

CVCVQ

pre

S

Lpre

LS

LpreSC

f

LpreSCT


Memory Elements

DRAM access and refreshing8

DRAM refreshing must be made periodically

Typical refreshing times are around 8ms

DRAM memories typically spend 1% of time refreshing the data

Whenever a given cell is activated, the whole line is refreshed

Saves clock cycles required for data refreshing

Reading cycle period can be divided into:

Pre-charge time: around 30%

Access time: around 70%

Read/writing requires:

Selecting the line

Activating the column

Read/Write


Memory Elements

DRAM control signals9

Reading data

from a DRAM

memory in

burst mode


Memory Elements

Synchronous DRAM (SDRAM)10

Synchronous access

Allows a burst mode where a new element can be read/written in

each clock cycle


Memory Elements

Double Data RAM (DDR)11

Keeping a low clock frequency allows for reduced the signal integrity on the circuit board connecting the memory to the controller

To increase bandwidth:

Double data rate by using both rising and falling edges

Uses a bus width of 64-bits

DDR Maximum transfer rate (using burst mode):

Memory bus frequency

X

2 (Dual data rate)

X

8 Bytes (bus data width is 64 bits)

=

16 x fCLK Bytes per second


Memory Elements


DDR2 memories:

Use an internal clock which is half the memory output bus clock

Allows to increase the bus clock frequency (thus doubling data rate), and

decrease power consumption

DDR3 memories:

Allows a bus clock frequency which is 4 times the internal clock

Note: depending on memory, access times for the 1st word in a DDR3 memory is 5-14 internal clock cycles

Bus word

width

Max. #words

per clock cycle

Bus clock

frequencyPeak bandwidth(assuming fCLK=100MHz)

DDR(DDR type 1)

64 bits(8 Bytes)

2(transfer data in both

rising and falling edges)

fCLK 1600 MB/s

DDR2(DDR type 2)

2fCLK 3200 MB/s

DDR3(DDR type 3)

4fCLK 6400 MB/s


Memory Elements


Standard

name

Memory

clock

Cycle

time

I/O bus

clock

Module

name

Peak Transfer

Rate

Timings

(in clock cycles)

Column Access

Latency

(MHz) (ns) (MHz) (MB/s)Column address

to data output

Row activate to

read/write

Row pre-charge

to activae(ns)

(1) (2) = 1/(1) (3) = (1) x 4 (5) (6) = (1) x 8 x 64/8 (7) (8) (9) (10) = (2)/4 x (7)

DDR3-800D100,00 10,00 400,00

PC3-6400(DDR 800MHz)

64005 5 5 12,50

DDR3-800E 6 6 6 15,00

DDR3-1066E

133,33 7,50 533,33PC3-8500

(DDR 1067MHz)8533

6 6 6 11,25

DDR3-1066F 7 7 7 13,13

DDR3-1066G 8 8 8 15,00

DDR3-1333F

166,67 6,00 666,67PC3-10600

(DDR 1333MHz)10667

7 7 7 10,50

DDR3-1333G 8 8 8 12,00

DDR3-1333H 9 9 9 13,50

DDR3-1333J 10 10 10 15,00

DDR3-1600G

200,00 5,00 800,00PC3-12800

(DDR 1600MHz)12800

8 8 8 10,00

DDR3-1600H 9 9 9 11,25

DDR3-1600J 10 10 10 12,50

DDR3-1600K 11 11 11 13,75

DDR3-1866J

233,33 4,29 933,33PC3-14900

(DDR 1866MHz)14933

10 10 10 10,71

DDR3-1866K 11 11 11 11,79

DDR3-1866L 12 12 12 12,86

DDR3-1866M 13 13 13 13,93

DDR3-2133K

266,67 3,75 1066,67PC3-17000

(DDR 2133MHz)17067

11 11 11 10,31

DDR3-2133L 12 12 12 11,25

DDR3-2133M 13 13 13 12,19

DDR3-2133N 14 14 14 13,13


Memory Elements

Cost per GB14

DRAM size increased by multiples of four approximately once every three

years until 1996, and thereafter considerably slower. The improvements in

access time have been slower but continuous, and cost roughly tracks density

improvements, although cost is often affected by other issues, such as

availability and demand. The cost per gigabyte is not adjusted for inflation.


Memory Elements

Access time vs size15

Reference values for a 2013 personal computer

Registers: Flip-flops

L1/L2/L3 Cache: SRAM

RAM Memory: DDR3 DRAM

CC – Clock Cycle

Most expensive

Cost per byte

Least Expensive

Access Time(Reference values)

Moth

erboar

d

(North

bridge

)

L1 Cache(32KB+32KB)

Registers

10ms (20 000 000 CCs)

<100µs (100 000 CCs)

70ns (140 CCs)

2ns (3-4 CCs)

0,5ns (1 CC)CPU clock period of 0,5 ns

(fCLK = 2 GHz)

L2 Cache(256KB)

7ns (14 CCs)

L3 Cache(8 MB)

22ns (44 CCs) Chip

Core

RAM Memory(8 GB)

Moth

erboar

d

(South

bridge

)Solid State Hard Disk (SSD)(256 GB)Magnetic Hard Disk Drive (HDD)(2 TB)


Interconnection hierarchy

16

Note: actual architecture

depends on the processor

model

Hierarchical interconnections:

closest to the CPU faster and dedicated interconnections

More on memories:

Cache memories

Next lesson17

lesson 2 - isa - ulisboa · memory technologies slides by: pedro tomás additional reading:...

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