Lesson 4: “Just like LEGO”

The NAND gate

“Reading” CMOS gates

Designing CMOS gates

Logic

Paulo Moreira Gates 3

NAND 2-inputs

A

Y

B

A B Y0 0 10 1 11 0 11 1 0

NAND

“Gates areinverters indisguise!”

“Gates areinverters indisguise!”

Paulo Moreira Gates 4

NAND 3-inputs

A

Y

B

C

NAND 3 inputs

Pu

ll d

ow

n <

=>

3 o

n Pu

ll u

p <

=>

1 o

nn

n

n

ppp

n/3

p

"Delay equivalent" inverter

Paulo Moreira Gates 5

NAND 3-inputs

A

Y

B

C

NAND 3 inputs

n

n

n

ppp

Bulk effect

Stray capacitance

Use transistorsclose to the outputfor critical signals

NAND: Switching Time, Propagation Delay

tLow2High= Rp/N (N*Cout,p+Cout,n/N+Cload)

tHigh2Low= N*Rn (Cout,n/N+N*Cout,p+Cload)Gate Delay=1/2*(tL2H+ tH2L)

n,p : n-channel, p-channel transistors.

Rp,Rn: Ron of respective transistors.

N = number of Inputs.

Estimation of Gate Delay:

Gate Delay = K1(pSec) +K2 (pSec*um/fF)* Cload / Wn

Wn=Width of n-channel FET (Wp/Wn=constant)

K1 & K2 determined from spice simulation of cascaded inverters.

Wp/Wn K1 K21 39 12.82 38 8.783 41 6.35

When FETs in series, the effective W is respectively smaller.Cload calculated from Fan-out * Capacity(per Gate) + Capacity of Line.

Paulo Moreira Gates 8

NAND 3-inputs

Minimumdistance

Sharedsource/drain

diffusions

A

B

C

Bad: high straycapacitance andlarge area

Good: minimumstray capacitaceand small area

Paulo Moreira Gates 9

NAND 3-inputs

Paulo Moreira Gates 10

“Reading” CMOS gatesAOI

Y

A

A

B

B

C

C

D

D

PM

OS

activa

ted

by "

0"

NM

OS

activate

d b

y "

1"

Pu

ll u

pP

ull

do

wn

(A+B)

(C+D)

(A+B)(C+D) (AB)(CD) AB+CD

(AB)

(CD)

AB + CD AB + CD

The NMOS pull-down => inversion

Paulo Moreira Gates 11

Designing CMOS gates

00 01 11 10

1 1 1 1

1 0 0 0

0 0 0 0

1 1 1 1

Y

00

01

11

01

AB

CD

00 01 11 10

1 1 1 1

1 0 0 0

0 0 0 0

1 1 1 1

Y

00

01

11

01

AB

CD

Compound gate

PM

OS

activate

d b

y "

0"

NM

OS

activate

d b

y "

1"

Pull

up

Pull

dow

n

Y

A B

D

C

D

C

B

A

D + A B C

D (A + B + C)

Y = D (A + B + C)

Paulo Moreira Gates 12

Complex CMOS gates

• Can a compound gate be arbitrarily complex?– NO, propagation delay is a strong function of fan-in:

– FO Fan-out, number of loads connected to the gate: • 2 gate capacitances per FO + interconnect

– FI Fan-in, Number of inputs in the gate:• Quadratic dependency on FI due to:

– Resistance increase

– Capacitance increase

– Avoid large FI gates (Typically FI 4)

t p a FO a FI a FI 0 1 22

NAND: Switching Point

VSP=(n / (N*p))^1/2*VT,n+(VDD-VT,p) --------------------------------------

1+(n / (N*p))^1/2

N = number of Inputs.n,p : n-channel, p-channel transistors.