lic lab manual ariv complete

8/3/2019 Lic Lab Manual Ariv Complete

1/78

THIRUMALAI

ENGINEERING

COLLEGEDEPARTMENT OF ELECTRICAL

& ELECTRONICS

ENGINEERING

KILAMBI , KANCHIPURAM -

631551

LAB MANUAL

CLASS : II YEAR EEE

SEMESTER : IV SEMESTER

ACADEMIC YEAR : 2011 2012

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SUBJECT CODE : 131452

SUBJECT : LINEAR AND DIGITAL

INTEGRATEDCIRCUITS LAB

AND GATE

LOGIC DIAGRAM:

PIN DIAGRAM OF IC 7408 :

CIRCUIT DIAGRAM:

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Expt. No.1 STUDY OF BASIC DIGITAL ICSDate:

AIM:

To verify the truth table of basic digital ICs of AND, OR, NOT, NAND, NOR,

EX-OR gates.

APPARATUS REQUIRED:

S.No Name of the Apparatus Range Quantity

1. AND gate IC 7408 1

2. OR gate IC 7432 1

3. NOT gate IC 7404 1

4. NAND gate IC 7400 1

5. NOR gate IC 7402 1

6. EX-OR gate IC 7486 1

7. Connecting wires As required

THEORY:

a. AND gate:

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An AND gate is the physical realization of logical multiplication

operation. It is an electronic circuit which generates an output

signal of 1 only if all the input signals are 1.

b. OR gate:

An OR gate is the physical realization of the logical addition


signal of 1 if any of the input signal is 1.

c. NOT gate:

A NOT gate is the physical realization of the complementation


signal which is the reverse of the input signal. A NOT gate is also

known as an inverter because it inverts the input.

TRUTH TABLE:

S.N

o

INPUT OUTPUT

A B Y = A . B

1. 0 0 0

2. 0 1 0

3. 1 0 0

4. 1 1 1

OR GATE

LOGIC DIAGRAM:


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d. NAND gate:

A NAND gate is a complemented AND gate. The output of the NAND

gate will be 0 if all the input signals are 1 and will be 1 if any

one of the input signal is 0.

e. NOR gate:

A NOR gate is a complemented OR gate. The output of the OR gate

will be 1 if all the inputs are 0 and will be 0 if any one of the

input signal is 1.

f. EX-OR gate:

An Ex-OR gate performs the following Boolean function,

A B = ( A . B ) + ( A . B )

It is similar to OR gate but excludes the combination of both A and B

being equal to one. The exclusive OR is a function that give an

output signal 0 when the two input signals are equal either 0 or

1.

PROCEDURE:

1. Connections are given as per the circuit diagram

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1. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.2. Apply the inputs and verify the truth table for all gates.

CIRCUIT DIAGRAM:

TRUTH TABLE:

S.N

o

INPUT OUTPUT

A B Y = A + B

1. 0 0 0

2. 0 1 1

3. 1 0 1

4. 1 1 1

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NOT GATE

LOGIC DIAGRAM:


CIRCUIT DIAGRAM:

TRUTH TABLE:

INPUT OUTPUT

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S.N

oA Y = A

1. 0 1

2. 1 0

NAND GATE

LOGIC DIAGRAM:


CIRCUIT DIARAM:

TRUTH TABLE:

INPUT OUTPUT

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S.N

oA B Y = (A . B)

1. 0 0 1

2. 0 1 1

3. 1 0 1

4. 1 1 0

NOR GATE

LOGIC DIAGRAM:


CIRCUIT DIAGRAM:

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TRUTH TABLE:

S.N

o

INPUT OUTPUT

A B Y = (A + B)

1. 0 0 1

2. 0 1 0

3. 1 0 0

4. 1 1 0

EX-OR GATE

LOGIC DIAGRAM


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CIRCUIT DIAGRAM:

TRUTH TABLE:

S.No

INPUT OUTPUT

A B Y = A B

1. 0 0 0

2. 0 1 1

3. 1 0 1

4. 1 1 0

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RESULT:

The truth table of all the basic digital ICs were verified.

LOGIC SYMBOL: RS FF

CIRCUIT DIAGRAM: RS FF

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Ex.NO:1(b) STUDY OF FLIP FLOPSDate:

AIM:

To verify the characteristic table of RS, D, JK, and T Flip flops.

APPARATUS REQUIRED:


1. Digital IC trainer kit - 1

2. NOR gate IC 7402 1


4. AND gate ( three input ) IC 7411 1

5. NAND gate IC 7400 1

6.Connecting wires - As

required

THEORY:

A Flip Flop is a sequential device that samples its input signals and

changes its output states only at times determined by clocking signal.

Flip Flops may vary in the number of inputs they possess and the manner

in which the inputs affect the binary states.

RS FLIP FLOP:

The clocked RS flip flop consists of NAND gates and the output changes its

state with respect to the input on application of clock pulse. When the

clock pulse is high the S and R inputs reach the second level NAND gates

in their complementary form. The Flip Flop is reset when the R input high

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and S input is low. The Flip Flop is set when the S input is high and R

input is low. When both the inputs are high the output is in an

indeterminate state.

D FLIP FLOP:

To eliminate the undesirable condition of indeterminate state in the SR

Flip Flop when both inputs are high at the same time, in the D Flip Flop

the inputs are never made equal at the same time. This is obtained by

making the two inputs complement of each other.

CHARACTERISTIC TABLE: RS FF

CLOCK

PULSE

INPUT PRESENT

STATE

(Q)

NEXT

STATE(Q+1)

STATUSS R

1 0 0 NC NC NO CHANGE

2 0 0 NC NC

3 0 1 0 0 RESET

4 0 1 1 0

5 1 0 0 1 SET

6 1 0 1 1

7 1 1 X X UNDEFINED

8 1 1 X X

LOGIC SYMBOL: D FF

CIRCUIT DIAGRAM: D FF

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JK FLIP FLOP:

The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop.

JK inputs behave like S and R inputs to set and reset the Flip Flop. The

output Q is ANDed with K input and the clock pulse, similarly the output Q

is ANDed with J input and the Clock pulse. When the clock pulse is zero

both the AND gates are disabled and the Q and Q output retain their

previous values. When the clock pulse is high, the J and K inputs reach

the NOR gates. When both the inputs are high the output toggles

continuously. This is called Race around condition and this must be

avoided.

T FLIP FLOP:

This is a modification of JK Flip Flop, obtained by connecting both inputs J

and K inputs together. T Flip Flop is also called Toggle Flip Flop.

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CHARACTERISTIC TABLE: D FF

CLOCK

PULSE

INPUT

D

PRESENT

STATE (Q)

NEXT

STATE(Q+1)

STATUS

1 0 0 0

2 0 1 0

3 1 0 1

4 1 1 1

LOGIC SYMBOL: JK FF

CIRCUIT DIAGRAM: JK FF

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CHARACTERISTIC TABLE: JK FF

CLOCK

PULSE

INPUT PRESENT

STATE (Q)

NEXT

STATE(Q+1)

STATUS

J K

1 0 0 0 0 NO CHANGE

2 0 0 1 1

3 0 1 0 0 SET

4 0 1 1 0

5 1 0 0 1 RESET

6 1 0 1 1

7 1 1 0 1 TOGGLE

8 1 1 1 0

LOGIC SYMBOL: T FF

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CIRCUIT DIAGRAM: T FF

CHARACTERISTIC TABLE: T FF

CLOCK INPUT PRESENT NEXT STATUS

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PULSE T STATE (Q) STATE(Q+1)

1 0 0 0

2 0 1 0 TOGGLE

3 1 0 1

4 1 1 0

PROCEDURE:

1. Connections are given as per the circuit diagrams.

2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and observe the status of all the flip flops.

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RESULT:

The Characteristic tables of RS, D, JK, T flip flops were verified.

CIRCUIT DIAGRAM:

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Expt. No.2 IMPLEMENTATION OF BOOLEAN FUNCTIONSDate:

AIM:

To design the logic circuit and verify the truth table of the given Boolean

expression,

F (A,B,C,D) = (0,1,2,5,8,9,10)

APPARATUS REQUIRED:


1. AND gate IC 7408

2. OR gate IC 7432

3. NOT gate IC 7404

4. NAND gate IC 7400

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5. NOR gate IC 7402

6. EX-OR gate IC 7486

7.Connecting wires As

required

DESIGN:

Given , F (A,B,C,D) = (0,1,2,5,8,9,10)

The output function F has four input variables hence a four variable

Karnaugh Map is used to obtain a simplified expression for the output.

From the K-Map,

F = B C + D B + A C D

Since we are using only two input logic gates the above expression can be

re-written as,

F = C (B + A D) + D B

Now the logic circuit for the above equation can be drawn.

TRUTH TABLE:

S.N

o

INPUT OUTPUT

A B C DF=DB+C(B+

AD)

1. 0 0 0 0 1

2. 0 0 0 1 1

3. 0 0 1 0 1

4. 0 0 1 1 0

5. 0 1 0 0 0

6. 0 1 0 1 1

7. 0 1 1 0 0

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8. 0 1 1 1 0

9. 1 0 0 0 1

10. 1 0 0 1 1

11. 1 0 1 0 1

12. 1 0 1 1 0

13. 1 1 0 0 0

14. 1 1 0 1 0

15. 1 1 1 0 0

16. 1 1 1 1 0

PROCEDURE:

1. Connections are given as per the circuit diagram2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for the given Boolean

expression.

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RESULT:

The truth table of the given Boolean expression was verified.

HALF ADDER

TRUTH TABLE:

S.No

INPUT OUTPUT

A B S C

1. 0 0 0 0

2. 0 1 1 0

3. 1 0 1 0

4. 1 1 0 1

DESIGN:

From the truth table the expression for sum and carry bits of the output

can be obtained as,

Sum, S = A B

Carry, C = A . B

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CIRCUIT DIAGRAM:

Expt. No. 3(a) IMPLEMENTATION OF HALF ADDER & FULL

ADDER Date:

AIM:

To design and verify the truth table of the Half Adder & Full Adder circuits.

APPARATUS REQUIRED:


1. AND gate IC 7408

2. OR gate IC 7432

3. NOT gate IC 7404



THEORY:

The most basic arithmetic operation is the addition of two binary digits.

There are four possible elementary operations, namely,

0 + 0 = 0 ; 0 + 1 = 1; 1 + 0 = 1; 1 + 1 = 102

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The first three operations produce a sum of whose length is one digit, but

when the last operation is performed the sum is two digits. The higher

significant bit of this result is called a carry and lower significant bit is

called the sum.

HALF ADDER:

A combinational circuit which performs the addition of two bits is called

half adder. The input variables designate the augend and the addend bit,

whereas the output variables produce the sum and carry bits.

FULL ADDER:

A combinational circuit which performs the arithmetic sum of three input

bits is called full adder. The three input bits include two significant bits

and a previous carry bit. A full adder circuit can be implemented with two

half adders and one OR gate.

FULL ADDER

TRUTH TABLE:

S.N

o

INPUT OUTPUT

A B C SUM CARRY

1. 0 0 0 0 0

2. 0 0 1 1 0

3. 0 1 0 1 0

4. 0 1 1 0 1

5. 1 0 0 1 0

6. 1 0 1 0 1

7. 1 1 0 0 1

8. 1 1 1 1 1

DESIGN:

From the truth table the expression for sum and carry bits of the output

can be obtained as,

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SUM = ABC + ABC + ABC + ABC

CARRY = ABC + ABC + ABC +ABC

Using Karnaugh maps the reduced expression for the output bits can be

obtained as,

SUM

SUM = ABC + ABC + ABC + ABC = A B C

CARRY

CARRY = AB + AC + BC

CIRCUIT DIAGRAM:

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PROCEDURE:

1. Connections are given as per the circuit diagrams.2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for the half adder and full

adder circuits.

RESULT:

The design of the half adder and full adder circuits was done and their

truth tables were verified.

HALF SUBTRACTOR

TRUTH TABLE:

S.N

o

INPUT OUTPUT

A B DIFF BORR

1. 0 0 0 0

2. 0 1 1 1

3. 1 0 1 0

4. 1 1 0 0

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DESIGN:

From the truth table the expression for difference and borrow bits of the

output can be obtained as,

Difference, DIFF = A B

Borrow, BORR = A . B

CIRCUIT DIAGRAM:

Expt. No. 3(b) IMPLEMENTATION OF HALF SUBTRACTOR & FULL

SUBTRACTOR Date:

AIM:

To design and verify the truth table of the Half Subtractor & Full

Subtractor circuits.

APPARATUS REQUIRED:


1. AND gate IC 7408

2. OR gate IC 7432

3. NOT gate IC 7404

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THEORY:

The arithmetic operation, subtraction of two binary digits has four

possible elementary operations, namely,

0 - 0 = 0; 0 - 1 = 1 with 1 borrow; 1 - 0 = 1; 1 - 1 = 0

In all operations, each subtrahend bit is subtracted from the minuend bit.

In case of the second operation the minuend bit is smaller than the

subtrahend bit, hence 1 is borrowed.

HALF SUBTRACTOR:

A combinational circuit which performs the subtraction of two bits is

called half subtractor. The input variables designate the minuend and the

subtrahend bit, whereas the output variables produce the difference and

borrow bits.

FULL SUBTRACTOR:

A combinational circuit which performs the subtraction of three input bits

is called full subtractor. The three input bits include two significant bits

and a previous borrow bit. A full subtractor circuit can be implemented

with two half subtractors and one OR gate.

FULL SUBTRACTOR

TRUTH TABLE:

S.N

o

INPUT OUTPUT

A B C DIFF BORR

1. 0 0 0 0 0

2. 0 0 1 1 1

3. 0 1 0 1 1

4. 0 1 1 0 1

5. 1 0 0 1 0

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6. 1 0 1 0 0

7. 1 1 0 0 0

8. 1 1 1 1 1

DESIGN:

From the truth table the expression for difference and borrow bits of the

output can be obtained as,

Difference, DIFF= ABC + ABC + ABC + ABC

Borrow, BORR = ABC + ABC + ABC +ABC

Using Karnaugh maps the reduced expression for the output bits can be

obtained as,

DIFFERENCE

DIFF = ABC + ABC + ABC + ABC = A B C

BORROW

BORR = AB + AC + BC

CIRCUIT DIAGRAM:

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PROCEDURE:

1. Connections are given as per the circuit diagrams.2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for the half subtractor

and full subtractor circuits.

RESULT:

The design of the half subtractor and full subtractor circuits was done andtheir truth tables were verified.

CIRCUIT DIAGRAM:

ODD PARITY GENERATOR

ODD PARITY GENERATOR

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TRUTH TABLE (ODD PARITY GENERATOR):

S.N

o

INPUT

( Three bit

message)

OUTPUT

( Odd Parity bit)

A B C P

1 0 0 0 1

2 0 0 1 0

3 0 1 0 0

4 0 1 1 1

5 1 0 0 0

6 1 0 1 1

7 1 1 0 1

8 1 1 1 0

Ex. No. 4 PARITY GENERATOR & CHECKERDate:

AIM:

To design and verify the truth table of a three bit Odd Parity generator

and checker.

APPARATUS REQUIRED:


1. Digital IC trainer kit 1


3. NOT gate IC 7404


required

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THEORY:

A parity bit is used for the purpose of detecting errors during transmission

of binary information. A parity bit is an extra bit included with a binary

message to make the number of 1s either odd or even.

The message including the parity bit is transmitted and then checked at

the receiving end for errors. An error is detected if the checked parity

does not correspond with the one transmitted. The circuit that generates

the parity bit in the transmitter is called a parity generator and the circuit

that checks the parity in the receiver is called a parity checker.

In even parity the added parity bit will make the total number of 1s an

even amount and in odd parity the added parity bit will make the total

number of 1s an odd amount.

In a three bit odd parity generator the three bits in the message together

with the parity bit are transmitted to their destination, where they are

applied to the parity checker circuit.

The parity checker circuit checks for possible errors in the transmission.

Since the information was transmitted with odd parity the four bits

received must have an odd number of 1s. An error occurs during the

transmission if the four bits received have an even number of 1s,

indicating that one bit has changed during transmission.

The output of the parity checker is denoted by PEC (parity error check)

and it will be equal to 1 if an error occurs, i.e., if the four bits received has

an even number of 1s.

From the truth table the expression for the output parity bit is,

P( A, B, C) = (0, 3, 5, 6)

Also written as P = ABC + ABC + ABC + ABC = (A B C)

CIRCUIT DIAGRAM:

ODD PARITY CHECKER

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TRUTH TABLE (ODD PARITY CHECKER):

S.N

o

INPUT

( four bit

message

Received )

OUTPUT

(Parity error

check)

A B C P X

1. 0 0 0 0 1

2. 0 0 0 1 0

3. 0 0 1 0 0

4. 0 0 1 1 1

5. 0 1 0 0 0

6. 0 1 0 1 1

7. 0 1 1 0 1

8. 0 1 1 1 0

9. 1 0 0 0 0

10. 1 0 0 1 1

11. 1 0 1 0 1

12. 1 0 1 1 0

13. 1 1 0 0 1

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14. 1 1 0 1 0

15. 1 1 1 0 0

16. 1 1 1 1 1

From the truth table the expression for the output parity checker bit is,

X (A, B, C, P) = (0, 3, 5, 6, 9, 10, 12, 15)

The above expression is reduced as,

This X = (A B C P)

PROCEDURE:

1. Connections are given as per the circuit diagrams.2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for the Parity generator

and checker.

RESULT:

The design of the three bit odd Parity generator and checker circuits was

done and their truth tables were verified.

TRUTH TABLE:

| Binary input | Gray codeoutput |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0

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0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

Ex. No. 4 DESIGN AND IMPLEMENTATION OF CODE CONVERTOR

Date:

AIM:

To design and implement 4-bit

(i) Binary to gray code converter

(ii) Gray to binary code converter

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APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.

1. X-OR GATE IC 7486 1

2. AND GATE IC 7408 1

3. OR GATE IC 7432 1

4. NOT GATE IC 7404 1

5. IC TRAINER KIT - 1

6. PATCH CORDS - 35

THEORY:

The availability of large variety of codes for the same discrete elements of

information results in the use of different codes by different systems. A conversion

circuit must be inserted between the two systems if each uses different codes for

same information. Thus, code converter is a circuit that makes the two systems

compatible even though each uses different binary code.

The bit combination assigned to binary code to gray code. Since each code

uses four bits to represent a decimal digit. There are four inputs and four outputs.

Gray code is a non-weighted code.

The input variable are designated as B3, B2, B1, B0 and the output variables

are designated as C3, C2, C1, Co. from the truth table, combinational circuit is

designed. The Boolean functions are obtained from K-Map for each output variable.

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G3 = B3

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LOGIC DIAGRAM :

A code converter is a circuit that makes the two systems compatible even

though each uses a different binary code. To convert from binary code to Excess-3

code, the input lines must supply the bit combination of elements as specified by

code and the output lines generate the corresponding bit combination of code. Each

one of the four maps represents one of the four outputs of the circuit as a function

of the four input variables.

A two-level logic diagram may be obtained directly from the Boolean

expressions derived by the maps. These are various other possibilities for a logic

diagram that implements this circuit. Now the OR gate whose output is C+D has

been used to implement partially each of three outputs.

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TRUTH TABLE:

| Gray Code | Binary Code

|

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

0

0

0

0

1

1

1

1

1

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

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1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

1

1

1

1

1

1

0

0

0

1

1

1

1

0

1

1

0

0

1

1

1

0

1

0

1

0

1

K-map

B3 = G3

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LOGIC DIAGRAM:

GRAY CODE TO BINARY CONVERTOR

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PROCEDURE:

(i) Connections were given as per circuit diagram.

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(ii) Logical inputs were given as per truth table

(iii) Observe the logical output and verify with the truth tables.

RESULT:

The design of the Binary to Gray code converter & gray to binary code

converter circuit was done and its truth table was verified.

CIRCUIT DIAGRAM:

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TRUTH TABLE:

For a serial data input of 1101,

S.NO CLOCK

PULSE

INPUTS OUTPUTS

D1 D2 D3 D4 Q1 Q2 Q3 Q4

1 1 1 X X X 1 X X X

2 2 1 1 X X 1 1 X X

3 3 0 1 1 X 0 1 1 X

4 4 1 0 1 1 1 0 1 1

5 5 X 1 0 1 X 1 0 1

6 6 X X 1 0 1 X 1 0

7 7 X X X 1 0 X X 1

8 8 X X X X X X X X

Ex. No. 5 IMPLEMENTATION OF SHIFT REGISTERS Date:

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AIM:

To design and implement 4 bit shift registers in SISO, SIPO, PISO,

PIPO modes using suitable ICs.

APPARATUS REQUIRED:



2. D Flip Flop IC 7474 2


required

THEORY:

A register capable of shifting its binary information either to the left

or to the right is called a shift register. The logical configuration of a shift

register consists of a chain of flip flops connected in cascade with the

output of one flip flop connected to the input of the next flip flop. All the

flip flops receive a common clock pulse which causes the shift from one

stage to the next.

The Q output of a D flip flop is connected to the D input of the flip

flop to the left. Each clock pulse shifts the contents of the register one bit

position to the right. The serial input determines, what goes into the right

most flip flop during the shift.

The serial output is taken from the output of the left most flip flop

prior to the application of a pulse. Although this register shifts its

contents to its left, if we turn the page upside down we find that the

register shifts its contents to the right. Thus a unidirectional shift

register can function either as a shift right or a shift left register.

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PIN DIAGRAM OF IC 7474:

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PROCEDURE:

1. Connections are given as per the circuit diagrams.2. Apply the input and verify the truth table of the counter

RESULT:

The truth table of a serial in serial out left shift register was hence

verified.

4 X 1 MULTIPLEXER

LOGIC SYMBOL:49


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TRUTH TABLE (4 X 1 MULTIPLEXER):

S.NoSELECTION INPUT OUTPUT

S1 S2 Y

1. 0 0 I0

2. 0 1 I1

3. 1 0 I2

4. 1 1 I3

PIN DIAGRAM OF IC 7411:

Expt. No. 6 MULTIPLEXER & DEMULTIPLEXER Date:

AIM:

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To design and verify the truth table of a 4X1 Multiplexer & 1X4

Demultiplexer.

APPARATUS REQUIRED:



2. OR gate IC 7432 1


4. AND gate ( three input ) IC 7411 1


required

THEORY:

Multiplexer is a digital switch which allows digital information from

several sources to be routed onto a single output line. The basic

multiplexer has several data input lines and a single output line.

The selection of a particular input line is controlled by a set of

selection lines. Normally, there are 2n input lines and n selector lines

whose bit combinations determine which input is selected. Therefore,

multiplexer is many into one and it provides the digital equivalent of an

analog selector switch.

A Demultiplexer is a circuit that receives information on a single line

and transmits this information on one of 2n possible output lines. The

selection of specific output line is controlled by the values of n selection

lines.

CIRCUIT DIAGRAM:

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1X4 DEMULTIPLEXER

LOGIC SYMBOL:

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TRUTH TABLE (1X4 DEMULTIPLEXER):

S.NoINPUT OUTPUT

S1 S2 Din Y0 Y1 Y2 Y3

1. 0 0 0 0 0 0 0

2. 0 0 1 1 0 0 0

3. 0 1 0 0 0 0 0

4. 0 1 1 0 1 0 0

5. 1 0 0 0 0 0 0

6. 1 0 1 0 0 1 0

7. 1 1 0 0 0 0 0

8. 1 1 1 0 0 0 1

CIRCUIT DIAGRAM:

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PROCEDURE:

1. Connections are given as per the circuit diagrams.

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2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.3. Apply the inputs and verify the truth table for the multiplexer

&Demultiplexer.

RESULT:

The design of the 4x1 Multiplexer and 1x4 Demultiplexer circuits was done

and their truth tables were verified.

PIN DIAGRAM:

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CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR:

Ex. No.7a STUDY OF NE555 TIMER IN ASTABLE MULTIVIBRATOR

Date:

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AIM:

To design an astable multivibrator circuit for the given specifications

using 555 Timer IC.

APPARATUS REQUIRED:

S.

No

Name of the Apparatus Range Quantity

1. Function Generator 3 MHz 1

2. CRO 30 MHz 1

3. Dual RPS 0 30 V 1

4. Timer IC IC 555 1

5. Bread Board 1

6.Resistors As

required

7.Capacitors As

required

8.Connecting wires and

probes

As

required

THEORY:

An astable multivibrator, often called a free-running multivibrator, is arectangular-wave-generating circuit. This circuit does not require an

external trigger to change the state of the output. The time during which

the output is either high or low is determined by two resistors and a

capacitor, which are connected externally to the 555 timer. The time

during which the capacitor charges from 1/3 Vcc to 2/3 Vcc is equal to the

time the output is high and is given by,

tc = 0.69 (R1 + R2) C

Similarly the time during which the capacitor discharges from 2/3 Vcc to 1/3

Vcc is equal to the time the output is low and is given by,

td = 0.69 (R2) C

Thus the total time period of the output waveform is,

T = tc + td = 0.69 (R1 + 2 R2) C

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DESIGN:

Given f= 4 KHz,

Therefore, Total time period, T = 1/f = ____________

We know, duty cycle = tc/ T

Therefore, tc = ------------------------

and td = ____________

We also know for an astable multivibrator

td = 0.69 (R2) C

Therefore, R2 = _____________

tc = 0.69 (R1 + R2) C

Therefore, R1 = _____________

OBSERVATIONS:

S.N

o

Waveforms

Amplitude

( No. of div x

Volts per div )

Time period

( No. of div x

Time per div )

tc td

1. Output Voltage , Vo

2. Capacitor voltage , Vc

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The term duty cycle is often used in conjunction with the astable

multivibrator. The duty cycle is the ratio of the time tc during which the

output is high to the total time period T. It is generally expressed in

percentage. In equation form,

% duty cycle = [(R1 + R2) / (R1 + 2 R2)] x 100

PROCEDURE:

1. Connections are given as per the circuit diagram.2. + 5V supply is given to the + Vcc terminal of the timer IC.3. At pin 3 the output waveform is observed with the help of a CRO4. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and

Vc voltage waveforms are plotted in a graph sheet.

RESULT:

The design of the Astable multivibrator circuit was done and the output

voltage and capacitor voltage waveforms were obtained.

PIN DIAGRAM:

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CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR:

Ex. No.7b STUDY OF NE555 TIMER IN MULTIVIBRATOR MONOSTABLE

OPERATION Date:

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AIM:

Todesign a monostable multivibrator for the given specifications

using 555 timer IC.

APPARATUS REQUIRED:


1. Function Generator 3 MHz, Analog 1

2. CRO 30 MHz 1


4. Timer IC IC 555 1

5. Bread Board 1

6. Resistors Asrequired

7.Capacitors As

required


probes

As

required

THEORY:

A monostable multivibrator often called a one-shot multivibrator is a pulse

generating circuit in which the duration of the pulse is determined by the

RC network connected externally to the 555 timer. In a stable or stand-by

state the output of the circuit is approximately zero or at logic low level.

When an external trigger pulse is applied, the output is forced to go high

(approx. Vcc). The time during which the output remains high is given by,

tp = 1.1 R1 C

At the end of the timing interval, the output automatically reverts back to

its logic low state. The output stays low until a trigger pulse is appliedagain. Then the cycle repeats.

Thus the monostable state has only one stable state hence the name

monostable.

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DESIGN:

[ To design a monostable multivibrator with tp = 0.616 ms , assume C = 0.01 F ]

Given tp = 0.616 ms = 1.1 R1 C

Therefore, R1 = _____________

OBSERVATIONS:

S.N

o Observation

Amplitude

( No. of div x

Volts per div )

Time period

( No. of div x

Time per div )

ton toff

1. Trigger input

2. Output Voltage , Vo

3. Capacitor voltage , Vc

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PROCEDURE:

1. Connections are given as per the circuit diagram.2. + 5V supply is given to the + Vcc terminal of the timer IC.

3. A negative trigger pulse of 5V, 2 KHz is applied to pin 2 of the 555 IC4. At pin 3 the output waveform is observed with the help of a CRO5. At pin 6 the capacitor voltage is obtained in the CRO and the V0 and

Vc voltage waveforms are plotted in a graph sheet.

RESULT:

The design of the Monostable multivibrator circuit was done and the input

and output waveforms were obtained.

PIN DIAGRAM:

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CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:

DESIGN:

We know for an inverting Amplifier ACL = RF / R1

Assume R1 (approx. 10 K) and find Rf

Hence Vo(theoretical) = - ACL Vi

Ex. No.8a INVERTING AMPLIFIER Date:

AIM64


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To design an Inverting Amplifier for the given specifications using Op-Amp

IC 741.

APPARATUS REQUIRED:



2. CRO 30 MHz 1


4. Op-Amp IC 741 1

5. Bread Board 1

6.Resistors As

required


probes

As

required

THEORY:

The input signal Vi is applied to the inverting input terminal through R1and the non-inverting input terminal of the op-amp is grounded. The

output voltage Vo is fed back to the inverting input terminal through the Rf

- R1 network, where Rf is the feedback resistor. The output voltage isgiven as,

Vo = - ACL Vi

Here the negative sign indicates that the output voltage is 1800 out of

phase with the input signal.

PRECAUTIONS:

Output voltage will be saturated if it exceeds 15V.

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PROCEDURE:

1. Connections are given as per the circuit diagram.2. + Vcc and - Vcc supply is given to the power supply terminal of the Op-

Amp IC.3. By adjusting the amplitude and frequency knobs of the function

generator, appropriate input voltage is applied to the inverting inputterminal of the Op-Amp.

4. The output voltage is obtained in the CRO and the input and outputvoltage waveforms are plotted in a graph sheet.

OBSERVATIONS:

S.No. Amplitude

( No. of div x Volts per

div )

Time period

( No. of div x Time per div )

Input

Output Theoretical -

Practical -

RESULT:

The design and testing of the inverting amplifier is done and the input and

output waveforms were drawn

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PIN DIAGRAM:

CIRCUIT DIAGRAM OF NON INVERITNG AMPLIFIER:

DESIGN:

We know for a Non-inverting Amplifier ACL = 1 + (RF / R1)

Assume R1 ( approx. 10 K ) and find Rf

Hence Vo = ACL Vi

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Ex. No.8b NON - INVERTING AMPLIFIER Date:

AIM:

To design a Non-Inverting Amplifier for the given specifications using Op-Amp IC 741.

APPARATUS REQUIRED:



2. CRO 30 MHz 1

3. Dual RPS (0 30) V 1

4. Op-Amp IC 741 1

5. Bread Board 1

6.Resistors As

required


probes

As

required

THEORY:

The input signal Vi is applied to the non - inverting input terminal of the

op-amp. This circuit amplifies the signal without inverting the input

signal. It is also called negative feedback system since the output is

feedback to the inverting input terminals. The differential voltage Vd at

the inverting input terminal of the op-amp is zero ideally and the output

voltage is given as,Vo = ACL Vi . Here the output voltage is in phase with

the input signal.

PRECAUTIONS:

Output voltage will be saturated if it exceeds 15V.

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PROCEDURE:



generator, appropriate input voltage is applied to the non - invertinginput terminal of the Op-Amp.


OBSERVATIONS:

S.No. Amplitude


div )

Time period


Input

Output Theoretical -

Practical -

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RESULT:

The design and testing of the Non-inverting amplifier is done and

the input and output waveforms were drawn.

PIN DIAGRAM:

CIRCUIT DIAGRAM OF INTEGRATOR:

DESIGN:

We know the frequency at which the gain is 0 dB, fb = 1 / (2 R1 Cf)

Therefore fb = _____

Since fb = 10 fa, and also the gain limiting frequency fa = 1 / (2 RfCf)

We get, Rf= _______ and hence R1 = __________

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Expt. No.8a INTEGRATOR Date:

AIM:

To design an Integrator circuit for the given specifications using Op-Amp

IC 741.

APPARATUS REQUIRED:



2. CRO 30 MHz 1


4. Op-Amp IC 741 1

5. Bread Board 1

6.Resistors As

required

7.Capacitors As

required


probes

As

required

THEORY:

A circuit in which the output voltage waveform is the integral of the input

voltage waveform is the integrator. Such a circuit is obtained by using a

basic inverting amplifier configuration if the feedback resistor Rf is

replaced by a capacitor Cf . The expression for the output voltage is givenas,

Vo = - (1/RfC1) Vi dt

Here the negative sign indicates that the output voltage is 180 0 out of

phase with the input signal. Normally between fa and fb the circuit acts as

an integrator. Generally, the value of fa < fb . The input signal will be

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integrated properly if the Time period T of the signal is larger than or

equal to Rf Cf. That is,

T Rf Cf

The integrator is most commonly used in analog computers and ADC and

signal-wave shaping circuits.

OBSERVATIONS:

S.No. Amplitude

( No. of div x Volts perdiv )

Time period


Input

Output

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PROCEDURE:





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RESULT:The design of the Integrator circuit was done and the input and output

waveforms were obtained.

PIN DIAGRAM:

CIRCUIT DIAGRAM OF DIFFERENTIATOR:

DESIGN:

Given fa = ---------------

We know the frequency at which the gain is 0 dB, fa = 1 / (2 Rf C1)

Let us assume C1 = 0.1 F; then

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Rf = _________

Since fb = 20 fa, fb = ---------------

We know that the gain limiting frequency fb = 1 / (2 R1 C1)

Hence R1 = _________

Also since R1C1 = RfCf ; Cf= _________

Expt. No.8b DIFFERENTIATOR Date:

AIM:

To design a Differentiator circuit for the given specifications using Op-

Amp IC 741.

APPARATUS REQUIRED:



2. CRO 30 MHz 1


4. Op-Amp IC 741 1

5. Bread Board 1

6. Resistors Asrequired

7.Capacitors As

required


probes

As

required

THEORY:

The differentiator circuit performs the mathematical operation of

differentiation; that is, the output waveform is the derivative of the inputwaveform. The differentiator may be constructed from a basic inverting

amplifier if an input resistor R1 is replaced by a capacitor C1. The

expression for the output voltage is given as,

Vo = - RfC1 (dVi /dt)

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Here the negative sign indicates that the output voltage is 180 0 out of

phase with the input signal. A resistor Rcomp = Rf is normally connected to

the non-inverting input terminal of the op-amp to compensate for the

input bias current. A workable differentiator can be designed by

implementing the following steps:

1. Select fa equal to the highest frequency of the input signal to bedifferentiated. Then, assuming a value of C1 < 1 F, calculate thevalue of Rf.

2. Choose fb = 20 fa and calculate the values of R1 and Cf so that R1C1 =RfCf.

The differentiator is most commonly used in waveshaping circuits to

detect high frequency components in an input signal and also as a rateof

change detector in FM modulators.

OBSERVATIONS:

Input - Sine wave

S.No. Amplitude


div )

Time period


Input

Output

Input Square wave

S.No. Amplitude


div )

Time period


Input

Output

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PROCEDURE:





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RESULT:

The design of the Differentiator circuit was done and the input and output

waveforms were obtained.

lic lab manual ariv complete

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