linear integrated circuits lab manual

Linear and digital integrated circuits Lab

EC1262 – LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY

1. Study of Basic Digital IC’s. (Verification of truth table for AND, OR, EXOR, NOT, NOR,

NAND, JK FF, RS FF, D FF)

2. Implementation of Boolean Functions, Adder/ Subtractor circuits.

a) Code converters, Parity generator and parity checking, Excess – 3, 2’sComplement,

Binary to Gray code using suitable IC’s.

b) Encoders and Decoders.

3. Counters: Design and implementation of 4 – bit modulo counters as synchronous and

4. Asynchronous types using FF IC’s and specific counter IC.

5. Shift Registers:

6. Design and implementation of 4 – bit shift registers in SISO, SIPO, PISO, PIPO

modes using suitable IC’s.

7. Multiplex/ De – multiplex:

8. Study of 4:1; 8:1 multiplexer and Study of 1:4; 1:8 demultiplexer.

9. Timer IC application:

10. Study of NE/SE 555 timer in Astable, Monostable operation.

11. Application of Op – Amp:

12. Slew rate verifications, inverting and non – inverting amplifier,

13. Adder, comparator, Integrater and Differentiator.

14. Study of Analog to Digital Converter and Digital to Analog Converter: Verification of A/D

conversion using dedicated IC’s.

15. Study of VCO and PLL ICs:

i. Voltage to frequency characteristics of NE/ SE 566 IC.

ii. Frequency multiplication using NE/SE 565 PLL IC.


LINEAR AND DIGITAL INTEGRATED CIRCUITS

LAB MANUAL

www.arivurp.tk


CONTENTS

SI.NO LIST OF EXPERIMENTS PAGE NO

1 Verification of Logic gates

2 Realization of Adder and Subtractor

a)Half/Full Adder

b)Half/Full Subtractor

3 Code converters

a)BCD to Excess-3

b)Excess-3 to BCD

c)Binary to gray

d)Gray to Binary

4 Parity generators and Parity checkers

5 Multiplexer and De multiplexer

6 Encoders and decoders

7 Design and Implementation of

4 bit Asynchronous counter

8 Design and Implementation of

4 bit synchronous counter

9 Design and implementation of 4-bit shift

register

10 Design and testing of Monostable and Astable

multivibrator using 555 timer IC.

11 Design of Integrator and Differentiator circuit

using Op-Amps IC 741

12 Study of VCO and PLL IC’s


Expt.No:1

AIM:

To study and verify the truth table of Logic gates

APPARATUS REQUIRED:

THEORY:

Circuit that takes the logical decision and the process are called logic gates. Each gate has

one or more input and only one output.

OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal

gates. Basic gates form these gates.

AND GATE:

The AND gate performs a logical multiplication commonly known as AND function. The

output is high when both the inputs are high. The output is low level when any one of the inputs

is low.

OR GATE:

SL No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1

2. OR GATE IC 7432 1

3. NOT GATE IC 7404 1

4. NAND GATE 2 I/P IC 7400 1

5. NOR GATE IC 7402 1

6. X-OR GATE IC 7486 1

7. NAND GATE 3 I/P IC 7410 1

8. IC TRAINER KIT - 1

9. PATCH CORD - 14


The OR gate performs a logical addition commonly known as OR function. The

output is high when any one of the inputs is high. The output is low level when both the inputs

are low.

NOT GATE:

The NOT gate is called an inverter. The output is high when the input is low. The

output is low when the input is high.

NAND GATE:

The NAND gate is a contraction of AND-NOT. The output is high when both inputs are

low and any one of the input is low .The output is low level when both inputs are high.

NOR GATE:

The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low.

The output is low when one or both inputs are high.

X-OR GATE:

The output is high when any one of the inputs is high. The output is low when both the

inputs are low and both the inputs are high.

PROCEDURE:

Verify the gates

Connections were given as per circuit diagram.

Logical inputs were given as per truth table

Observe the logical output and verify with the truth tables

AND GATE:


SYMBOL: PIN DIAGRAM:

OR GATE:

NOT GATE:



X-OR GATE :

SYMBOL : PIN DIAGRAM :

2-INPUT NAND GATE:



3-INPUT NAND GATE :

NOR GATE:


Result:

The different logic gates were studied and their truth table was verified using 74XX IC’s.


Expt.No:2

AIM:

To design and construct half adder, full adder, half subtractor and full subtractor

circuits and verify the truth table using XOR and basic logic gates.

APPARATUS REQUIRED:

Sl.No. COMPONENT SPECIFICATION QTY.






4. PATCH CORDS - 23

THEORY:

HALF ADDER:

A half adder has two inputs for the two bits to be added and two outputs one from the

sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above circuit is called as a

carry signal from the addition of the less significant bits sum from the X-OR Gate the carry out

from the AND gate.

FULL ADDER:

A full adder is a combinational circuit that forms the arithmetic sum of input; it consists

of three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder

cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken

from OR Gate.

HALF SUBTRACTOR:

The half subtractor is constructed using X-OR and AND Gate. The half subtractor has

two input and two outputs. The outputs are difference and borrow. The difference can be applied

using X-OR Gate, borrow output can be implemented using an AND Gate and an inverter.


FULL SUBTRACTOR:

The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor

the logic circuit should have three inputs and two outputs. The two half subtractor put together

gives a full subtractor .The first half subtractor will be C and A B. The output will be difference

output of full subtractor. The expression AB assembles the borrow output of the half subtractor

and the second term is the inverted difference output of first X-OR.

LOGIC DIAGRAM:

HALF ADDER

TRUTH TABLE:

A B CARRY SUM

0

0

1

1

0

1

0

1

0

0

0

1

0

1

1

0

K-Map for SUM: K-Map for CARRY:

SUM = A’B + AB’ CARRY = AB


LOGIC DIAGRAM:

FULL ADDER

FULL ADDER USING TWO HALF ADDER

TRUTH TABLE:

A B C CARRY SUM

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

0

0

1

0

1

1

1

0

1

1

0

1

0

0

1

K-Map for SUM:

SUM = A’B’C + A’BC’ + ABC’ + ABC


K-Map for CARRY:

CARRY = AB + BC + AC

LOGIC DIAGRAM:

HALF SUBTRACTOR

TRUTH TABLE:

A B BORROW DIFFERENCE

0

0

1

1

0

1

0

1

0

1

0

0

0

1

1

0

K-Map for DIFFERENCE:

DIFFERENCE = A’B + AB’

K-Map for BORROW:


BORROW = A’B

LOGIC DIAGRAM:

FULL SUBTRACTOR

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

TRUTH TABLE:

A B C BORROW DIFFERENCE

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

1

1

0

0

0

1

0

1

1

0

1

0

0

1

K-Map for Difference:


Difference = A’B’C + A’BC’ + AB’C’ + ABC

K-Map for Borrow:

Borrow = A’B + BC + A’C

PROCEDURE:

Verify the gates



Observe the logical output and verify with the truth tables

RESULT:

The Adder and subtractor circuits were constructed and their truth table was verified.


Expt.No:3

AIM:

To design and implement 4-bit

(i) Binary to gray code converter

(ii) Gray to binary code converter

(iii) BCD to excess-3 code converter

(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:







6. PATCH CORDS - 35

THEORY:

The availability of large variety of codes for the same discrete elements of information

results in the use of different codes by different systems. A conversion circuit must be inserted

between the two systems if each uses different codes for same information. Thus, code converter

is a circuit that makes the two systems compatible even though each uses different binary code.

The bit combination assigned to binary code to gray code. Since each code uses four bits

to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-weighted

code.

The input variable are designated as B3, B2, B1, B0 and the output variables are

designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The

Boolean functions are obtained from K-Map for each output variable.

A code converter is a circuit that makes the two systems compatible even though each

uses a different binary code. To convert from binary code to Excess-3 code, the input lines must

supply the bit combination of elements as specified by code and the output lines generate the


corresponding bit combination of code. Each one of the four maps represents one of the four

outputs of the circuit as a function of the four input variables.

A two-level logic diagram may be obtained directly from the Boolean expressions

derived by the maps. These are various other possibilities for a logic diagram that implements

this circuit. Now the OR gate whose output is C+D has been used to implement partially each of

three outputs.

LOGIC DIAGRAM:

BINARY TO GRAY CODE CONVERTOR

K-Map for G3:

G3 = B3

K-Map for G2:


K-Map for G1:

K-Map for G0:


TRUTH TABLE:

| Binary input | Gray code output |

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

LOGIC DIAGRAM:

GRAY CODE TO BINARY CONVERTOR


K-Map for B3:

B3 = G3

K-Map for B2:

K-Map for B1:


K-Map for B0:

TRUTH TABLE:

| Gray Code | Binary Code |

G3 G2 G1 G0 B3 B2 B1 B0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

1

1

0

0

1

1

1

1

0

0

0

0

0

1

1

0

0

1

1

0

0

1

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1


1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

0

0

1

1

0

1

1

1

1

1

1

0

0

1

1

1

1

1

1

0

0

1

1

0

1

0

1

0

1

LOGIC DIAGRAM:

BCD TO EXCESS-3 CONVERTOR

K-Map for E3:

E3 = B3 + B2 (B0 + B1)


K-Map for E2:

K-Map for E1:


K-Map for E0:

TRUTH TABLE:

| BCD input | Excess – 3 output |

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

1

1

1

1

1

x

x

x

x

x

x

0

1

1

1

1

0

0

0

0

1

x

x

x

x

x

x

1

0

0

1

1

0

0

1

1

0

x

x

x

x

x

x

1

0

1

0

1

0

1

0

1

0

x

x

x

x

x

x


LOGIC DIAGRAM:

EXCESS-3 TO BCD CONVERTER

K-Map for A:

A = X1 X2 + X3 X4 X1


K-Map for B:

K-Map for C:


K-Map for D:

TRUTH TABLE:

| Excess – 3 Input | BCD Output |

B3 B2 B1 B0 G3 G2 G1 G0

0

0

0

0

0

1

1

1

1

1

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

0

0

0

0

0

0

0

0

1

1

0

0

0

0

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

0

1


PROCEDURE:

Verify the gates



Observe the logical output and verify with the truth tables.

RESULT:

The 4 bit code converters were designed and their truth table was verified.


Expt.No:4

AIM:

To implement the odd and even parity checkers using the logic gates and also to generate

the odd parity and even parity numbers using the generators.

APPARATUS REQUIRED:

Theory:

Parity checking is used for error detection in data transmission.

Odd parity checkers:

It counts the number of 1’s in the given input and produces a 1 in the output when the

number of 1’s is odd.

Even parity checker:

It counts the number of 1’s in the given input and produces a 1 in the output when the

number of 1’s is even.

Odd parity generators:

It generates an odd parity number. The odd parity checker circuit is used with the

inverted output and also the input bits. So when the input is a 4-bit number then the output of the

generator circuit will have 5 bits which is an odd parity number.

Even parity generator: It generates an even parity number. The even parity checker circuit is used with the

inverted output and also the input bits. So when the input is a 4-bit number then the output of the

generator circuit will have 5 bits which is an even parity number.

Logic diagrams:

Odd parity checker:

A

B

C

DODD PARITY

74LS86A

10

98

74LS86A

4

5674LS86A

1

23

Sl.No Component Type Quantity

1 Trainer Kit - 1

5 EX-OR IC7486 1

5 NOT gate IC 7404 1

6 Connecting wires - Required


Even parity checker:

A

B

C

DODD PARITY EVEN PARITY

74LS86A

10

98

74LS86A

4

5674LS86A

1

23

74LS04

1 2

Odd parity generator:

A

AB

B

C

C

D

D

PARITY BIT

74LS86A

10

98

74LS86A

4

56

74LS86A

1

23

74LS04

1 2

Even parity generator

AB

BA

C

C

D

D

PARITY BIT74LS86A

1

23

74LS86A

4

56

74LS86A

10

98

Procedure:

1. The circuit is implemented using logic gates.

2. The inputs are given as per the truth table.

3. The corresponding outputs are noted.

4. The theoretical and practical values were verified.


TRUTH TABLE:

Input Checker output Generator output

A B C D odd even odd even

0 0 0 0 0 1 00001 00000

0 0 1 1 0 00010 00011

0 0 1 0 1 0 00100 00101

0 0 1 1 0 1 00111 00110

0 1 0 0 1 0 01000 01001

0 1 0 1 0 1 01011 01010

0 1 1 0 0 1 01101 01100

0 1 1 1 1 0 01110 01111

1 0 0 0 1 0 10000 10001

1 0 0 1 0 1 10011 10010

1 0 1 0 0 1 10101 10100

1 0 1 1 1 0 10110 10111

1 1 0 0 0 1 11001 11000

1 1 0 1 1 0 11010 11011

1 1 1 0 1 0 11100 11101

1 1 1 1 0 1 11111 11110

RESULT:

The odd and even parity checkers are implemented using the logic gates and the odd

parity and even parity numbers are generated using the corresponding generators.


Expt.No:5

AIM:

To design and realize a 4-bit synschronous counter

APPARATUS REQUIRED:

IC 7408, IC 7476, IC 7400, IC 7432 etc.

Procedure: -

1. Connections are made as per circuit diagram.

2. Clock pulses are applied one by one at the clock I/P and the O/P is

observed at QA, QB & QC for IC 7476.

3. Verify the Truth table .


Binary 4-bit Synchronous Counter

Truth Table for JK flip-flop:

J K Qn+1

0

0

1

1

0

1

0

1

Qn

0

1

Qn


Pin diagram:

4-bit Synchronous Counter Waveform Timing Diagram.

THEORY:

It can be seen that the external clock pulses (pulses to be counted) are fed directly to each J-K

flip-flop in the counter chain and that both the J and K inputs are all tied together in toggle mode,

but only in the first flip-flop, flip-flop A (LSB) are they connected HIGH, logic "1" allowing the

flip-flop to toggle on every clock pulse. Then the synchronous counter follows a predetermined

sequence of states in response to the common clock signal, advancing one state for each pulse.

http://www.electronics-tutorials.ws/sequential/seq_2.html

http://www.electronics-tutorials.ws/sequential/seq_2.html


The J and K inputs of flip-flop B are connected to the output "Q" of flip-flop A, but the J and K

inputs of flip-flops C and D are driven from AND gates which are also supplied with signals

from the input and output of the previous stage. If we enable each J-K flip-flop to toggle based

on whether or not all preceding flip-flop outputs (Q) are "HIGH" we can obtain the same

counting sequence as with the asynchronous circuit but without the ripple effect, since each flip-

flop in this circuit will be clocked at exactly the same time. As there is no propagation delay in

synchronous counters because all the counter stages are triggered in parallel the maximum

operating frequency of this type of counter is much higher than that of a similar asynchronous

counter. Because this 4-bit synchronous counter counts sequentially on every clock pulse the

resulting outputs count upwards from 0 ( "0000" ) to 15 ( "1111" ). Therefore, this type of

counter is also known as a 4-bit Synchronous Up Counter.

TRUTH TABLE

COUNT OUTPUTS

QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

RESULT:

The 4-bit synchronous counter was designed and its truth table was verified.


Expt.No:6

AIM:

To design and realize a 4-bit Asynschronous counter

APPARATUS REQUIRED:


1. JK FLIP FLOP IC 7476 2

2. NAND GATE IC 7400 1


4. PATCH CORDS - 30

THEORY:

A counter is a register capable of counting number of clock pulse arriving at its clock input.

Counter represents the number of clock pulses arrived. A specified sequence of states appears as counter output. This is the main difference between a register and a counter. There are two types of counter,

synchronous and asynchronous. In synchronous common clock is given to all flip flop and in

asynchronous first flip flop is clocked by external pulse and then each successive flip flop is clocked by Q or Q output of previous stage. A soon the clock of second stage is triggered by output of first stage.

Because of inherent propagation delay time all flip flops are not activated at same time which results in

asynchronous operation. A simple implementation of a 4-bit counter is shown in Figure 1, which consists

of 4 stages of cascaded J-K flip-flops. This is a binary counter, since the output is in binary system format, i.e., only two digits are used to represent the count, i.e., '1' and '0'. With only 4 bits, it can only

count up to '1111', or decimal number 15. The J and K inputs of all the flip-flops are tied to '1', so that

they will toggle between states every time they are clocked. Also, the output of each flip-flop in the counter is used to clock the next flip-flop. As a result, the succeeding flip-flop toggles between '1' and '0'

at only half the frequency as the flip-flop before it.

The last flip-flop will only toggle after the first flip-flop has already toggled 8 times. This type of binary counter is known as a 'serial', 'ripple', or 'asynchronous' counter. The name 'asynchronous' comes from

the fact that this counter's flip-flops are not being clocked at the same time.

A 4-bit counter, which has 16 unique states that it can count through, is also called a modulo-16 counter,

or mod-16 counter. By definition, a modulo-k or base-k counter is one that returns to its initial state after k cycles of the input waveform. A counter that has N flip-flops is a modulo 2

N counter.


An asynchronous counter has a serious drawback - its speed is limited by the cumulative propagation

times of the cascaded flip-flops. A counter that has N flip-flops, each of which has a propagation time t,

must therefore wait for a duration equal to N x t before it can undergo another transition clocking

PIN DIAGRAM FOR IC 7476:

LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:


TRUTH TABLE:

CLK QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0

3 1 1 0 0

4 0 0 1 0

5 1 0 1 0

6 0 1 1 0

7 1 1 1 0

8 0 0 0 1

9 1 0 0 1

10 0 1 0 1

11 1 1 0 1

12 0 0 1 1

13 1 0 1 1

14 0 1 1 1

15 1 1 1 1

RESULT:

The 4-bit Asynchronous counter was designed and its truth table was verifie


Expt.No:7

AIM:

Aim:

To realize the Encoder and Decoder circuit using logic gates and to verify the truth table.

Apparatus Required:

ENCODER:(8:3)

Theory:

An encoder has 2n (or fewer) input lines and ‘n’ output lines. The output lines generate

the binary code corresponding to the input value. In encoders, it is assumed that only one input

has a value of 1 at any given time. The encoders are specified as m-to-n encoders where m ≤ 2n.

Truth Table:

D0 D1 D2 D3 D4 D5 D6 D7 A B C

1 0 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0 1

0 0 1 0 0 0 0 0 0 1 0

0 0 0 1 0 0 0 0 0 1 1

0 0 0 0 1 0 0 0 1 0 0

0 0 0 0 0 1 0 0 1 0 1

0 0 0 0 0 0 1 0 1 1 0

0 0 0 0 0 0 0 1 1 1 1

Sl.No Component Type Quantity

1 Trainer Kit - 1

2 OR Gate IC 7432 3

3 AND gate(3 input) IC7411 2

4 NOT gate IC 7404 1

5 Connecting wires - Required


Logic Diagram:

B

A

C

D0D1D2D3D4D5D6D7

74LS32

13

1211

74LS32

10

98

74LS32

13

1211

74LS32

4

56

74LS32

1

23

74LS32

1

23

74LS32

4

56

74LS32

10

98

74LS32

1

23

DECODER :( 2:4)

Theory:

A decoder is a combinational circuit that converts binary information from ‘n’ input lines

to a maximum of 2n unique output lines. It performs the reverse operation of the encoder. If the

n-bit decoded information has unused or don’t-care combinations, the decoder output will have

fewer than 2n outputs. The decoders are represented as n-to-m line decoders, where m ≤ 2

n. Their

purpose is to generate the 2n (or fewer) minterms of n input variables. The name decoder is also

used in conjunction with some code converters such as BCD-to-seven-segment decoders. Most,

if not all, IC decoders include one or more enable inputs to control the circuit operation. A

decoder with an enable input can function as a de-multiplexer.

Truth Table:

INPUTS OUTPUTS

DIN X Y D0 D1 D2 D3

1

1

1

1

0

0

1

1

0

1

0

1

1

0

0

0

0

1

0

0

0

0

1

0

0

0

0

1


Logic diagram:

X YDIN

D0

D1

D2

D3

74LS11

1089

11

74LS11

364

5

74LS04

12

74LS11

1122

13

74LS11

1122

13

74LS04

12

Procedure:

1. The Encoder and Decoder circuit is designed and the Boolean function is found out.

2. The Low level input is Grounded and the HIGH level input is connected to the +5V

supply.

3. Connections are made as per the circuit given.

4. Observe the output for various combinations of inputs.

5. Thus the truth table is verified.

Result:

Thus the Encoder and Decoder circuit was designed using 74XX IC’s and the output was

verified.


Expt.No:8

DESIGN AND IMPLEMENTATION OF SHIFT REGISTER

AIM:

To design and implement

(i) Serial in serial out

(ii) Serial in parallel out

(iii) Parallel in serial out

(iv) Parallel in parallel out

APPARATUS REQUIRED:


1. D FLIP FLOP IC 7474 2



4. PATCH CORDS - 35

THEORY:

A register is capable of shifting its binary information in one or both directions is known

as shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with

output of one flip flop connected to input of next flip flop. All flip flops receive common clock

pulses which causes the shift in the output of the flip flop.The simplest possible shift register is

one that uses only flip flop. The output of a given flip flop is connected to the input of next flip

flop of the register. Each clock pulse shifts the content of register one bit position to right.

Shift registers are a type of sequential logic circuit, mainly for storage of digital data.

They are a group of flip-flops connected in a chain so that the output from one flip-flop becomes

the input of the next flip-flop. Most of the registers possess no characteristic internal sequence

of states. All the flip-flops are driven by a common clock, and all are set or reset simultaneously.

In this chapter, the basic types of shift registers are studied, such as Serial In - Serial Out,

Serial In - Parallel Out, Parallel In - Serial Out, Parallel In - Parallel Out, and bidirectional shift

registers. A special form of counter - the shift register counter, is also introduced.

Serial In - Serial Out Shift Registers:


A basic four-bit shift register can be constructed using four D flip-flops, as shown below.

The operation of the circuit is as follows. The register is first cleared, forcing all four outputs to

zero. The input data is then applied sequentially to the D input of the first flip-flop on the left

(FF0). During each clock pulse, one bit is transmitted from left to right. Assume a data word to

be 1001. The least significant bit of the data has to be shifted through the register from FF0 to

FF3.

Serial In - Parallel Out Shift Registers:

For this kind of register, data bits are entered serially in the same manner as discussed in

the last section. The difference is the way in which the data bits are taken out of the register.

Once the data are stored, each bit appears on its respective output line, and all bits are available

simultaneously.

Parallel In - Serial Out Shift Registers:

A four-bit parallel in - serial out shift register is shown below. The circuit uses D flip-

flops and NAND gates for entering data (ie writing) to the register D0, D1, D2 and D3 are the

parallel inputs, where D0 is the most significant bit and D3 is the least significant bit. To write

data in, the mode control line is taken to LOW and the data is clocked in. The data can be

shifted when the mode control line is HIGH as SHIFT is active high. The register performs right

shift operation on the application of a clock pulse, as shown in below.

Parallel In - Parallel Out Shift Registers:

For parallel in - parallel out shift registers, all data bits appear on the parallel outputs

immediately following the simultaneous entry of the data bits. The following circuit is a four-bit

parallel in - parallel out shift register constructed by D flip-flops.

The D's are the parallel inputs and the Q's are the parallel outputs. Once the register is

clocked, all the data at the D inputs appear at the corresponding Q outputs simultaneously

PIN DIAGRAM:


LOGIC DIAGRAM:

SERIAL IN SERIAL OUT:

TRUTH TABLE:

CLK

Serial in Serial out

1 1 0

2 0 0

3 0 0

4 1 1

5 X 0

6 X 0

7 X 1

LOGIC DIAGRAM:

SERIAL IN PARALLEL OUT:


TRUTH TABLE:

CLK

DATA

OUTPUT

QA QB QC QD

1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 1

4 1 1 0 0 1

LOGIC DIAGRAM:

PARALLEL IN SERIAL OUT:


TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1

LOGIC DIAGRAM:

PARALLEL IN PARALLEL OUT:

TRUTH TABLE:

CLK

DATA INPUT OUTPUT

DA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0

PROCEDURE:

(i) Verify the gates.


(ii) Connections are given as per circuit diagram.

(iii) Logical inputs are given as per circuit diagram.

(iv) Observe the output and verify the truth table.

RESULT:

The Shift Registers were designed using 74XX IC’s and their output was verified.


Expt.No:9

MULTIPLEXER AND DEMULTIPLEXER

AIM: To construct and verify the truth table of multiplexer and

demultiplexer circuits

APPARATUS REQUIRED:

S.NO Particular Name SPECIFICATION QUANTITY

1

2

3

Digital IC trainer kit

IC7404, IC7432 IC7411

Connecting Wires

----

----

1

1 each

2

MULTIPLEXER (4:1)

CIRCUIT DIAGRAM :


TRUTH TABLE:

Inputs Control input Outputs (D0,D1,D2,D3)

D0 D1 D2 D3 X Y Z

1 0 0 0 0 0 D0

0 1 0 0 0 1 D1

0 0 1 0 1 0 D2

0 0 0 1 1 1 D3

DEMULTIPLEXER (1:4)


TRUTH TABLE:

INPUTS CONTROL INPUTS

OUTPUTS

D X Y D0 D1 D2 D3

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1

0 X X 0 0 0 0

THEORY:

MULTIPLEXER:

Multiplexer means transmitting a large number of information units over a smaller

number of channels or lines. A digital multiplexer is a combinational circuit that selects binary

information from one of many input lines and directs it to a single output line. The selection of a

particular input line is controlled by a set of selection lines. Normally there are 2n input line and

n selection lines whose bit combination determine which input is selected.

DEMULTIPLEXER:

The function of Demultiplexer is in contrast to multiplexer function. It takes information

from one line and distributes it to a given number of output lines. For this reason, the

demultiplexer is also known as a data distributor. Decoder can also be used as demultiplexer.

In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data

select lines enable only one gate at a time and the data on the data input line will pass through the

selected gate to the associated data output line.

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:


FUNCTION TABLE:

S1 S0 INPUTS Y

0 0 D0 → D0 S1’ S0’

0 1 D1 → D1 S1’ S0

1 0 D2 → D2 S1 S0’

1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0

BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:


FUNCTION TABLE:

S1 S0 INPUT

0 0 X → D0 = X S1’ S0’

0 1 X → D1 = X S1’ S0

1 0 X → D2 = X S1 S0’

1 1 X → D3 = X S1 S0

Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1 S0

PROCEDURE:

1. Give connections as per the circuit diagram

2. Inputs are given to the circuit making high ‘1’, i.e. +5 V or

+ Vcc supply to the 16th

pin and for low ‘0’ i.e. GND to the 8th

pin of the gate IC

3. Verify the truth table for the multiplexer as given

4. Repeat the procedure steps for demulitplexer and verify its truth table

RESULT:

The multiplexer and demultiplexer circuits are constructed and their truth table was

verified


Expt No:10

Design and testing of Monostable and Astable multivibrator using

555 timer IC.

Aim:

To design and test monostable and astable multivibrator using 555

timer IC.

Apparatus required: 1.CRO (cathode ray oscilloscope)

2.power supply (+5V to +18V)

3.555 timer

4.Resistors

5.Capacitors

6.connecting wires

7.connecting leads of CRO

Theory:

Astable multivibrator: An astable multivibrator is a wave-generating circuit in which neither of the output levels is

stable. The output keeps on switching between the two unstable states and is a periodic,

rectangular waveform. The circuit is therefore known as an ‘astable multivibrator’. Also, no

external trigger is required to change the state of the output, hence it is also called ‘free-running

multivibrator’. The time for which the output remains in one particular state is determined by the

two resistors and a capacitor externally connected to the 555 timer.

Monostable Multivibrator: A monostable multivibrator is a pulse-generating circuit having one stable and one quasi-stable

state. Since there is only one stable state, the circuit is known as ‘monostable multivibrator’. The

duration of the output pulse is determined by the RC network connected externally to the 555

timer. The stable state output is approximately zero or at logic-low level. An external trigger

pulse forces the output to become high or approximately. After a predetermined length of time,

the output automatically switches back to the stable state and remains low until a trigger pulse is

again applied. The cycle then repeats. That is, each time a trigger pulse is applied, the circuit

produces a single pulse. Hence, it is also called ‘one-shot multivibrator’.


555 timer IC pin diagram:

Pin 1. − Ground, The ground pin connects the 555 timer to the negative (0v) supply rail.

• Pin 2. − Trigger, The negative input to comparator No 1. A negative pulse on this pin "sets"

the internal Flip-flop when the voltage drops below 1/3Vcc causing the output to switch from a

"LOW" to a "HIGH" state.

• Pin 3. − Output, The output pin can drive any TTL circuit and is capable of sourcing or

sinking up to 200mA of current at an output voltage equal to approximately Vcc - 1.5V so small

speakers, LEDs or motors can be connected directly to the output.

• Pin 4. − Reset, This pin is used to "reset" the internal Flip-flop controlling the state of the

output, pin 3. This is an active-low input and is generally connected to a logic "1" level when not

used to prevent any unwanted resetting of the output.

• Pin 5. − Control Voltage, This pin controls the timing of the by overriding the 2/3Vcc level

of the voltage divider network. By applying a voltage to this pin the width of the output signal

can be varied independently of the RC timing network. When not used it is connected to ground

via a 10nF capacitor to eliminate any noise.

• Pin 6. − Threshold, The negative input to comparator No 2. This pin is used to reset the Flip-

flop when the voltage applied to it exceeds 2/3Vcc causing the output to switch from "HIGH" to

"LOW" state. This pin connects directly to the RC timing circuit.

• Pin 7. − Discharge, The discharge pin is connected directly to the Collector of an internal

NPN transistor which is used to "discharge" the timing capacitor to ground when the output at

pin 3 switches "LOW".

• Pin 8. − Supply +Vcc, This is the power supply pin and for general purpose TTL 555 timers

is between 4.5V and 15V.


Astable multivibrator circuit diagram

Astable 555 Oscillator

This circuit diagram shows how a 555 timer IC is configured to function as an astable

multivibrator. An astable multivibrator is a timing circuit whose 'low' and 'high' states are both unstable. As such, the output of an astable multivibrator toggles between 'low' and 'high' continuously, in effect generating a train of pulses. This circuit is therefore also known as a 'pulse generator' circuit.

In the 555 Oscillator above, pin 2 and pin 6 are connected together allowing the circuit to re-

trigger itself on each and every cycle allowing it to operate as a free running oscillator. During

each cycle capacitor, C charges up through both timing resistors, R1 and R2 but discharges itself

only through resistor, R2 as the other side of R2 is connected to the Discharge terminal, pin 7.

Then the capacitor charges up to 2/3Vcc (the upper comparator limit) which is determined by the

http://ecelab.com/555-timer.htm


0.693(R1+R2)C combination and discharges itself down to 1/3Vcc (the lower comparator limit)

determined by the 0.693(R2.C) combination. This results in an output waveform whose voltage

level is approximately equal to Vcc - 1.5V and whose output "ON" and "OFF" time periods are

determined by the capacitor and resistors combinations. The individual times required to

complete one charge and discharge cycle of the output is therefore given as:

Astable 555 Oscillator Charge and Discharge Times

Where, R is in Ω's and C in Farads.

When connected as an Astable Multivibrator, the output from the 555 Oscillator will continue

indefinitely charging and discharging between 2/3Vcc and 1/3Vcc until the power supply is

removed. As with the Monostable Multivibrator these charge and discharge times and therefore

the frequency are independent of the supply voltage. The duration of one full cycle is therefore

equal to the sum of the two individual times that the capacitor charges and discharges added

together and is given as:

555 Oscillator Total Time Period

The output frequency of oscillations can be found by inverting the equation above for the total

cycle time giving a final equation for the output frequency of an Astable 555 Oscillator as:

555 Oscillator Frequency Equation

By altering the time constant of just one of the RC combinations, the Duty Cycle better known

as the "Mark-to-Space" ratio of the output waveform can be accurately set and is given as the

ratio of resistor R2 to resistor R1. The Duty Cycle for the 555 Oscillator, which is the ratio of the

"ON" time divided by the "OFF" time is given by:

555 Oscillator Duty Cycle

The duty cycle has no units as it is a ratio but can be expressed as a percentage (%). If both

timing resistors, R1 and R2 are equal the output duty cycle will be given as 2:1 or 33%.


Monostable multivibrator circuit diagram:

This circuit diagram shows how a 555 timer IC is configured to function as a basic monostable multivibrator. A monostable multivibrator is a timing circuit that changes state once triggered, but returns to its original state after a certain time delay. It got its name from the fact that only one of its output states is stable. It is also known as a 'one-shot'. In this circuit, a negative pulse applied at pin 2 triggers an internal flip-flop that turns off pin 7's discharge transistor, allowing C1 to charge up through R1. At the same time, the flip-flop brings the output (pin 3) level to 'high'. When capacitor C1 as charged up to about 2/3 Vcc, the flip-flop is triggered once again, this time making the pin 3 output 'low' and turning on pin 7's discharge transistor, which discharges C1 to ground. This circuit, in effect, produces a pulse at pin 3 whose width t is just the product of R1 and C1, i.e., t=R1C1. The reset pin, which may be used to reset the timing cycle by pulling it momentarily low, should be tied to the Vcc if it will not be used.

Pin 1 is grounded. Trigger input is applied to pin 2. In quiescent condition of output this input is

kept at + VCC. To obtain transition of output from stable state to quasi-stable state, a negative-

going pulse of narrow width (a width smaller than expected pulse width of output waveform)

and amplitude of greater than + 2/3 VCC is applied to pin 2. Output is taken from pin 3. Pin 4 is

usually connected to + VCC to avoid accidental reset. Pin 5 is grounded through a 0.01 u F

capacitor to avoid noise problem. Pin 6 (threshold) is shorted to pin 7. A resistor RA is connected

between pins 6 and 8. At pins 7 a discharge capacitor is connected while pin 8 is connected to

supply VCC. Example problem:

An Astable 555 Oscillator is constructed using the following components, R1 = 1kΩ, R2 = 2kΩ

and capacitor C = 10uF. Calculate the output frequency from the 555 oscillator and the duty

cycle of the output waveform.


t1 - Charge time ("ON") is calculated as:

t2 - Discharge time ("OFF") is calculated as:

Total periodic time is calculated as:

The Output Frequency is therefore calculated as:

Giving a Duty Cycle value of:

Example problem:

Monostable 555 Timer is required to produce a time delay within a circuit. If a 10uF timing

capacitor is used calculate the value of the resistor required to produce an output time delay of

500mS.

500mS is the same as saying 0.5s so by rearranging the formula above, we get the calculated

value for the resistor, R as:


Tabulation:

Astable Multivibrator:

Theoritical Practical

ON time

OFF time

% Duty cycle

Frequency

Monostable Multivibrator:


ON time

OFF time

% Duty cycle

Frequency

RESULT:

Thus multivibrators were designed using 555 timer IC to generate square pulse wave form.


Expt.NO:11

AIM:

To design a differentiator and Integrator circuit using op-amps IC 741.

Apparatus required:

1.IC 741

2.Resistors 3.Capacitors

4.AFO

5.CRO 6.Bread board

7.Connecting wires

Pin diagram of IC 741 op-amp

An operational amplifier, often referred as an op-amp, is a very high gain performance amplifier

designed to amplify ac and dc voltage voltages used to perform arithmetic operations (addition,

subtraction, multiplication) with signals. In fact, op amps can also be used to integrate (calculate

the areas under) and differentiate (calculate the slopes of) signals.


A differentiator circuit produces a constant output voltage for a steadily changing input

voltage.

An integrator circuit produces a steadily changing output voltage for a constant input voltage.

Both types of devices are easily constructed, using reactive components (usually capacitors

rather than inductors) in the feedback part of the circuit.

Integrator

In this circuit we have replaced the feedback resistor with a capacitor. Therefore, any feedback

current must be based on a change in output voltage. As feedback current flows, the capacitor

will gain an electric charge, which will change according to the cumulative effects of the output

signal.

If the input voltage is zero, no input current will flow. Therefore no feedback current can flow

and the output voltage will remain constant. If the input voltage is non-zero, the basic equation

for the output voltage becomes Vout = -Vin/RC + K, where R is the input resistance in ohms, C is

the feedback capacitance in farads, and K is a fixed constant representing the accumulated

voltage from the past.

If the input voltage is constantly changing, the output voltage at any instant will be the integral of

all past input voltage values. For example, a bipolar sine wave input will actually produce

another sine wave as its output, at a phase angle of 90° from the input sine wave. Technically,

the output will be an inverted cosine wave.

The formula for determining voltage output for the integrator is as follows:


Differentiator:

The circuit to the right shows an op amp connected as a differentiator. Since the input circuit

element is a capacitor, this circuit will only experience input current in response to changes in

input voltage — the faster and larger the change in input voltage, the greater the input current,

therefore the greater the output voltage in response.

Since the output voltage will reflect the rate of change of the input, this circuit will indeed

perform differentiation. The general equation for the output voltage is:

Vout = -RC

dVin

dt

The "d/dt" notation indicates differentiation with respect to time. If you're not familiar with

differential calculus, don't worry about it here; you won't need it for these pages.


The op amp differentiator is not used in any analog computer application, and indeed not

generally. The basic reason for this is that high-frequency noise signals will not be suppressed by

this circuit; rather they will be amplified far beyond the amplification of the desired signal.

The formula for determining voltage output for the differentiator is as follows:

In some applications, it may be possible to add a series input resistor, as shown in the schematic

diagram to the right. This limits the high frequency gain of the circuit to the ratio Rf/Rin. The low

frequency gain is still set by Rf and C, as before. The cutoff frequency, where these two effects

meet, is determined by Rin and C, according to the expression: fco = 1/2 RinC.

Higher-frequency signals are still amplified more than low-frequency signals, so any noise

present in the circuit will still be amplified more than the desired signal. If an application can

suppress such noise and doesn't require higher-frequency components, this modified circuit may

serve the need. In other cases, if differentiation is absolutely required, a passive RC circuit is

generally used instead, and the inevitable signal losses compensated later.

Linear Integrating and Non-Integrating Amplifiers:

Op-amps can be used in an enormous variety of different types of circuit but one of the most

common is within amplifier circuits themselves. Here they enable high performance circuits to

be made with a minimum number of components.

There are two common formats for amplifiers using op-amp based circuits:

Non-inverting amplifier circuit: - here the output is in the same sense as the input signal,

i.e. when the input voltage goes positive, so does the output.

In this circuit, the input signal is effectively used as the reference voltage at the "+" input

to the differential amplifier, while the "-" input is indirectly referenced to ground. In

order to keep the two input voltages to the amplifier the same, the amplifier must set Vout

to whatever voltage is required to make the feedback voltage to the "-" input match the

input voltage to the "+" input.

Since Rf and Rin form a voltage divider, the feedback voltage will be VoutRin/(Rf + Rin).

The gain of this circuit, then, calculated as Vout/Vin, is (Rf + Rin)/Rin, or (Rf/Rin) + 1.

Resistor Rz has no effect on the gain of the circuit. However, to balance out variations

caused by the small input current to the amplifier, Rz should be made equal to the parallel

combination of Rf and Rin.


Inverting amplifier circuit: - here the output is an inverted version (upside down) of the

signal that enters the circuit, i.e. when the input voltage goes more positive, the output

goes more negative.

Procedure:

a) Put the op amp in the breadboard and connect +Vcc and -Vcc to the chip. Set the

magnitude of Vcc to 12 volts (you will have to check this with a voltmeter). Connect the

rest of the circuit with R1=10kΩ and Rf=30kΩ. You should verify that the resistor values

are correct by reading them off the resistor (they are sometimes in the wrong drawer).

b) Derive an expression for vout/vin for the inverting amplifier, in terms of R1 and Rf.

c) Now drive the inverting amplifier with a 1 kHz sine wave, that is 2 volts peak-to-peak.

Hook up the oscilloscope so you can see both vin and vout. What is the gain? What is the

maximum output swing

HOW TO CALCULATE THE 'GAIN'

An operational amplifiers purpose is to amplify a weak signal and this is called the GAIN.

INVERTING AMPLIFIER

GAIN (AV) = -R2 / R1

Example : if R2 is 100 kilo-ohm and R1 is 10 kilo-ohm the gain would be :

-100 / 10 = -10 (Gain AV)

If the input voltage is 0.5v the output voltage would be :

http://www.swarthmore.edu/NatSci/echeeve1/Ref/Resistor/resistor.html


0.5v X -10 = -5v

NON-INVERTING AMPLIFIER

GAIN (AV) = 1+(R2 / R1)

Example : if R2 is 1000 kilo-ohm and R1 is 100 kilo-ohm the gain would be :

1+ (1000/100) = 1 + 10

OR

GAIN (AV) = 11

If the input voltage is 0.5v the output voltage would be :

0.5 X 11 = 5.5v

Result: The


Expt.No 12

STUDY OF VCO AND PLL

Introduction to PLL or Phase Locked Loops

Phase-locked loop is a feedback loop consisting of a phase detector, a low-pass filter, amplifier

(optional) and a voltage-controlled oscillator (VCO), as illustrated in figure. It plays the same

role in the frequency or phase world as the op-amp does in the voltage world. The op-amp has

two voltage inputs, non-inverting and inverting (normally used for feedback from the output).

Similarly, the PLL has two inputs; the PLL’s feedback input is normally connected to the

circuits’ output. Digital frequencies are usually applied. The op-amp changes its output voltage

to whatever values is necessary to drive the difference in voltage between its two inputs to zero.

The PLL changes its output phase and frequency to whatever frequency or phase is necessary to

make the two input frequencies and phase track. Placing a voltage divider in the feedback loop of

an op-amp causes the output voltage to be increased by the amount of the feedback voltage

division (amplification). Placing a frequency divider in the feedback of a PLL causes the output

frequency to be increased by the amount of the feedback divider. A firm grasp on similarities

between the PLL and the op-amp simplifies our analysis and design of circuits containing PLLs.

Phase Locked Loop

With the rapid development of IC technology, the phase-locked loop (PLL) has emerged as one of the fundamental building blocks in electronic technology.

Phase Detector

A phase detector is basically a comparator that compares the input frequency fin with feedback

frequency fout. The phase detector receives two digital signals, one from the input, the other

feedback from the output. The loop is locked when these two signals are of the same frequency

and have a fixed phase difference (A locked PLL is analogous to an op-amp not being saturated).

The output of a phase detector is a dc voltage and therefore is often referred to as the error

voltage, Ve. DC output voltage becomes maximum when the phase difference between the two

frequencies fin and fout is ∏ radians or 180°. Without input signal, the error voltage Ve is equal to

zero and the VCO operates at a set frequency ‘fr‘ which is also called free-running frequency of

the VCO. When the input signal frequency is the same as that from the VCO to the PC, the

voltage, Vd, taken as output is the value required to hold the VCO in lock with the input signal. If

http://www.circuitstoday.com/op-amps-operational-amplifiers


the two input pulses to the PC are of exactly the same frequency and phase, the output of the PC

is zero, otherwise there I will be an output proportional to their phase difference.

Low-pass filter

Low-pass filter is used to remove high frequency components and noise from the output of the

phase detector. It affects the dynamic characteristics of the PLL including bandwidth, capture

and lock ranges and transient response. The low-pass filter accepts the output from the phase

detector, removes the high frequency noise and produces a dc level.

Voltage Controlled Oscillator (VCO)

Voltage-controlled oscillator generates frequency controlled by input voltage. The dc level

output of a low-pass filter is applied as control signal to the voltage-controlled oscillator (VCO).

The output frequency of the VCO is directly proportional to the input dc level. The VCO

frequency is adjusted till it becomes equal to the frequency of the input signal. During this

adjustment, PLL goes through three stages-free running, capture and phase lock. Best operation

is obtained if the centre frequency of the VCO is set with the dc bias voltage midway in its linear

operating range. The amplifier allows this adjustment in dc voltage from that obtained as output

of the filter circuit. When the loop is in lock, the two signals to the PC are necessarily of the

same frequency although not necessarily in phase. A fixed phase difference between the two

signals to the comparator results in a fixed dc voltage to the VCO. Variation in the input signal

frequency then causes variation in the dc voltage to the VCO. Within a capture-and-Iock

frequency range, the dc voltage will drive the VCO frequency to match that of the input.

While the loop is trying to achieve lock, the output of the PC contains frequency components at

the sum and difference of the signals compared. A low-pass filter passes only the lower-

frequency component of the signal so that the loop can obtain lock between input and VCO

signals.

Owing to the limited operating range of the VCO and the feedback connection of the PLL

circuit, there are two important frequency bands specified for a PLL. The capture range of a PLL

is the range of frequencies centred about the VCO free-running frequency fr, over which the

output signal frequency of the VCO can acquire lock with the input signal frequency. Once the

PLL has achieved capture, it can maintain lock with the input signal over a somewhat wider

frequency range called the lock range.

Common applications of a PLL include

(i) frequency synthesizers that provide multiples of a reference signal frequency;

(ii) FM demodulation networks for FM operation with excellent linearity between the input

signal frequency and the PLL output voltage;

(iii) demodulation of the two data transmission or carrier frequencies in digital-data transmission

employed in frequency-shift keying (FSK) operation;


(iv) a wide variety of areas including telemetry receivers and transmitters, tone decoders, AM

detectors, tracking filters and motor speed controls.

Although the evolution of the PLL began in the early 1930s but its cost outweighted its

advantage in the beginning. Today the PLL is even available as a single package, typical

examples of which are the Signetic’s SE/NE series such as 560, 561, 562, 564, 565 and 567.

They only differ in operating frequency range, power requirements, and frequency and

bandwidth (BW) adjustment ranges. SE/NE 565 is the most widely employed IC of the series.

The device is available as a 14-pin DIP package and as a 10-pin metal can package. Its

important electrical characteristics are given below:

PLL PIN IDENTIFICATION

Voltage controlled oscillator

http://www.circuitstoday.com/pll-phase-locked-loops


In most cases, the frequency of an oscillator is determined by the time constant RC. However, in

cases or applications such as FM, tone generators, and frequency-shift keying (FSK), the

frequency is to be controlled by means of an input voltage, called the control voltage. This can

be achieved in a voltage-controlled oscillator (VCO). A VCO is a circuit that provides an

oscillating output signal (typically of square-wave or triangular waveform) whose frequency

can be adjusted over a range by a dc voltage. An example of a VCO is the 566 IC unit, that

provides simultaneously the square-wave and triangular-wave outputs as a function of input

voltage. The frequency of oscillation is set by an external resistor R1 and a capacitor C1 and the

voltage Vc applied to the control terminals. Figure shows that the 566 IC unit contains current

sources to charge and discharge an external capacitor Cv at a rate set by an external resistor R1

and the modulating dc input voltage. A Schmitt trigger circuit is employed to switch the current

sources between charging and discharging the capacitor, and the triangular voltage produced

across the capacitor and square-wave from the Schmitt trigger are provided as outputs through

buffer amplifiers. Both the output waveforms are buffered so that the output impedance of each

is 50 f2. The typical magnitude of the triangular wave and the square wave are 2.4 Vpeak.to-peak

and 5.4Vpeak.to.peak.

The frequency of the output waveforms is approximated by

fout = 2(V+

- Vc)/R1C1V+

Figure shows the pin connection of the 566 unit. The VCO can be

programmed over a 10-to-l frequency range by proper selection of an external resistor and

capacitor, and then modulated over a 10-to-l frequency range by a control voltage, Vc The

voltage controlled oscillators (VCOs) are commonly used in converting low-frequency signals

such as EEG (electro-encephalograms) or ECG (electro-cardiograms) into an audiofrequency

(AF range)


MULTIVIBRATOR USING 555 TIMER

AIM:

To design and construct the astable and mono stable multivibrator using 555 timer. Draw

the waveform.

APPARATUS REQUIRED:

S.No Apparatus Range Quantity

1.

2.

3.

4.

5.

6.

7.

8.

Resistor

Capacitor

Timer IC

RPS

AFO

CRO

Bread board

Connecting wires

6.8kΩ,10kΩ

470Ω

470pF,

.1nF,1μF

NE555

-

-

(0-30)v

-

-

1,2

1

1,1

1

1

1

1

1

1

-

DESIGN:

Astable multivibrator:

For 50% duty cycle:

Tc= 0.69(Ra+Rb)*C

Td= 0.69Rb* C

T = Tc+Td

T = 0.69(Ra+2Rb)*C

f = 1/T = 1.45/(Ra+2Rb)*C

% Duty cycle D = Td/T*100

D = Ra/(Ra+2Rb)*C

Let Tc = Td = 0.05 msec

Choose C = 10nf

0.05*10-3

= 0.69(Ra+Rb)*10n

Therefore Ra+Rb = 7.215k

Choose Ra=470Ω

Rb=6.8kΩ



Tp = 1.1 RC

For Tp = 0.1ms

Choose C= 0.01μF

To Find R

R =Tp/1.1C=10KΩ

PROCEDURE:

Astable multivibrator:

1. Connections are made as per the circuit diagram.

2. The output waveforms are viewed through CRO.

3. The voltage across the capacitor and that at the output terminal is measured

and the waveforms are drawn.

Monostable multivibrator:

1. Connections are made as per the circuit diagram.

2. A low frequency trigger pulse is applied.

3. The output waveforms are viewed through CRO.

4. The voltage across the capacitor and that at the output terminal is measured

and the waveforms are drawn.

ASTABLE MULTIVIBRATOR:

R1

1k

R2

1k

C1

1n C2

1n

21

8 4

3

6

7

5

555

v cc

o/p


MONOSTABLE MULTIVIBRATOR:

Theory:

Astable multivibrator: An astable multivibrator is a wave-generating circuit in which neither of the output levels is

stable. The output keeps on switching between the two unstable states and is a periodic,

rectangular waveform. The circuit is therefore known as an ‘astable multivibrator’. Also, no

external trigger is required to change the state of the output, hence it is also called ‘free-running

multivibrator’. The time for which the output remains in one particular state is determined by the

two resistors and a capacitor externally connected to the 555 timer.

An astable multivibrator is a timing circuit whose 'low' and 'high' states are both unstable. As such, the output of an astable multivibrator toggles between 'low' and 'high' continuously, in effect generating a train of pulses. This circuit is therefore also known as a 'pulse generator' circuit.

In the 555 Oscillator above, pin 2 and pin 6 are connected together allowing the circuit to re-

trigger itself on each and every cycle allowing it to operate as a free running oscillator. During

each cycle capacitor, C charges up through both timing resistors, R1 and R2 but discharges itself

only through resistor, R2 as the other side of R2 is connected to the Discharge terminal, pin 7.

Then the capacitor charges up to 2/3Vcc (the upper comparator limit) which is determined by the

0.693(R1+R2)C combination and discharges itself down to 1/3Vcc (the lower comparator limit)

determined by the 0.693(R2.C) combination. This results in an output waveform whose voltage

level is approximately equal to Vcc - 1.5V and whose output "ON" and "OFF" time periods are

determined by the capacitor and resistors combinations

R2

2 1k

k

C1

1 1n

n

C2

2 1n

n

2

1

4

3

7

5

8

6

vcc

555

5

o/p

p C3

3

1n

n R3

3 1k

k

D1

1

DIODE

E

I/P

P


Monostable Multivibrator: A monostable multivibrator is a pulse-generating circuit having one stable and one quasi-stable

state. Since there is only one stable state, the circuit is known as ‘monostable multivibrator’. The

duration of the output pulse is determined by the RC network connected externally to the 555

timer. The stable state output is approximately zero or at logic-low level. An external trigger

pulse forces the output to become high or approximately. After a predetermined length of time,

the output automatically switches back to the stable state and remains low until a trigger pulse is

again applied. The cycle then repeats. That is, each time a trigger pulse is applied, the circuit

produces a single pulse. Hence, it is also called ‘one-shot multivibrator’.

A monostable multivibrator is a timing circuit that changes state once triggered, but returns to its original state after a certain time delay. It got its name from the fact that only one of its output states is stable. It is also known as a 'one-shot'. Pin 1 is grounded. Trigger input is applied to pin 2. In quiescent condition of output this input is

kept at + VCC. To obtain transition of output from stable state to quasi-stable state, a negative-

going pulse of narrow width (a width smaller than expected pulse width of output waveform)

and amplitude of greater than + 2/3 VCC is applied to pin 2. Output is taken from pin 3. Pin 4 is

usually connected to + VCC to avoid accidental reset. Pin 5 is grounded through a 0.01 u F

capacitor to avoid noise problem. Pin 6 (threshold) is shorted to pin 7. A resistor RA is connected

between pins 6 and 8. At pins 7 a discharge capacitor is connected while pin 8 is connected to

supply VCC.

Tabulation:

Astable Multivibrator:


ON time

OFF time

% Duty cycle

Frequency



ON time

OFF time

% Duty cycle

Frequency

RESULT:

The astable and mono stable multivibrator using 555 timer are designed and the

waveforms are drawn.

linear integrated circuits lab manual

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