lm76002/lm76003 3.5-v to 60-v, 2.5-a/3.5-a … typical applications ..... 24 9 power supply...

Load Current (A)

Effi

cien

cy (

%)

0.01 0.1 1 550

10

20

30

40

50

60

70

80

90

100

D013

VIN = 12 VVIN = 24 VVIN = 48 V

LM76003

VIN PVIN

EN

BOOT

SW

FB

AGND

VOUT

CBOOT

LCIN

COUT

RFBT

RFBBVCC

BIAS

PGND

CVCC

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SS/TRK

RT

SYNC/MODE

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Folder

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Now

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM76002, LM76003SNVSAK0 –OCTOBER 2017

LM76002/LM76003 3.5-V to 60-V, 2.5-A/3.5-A Synchronous Step-Down Voltage Regulator

1

1 Features1• Integrated Synchronous Rectification• Input Voltage 3.5 V to 60 V (65 V Maximum)• Output Current:

– LM76002: 2.5 A– LM76003: 3.5 A

• Output Voltage 1 V to 95% VIN

• 15-µA Quiescent Current in Regulation• Wide Voltage Conversion Range

– tON-MIN = 65 ns (Typical)– tOFF-MIN = 95 ns (Typical)

• System-Level Features– Synchronization to External Clock– Power-Good Flag– Precision Enable– Adjustable Soft Start (6.3 ms Default)– Voltage Tracking Capability

• Pin-Selectable FPWM Operation• High-Efficiency at Light-Load Architecture (PFM)• Protection Features

– Cycle-by-Cycle Current Limit– Short-Circuit Protection With Hiccup Mode– Overtemperature Thermal Shutdown

Protection• Create a Custom Design Using the LM76002/03

With the WEBENCH® Power Designerspace

Simplified Schematic

2 Applications• Telecommunications Infrastructure• Asset and Fleet Management Systems• Video Surveillance• Programmable Logic Controllers

3 DescriptionThe LM76002/LM76003 regulator is an easy-to-usesynchronous step-down DC-DC converter capable ofdriving up to 2.5 A (LM76002) or 3.5 A (LM76003) ofload current from an input up to 60 V. TheLM76002/LM76003 provides exceptional efficiencyand output accuracy in a very small solution size.Peak current-mode control is employed. Additionalfeatures such as adjustable switching frequency,synchronization, FPWM option, power-good flag,precision enable, adjustable soft start, and trackingprovide both flexible and easy-to-use solutions for awide range of applications. Automatic frequencyfoldback at light load and optional external biasimprove efficiency. This device requires few externalcomponents and has a pinout designed for simplePCB layout with best-in-class EMI (CISPR22) andthermal performance. Protection features includethermal shutdown, input undervoltage lockout, cycle-by-cycle current limit, and short-circuit protection. TheLM76002/LM76003 device is available in the WQFN30-pin leadless package with wettable flanks.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)LM76002

WQFN (30) 6.00 mm × 4.00 mmLM76003

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

space

space

Efficiency vs Output Current(VOUT = 5 V, fSW = 500 kHz, Auto Mode)

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Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Pin Configuration and Functions ......................... 36 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 56.2 ESD Ratings.............................................................. 56.3 Recommended Operating Conditions....................... 56.4 Thermal Information .................................................. 66.5 Electrical Characteristics........................................... 66.6 Timing Characteristics............................................... 86.7 Switching Characteristics .......................................... 86.8 System Characteristics ............................................. 96.9 Typical Characteristics ............................................ 10

7 Detailed Description ............................................ 127.1 Overview ................................................................. 127.2 Functional Block Diagram ....................................... 12

7.3 Feature Description................................................. 137.4 Device Functional Modes........................................ 22

8 Application and Implementation ........................ 248.1 Application Information............................................ 248.2 Typical Applications ............................................... 24

9 Power Supply Recommendations ...................... 4210 Layout................................................................... 42

10.1 Layout Guidelines ................................................. 4210.2 Layout Example .................................................... 4510.3 Thermal Design..................................................... 46

11 Device and Documentation Support ................. 4711.1 Device Support...................................................... 4711.2 Receiving Notification of Documentation Updates 4711.3 Community Resources.......................................... 4711.4 Trademarks ........................................................... 4711.5 Electrostatic Discharge Caution............................ 4711.6 Glossary ................................................................ 47

12 Mechanical, Packaging, and OrderableInformation ........................................................... 48

4 Revision History

DATE REVISION NOTESOctober 2017 * Initial release



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2

3

4 23

25

24

PVIN

SW

SW

DAP PVIN

PGNDSW

22

261

5SW

SW

NC

216

VCC

PGND

PGND

RT

BIAS

207 PVIN

PGOOD

198 NC

SS/TRK

9

10

18

17

EN

BOOT

FB

SYNC/MODE

1611

29 28 2730

13 14 1512

NCNCNCNC

AGNDAGNDAGND

NC

3

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5 Pin Configuration and Functions

RNP Package30-Pin WQFN

Top View



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4




(1) A = Analog, O = Output, I = Input, G = Ground, P = Power

Pin FunctionsPIN

I/O (1) DESCRIPTIONNO. NAME

1, 2, 3, 4, 5 SW P Switching output of the regulator. Internally connected to source of the HS FET and drain ofthe LS FET. Connect to power inductor and boot-strap capacitor.

6 BOOT P Boot-strap capacitor connection for high-side driver. Connect a high-quality 470-nFcapacitor from this pin to the SW pin.

7, 19, 23, 27,28, 29, 30 NC — Not internally connected. Connect to ground copper on PCB to improve heat-sinking of the

device and board level reliability.

8 VCC POutput of internal bias supply. Used as supply to internal control circuits. Connect a high-quality 2.2-µF capacitor from this pin to GND. TI does not recommended loading this pin byexternal circuitry.

9 BIAS POptional BIAS LDO supply input. TI recommends tying this to VOUT when 3.3 V ≤ VOUT ≤ 18V, or tying to an external 3.3-V or 5-V rail if available, to improve efficiency. When used,place a 1-µF capacitor from this terminal to ground. Tie to ground when not in use.

10 RT A Switching frequency setting pin. Place a resistor from this pin to ground to set the switchingfrequency. If floating, the default switching frequency is 500 kHz. Do not short to ground.

11 SS/TRK A

Soft-start-control pin. Leave this pin floating to use the 6.3-ms internal soft-start ramp. Anexternal capacitor can be connected from this pin to ground to extend the soft-start time. A2-µA current sourced from this pin can charge the capacitor to provide the ramp. Connectto external ramp for tracking. Do not short to ground.

12 FB A Feedback input for output voltage regulation. Connect a resistor divider to set the outputvoltage. Never short this terminal to ground during operation.

16 PGOOD AOpen-drain power-good flag output. Connect to suitable voltage supply through a currentlimiting resistor. High = VOUT regulation OK, Low = VOUT regulation fault. PGOOD = Lowwhen EN = Low.

17 SYNC/MODE A

Synchronization input and mode setting pin. Do not float, tie to ground if not used. Tie toground: DCM/PFM operation under light loads, improved efficiency; tie to logic high: forcedPWM under light loads, constant switching frequency over load; tie to external clock source:synchronize switching action to the clock, forced PWM under light loads. Triggers on therising edge of external clock.

18 EN A Precision-enable input to regulator. Do not float. High = on, Low = off. Can be tied to VIN.Precision-enable input allows adjustable UVLO by external resistor divider.

13, 14, 15 AGND G Analog ground. Ground reference for internal references and logic. All electrical parametersare measured with respect to this pin. Connect to system ground on PCB.

20, 21, 22 PVIN PSupply input to internal bias LDO and HS FET. Connect to input supply and input bypasscapacitors CIN. CIN must be placed right next to this pin and PGND and connected withshort traces.

24, 25, 26 PGND G Power ground, connected to the source of LS FET internally. Connect to system ground,DAP/EP, AGND, ground side of CIN and COUT. Path to CIN must be as short as possible.

EP DAP —Low impedance connection to AGND. Connect to system ground on PCB. Major heatdissipation path for the die. Must be used for heat sinking by soldering to ground copper onPCB. Thermal vias are preferred.



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5




(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the de vice. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratingsover operating free-air temperature range of –40°C to +125°C (unless otherwise noted) (1)

PARAMETER MIN MAX UNIT

Input voltages

PVIN to PGND –0.3 65

V

EN to AGND –0.3 VIN + 0.3FB, RT, SS/TRK to AGND –0.3 5PGOOD to AGND –0.1 20SYNC to AGND –0.3 5.5BIAS to AGND –0.3 Lower of (VIN + 0.3) or 30AGND to PGND –0.3 0.3

Output voltages

SW to PGND –0.3 VIN + 0.3

VSW to PGND less than 10-ns transients –3.5 65BOOT to SW –0.3 5.5VCC to AGND –0.3 5.5

Operating junction temperature, TJ –40 150 °CStorage temperature, Tstg –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD RatingsVALUE UNIT

V(ESD) Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000

VCharged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500

(1) Recommended operating rating indicate conditions for which the device is intended to be functional, but do not ensure specificperformance limits. For ensured specifications, see Electrical Characteristics

6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNIT

Input voltages

PVIN to PGND 3.5 60

V

EN 0 VIN

FB 0 4.5PGOOD 0 18BIAS input not used 0 0.3

BIAS input used 0 Lower of (VIN+ 0.3) or 24

AGND to PGND –0.1 0.1Output voltage VOUT 1 95% of VIN VOutput current IOUT, LM76002 0 2.5 AOutput current IOUT, LM76003 0 3.5 ATemperature Operating junction temperature, TJ –40 125 °C



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6




(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport.

6.4 Thermal Information

THERMAL METRIC (1)LM76002/LM76003

UNITRNP (WQFN)30 PINS

RθJA Junction-to-ambient thermal resistance 29 °C/WRθJC(top) Junction-to-case (top) thermal resistance 24.3 °C/WRθJB Junction-to-board thermal resistance 1.7 °C/WψJT Junction-to-top characterization parameter 0.7 °C/WψJB Junction-to-board characterization parameter 13.6 °C/WRθJC(bot) Junction-to-case (bottom) thermal resistance 5.1 °C/W

(1) Shutdown current includes leakage current of the switching transistors.

6.5 Electrical CharacteristicsLimits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the mostlikely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the followingconditions apply: VIN = 24 V, VOUT = 3.3 V, fSW = 500 kHz.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITSUPPLY VOLTAGE (PVIN PINS)VIN Operating input voltage range 3.5 60 V

ISDShutdown quiescent current;measured at PVIN pin (1)

VEN = 0 VTJ = 25 1.2 10 µA

IQ_NONSWOperating quiescent currentfrom VIN (non-switching)

VEN = 2 V, VFB = 1.5 V, VBIAS = 3.3 Vexternal 0.9 12 µA

ENABLE (EN PIN)

VEN_VCC_HEnable input high level forVCC output VEN rising 1.2 V

VEN_VCC_LEnable input low level for VCCoutput VEN falling 0.3 V

VEN_VOUT_HEnable input high level forVOUT

VEN rising 1.14 1.204 1.25 V

VEN_VOUT_HYSEnable input hysteresis forVOUT

VEN falling hysteresis –150 mV

ILKG_EN Enable input leakage current VEN = 2 V 1.4 200 nAINTERNAL LDO (VCC PIN, BIAS PIN)

VCC Internal VCC voltagePWM operation 3.29 VPFM operation 3.1 V

VCC_UVLOInternal VCC undervoltagelockout

VCC rising 2.96 3.14 3.27 VVCC falling hysteresis –565 mV

VBIAS_ON Input changeoverVBIAS rising 3.11 3.25 VVBIAS falling hysteresis –63 mV

IBIAS_NONSW

Operating quiescent currentfrom external VBIAS (non-switching)

VEN = 2 V, VFB = 1.5 V, VBIAS = 3.3 Vexternal 21 50 µA

VOLTAGE REFERENCE (FB PIN)VFB Feedback voltage PWM mode 0.987 1.006 1.017 V

ILKG_FBInput leakage current at FBpin VFB = 1 V 0.2 60 nA

HIGH SIDE DRIVER (BOOT PIN)

VBOOT_UVLOBOOT - SW undervoltagelockout 1.6 2.2 2.7 V



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7




Electrical Characteristics (continued)Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the mostlikely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the followingconditions apply: VIN = 24 V, VOUT = 3.3 V, fSW = 500 kHz.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(2) This current limit was measured as the internal comparator trip point. Due to inherent delays in the current limit comparator and drivers,the peak current limit measured in closed loop with faster slew rate will be larger, and valley current limit will be lower.

(3) Measured at pins.(4) Ensured by design.

CURRENT LIMITS AND HICCUP

IHS_LIMIT(2) Short-circuit, high-side

current limitLM76002 3.2 4.2 5.3

ALM76003 4.35 5.5 6.8

ILS_LIMIT(2) Low-side current limit

LM76002 2.3 3.2 4.2A

LM76003 3.4 4.2 5.3

INEG_LIMIT Negative current limitLM76002 –2.5

ALM76003 –3.3

VHICCUP Hiccup threshold on FB pin 0.38 0.42 0.46 VIL_ZC Zero cross-current limit 0.05 ASOFT START (SS/TRK PIN)ISSC Soft-start charge current 1.8 2 2.2 µA

RSSDSoft-start dischargeresistance UVLO, TSD, OCP; or EN = 0 V 2 kΩ

POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION

VPGOOD_OVPower-good overvoltagethreshold % of FB voltage 106% 110% 113%

VPGOOD_UVPower-good undervoltagethreshold % of FB voltage 86% 90% 93%

VPGOOD_HYS Power-good hysteresis % of FB voltage 2.5%

VPGOOD_VALIDMinimum input voltage forproper PGOOD function

50-µA pullup to PGOOD pin, VEN = 0 V,TJ = 25°C 1.3 2 V

RPGOOD Power-good on-resistanceVEN = 2.5 V 40 100

ΩVEN = 0 V 30 90

MOSFETS

RDS_ON_HS(3) High-side MOSFET on-

resistance IOUT = 1 A, VBIAS = VOUT = 3.3 V 95 150 mΩ

RDS_ON_LS(3) Low-side MOSFET on-

resistance IOUT = 1 A, VBIAS = VOUT = 3.3 V 45 85 mΩ

THERMAL SHUTDOWN

TSD(4) Thermal shutdown threshold Shutdown threshold 160 °C

Recovery threshold 135 °C



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8




(1) Ensured by design.

6.6 Timing CharacteristicsMIN NOM MAX UNIT

CURRENT LIMITS AND HICCUP

NOC(1) Number of switching cycles

before hiccup is tripped 128 Cycles

tOCOvercurrent hiccup retry delaytime 46 ms

SOFT START (SS/TRK PIN)

tSS Internal soft-start time CSS = OPEN, from EN risingedge to PGOOD rising edge 3.5 6.3 ms

POWER GOOD (PGOOD PIN) and OVERVOLTAGE PROTECTION

tPGOOD_RISEPGOOD rising edge deglitchdelay 80 140 200 µs

tPGOOD_FALLPGOOD falling edge deglitchdelay 80 140 200 µs

6.7 Switching CharacteristicsPARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PWM LIMITS (SW PINS)tON-MIN Minimum switch on-time 65 95 nstOFF-MIN Minimum switch off-time 95 130 nstON-MAX Maximum switch on-time HS timeout in dropout 3.8 8 11.4 µsOSCILLATOR (RT and SYNC PINS)fOSC Internal oscillator frequency RT = open 440 500 560 kHz

fADJ

Minimum adjustable frequency byRT or SYNC RT =133 kΩ, 0.1% 270 300 330 kHz

Maximum adjustable frequency byRT or SYNC RT = 17.4 kΩ, 0.1% 1980 2200 2420 kHz

VSYNC_HIGH Sync input high level threshold 2 VVSYNC_LOW Sync input low level threshold 0.4 VVMODE_HIGH Mode input high level threshold for

FPWM0.42 V

VMODE_LOWMode input low level threshold forAUTO mode 0.4 V

tSYNC_MINSync input minimum on- and off-time 80 ns



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9




6.8 System CharacteristicsThe following specifications apply to the circuit found in the typical Simplified Schematic with appropriate modifications (seeTable 2). These parameters are not tested in production and represent typical performance only. Unless otherwise stated thefollowing conditions apply: TA = 25°C, VIN = 24 V, VOUT = 3.3 V, fSW = 500 kHz.

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VFB_PFMOutput voltage offset at no loadin auto mode

VIN = 3.8 V to 36 V, VSYNC = 0 V, auto modeIOUT = 0 A 2%

Vdrop

Minimum input to outputvoltage differential to maintainspecified accuracy

VOUT = 5 V, IOUT = 1.5 A, fSW = 2.2 MHz 0.4 V

IQ_SWOperating quiescent current(switching)

VEN = 3.3 V, IOUT = 0 A, RT = open, VBIAS =VOUT = 3.3 V, RFBT = 1 Meg 15 µA

IPEAK_MIN Minimum inductor peak current

LM76002:VSYNC = 0 V, IOUT = 10 mA 0.5

ALM76003:VSYNC = 0 V, IOUT = 10 mA 0.7

IBIAS_SWOperating quiescent currentfrom external VBIAS (switching)

fSW = 500 kHz, IOUT = 1 A 7mA

fSW = 2.2 MHz, IOUT = 1 A 25DMAX Maximum switch duty cycle While in frequency foldback 97.5%

tDEADDead time between high-sideand low-side MOSFETs 4 ns



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Temperature (qC)

Cur

rent

Lim

its (

A)

-40 -20 0 20 40 60 80 100 120 1402

2.5

3

3.5

4

4.5

5

D005

HS LimitLS Limit

Temperature (qC)

Fre

quen

cy (

kHz)

-40 -20 0 20 40 60 80 100 120 1400

250

500

750

1000

1250

1500

1750

2000

2250

2500

D006

FREQ = 300 kHzFREQ = 1 MHzFREQ = 2.2 MHz

Input Voltage (V)

Fee

dbac

k V

olta

ge (

V)

0 6 12 18 24 30 36 42 48 54 601

1.001

1.002

1.003

1.004

1.005

1.006

1.007

1.008

D003

Temp = 40qCTemp = 25qCTemp = 125qC

Temperature (qC)

Cur

rent

Lim

its (

A)

-40 -20 0 20 40 60 80 100 120 1403

3.5

4

4.5

5

5.5

6

D004

HS LimitLS Limit

Temperature (qC)

Shu

tdow

n C

urre

nt (

nA)

-40 -20 0 20 40 60 80 100 120 140200300400500600700800900

100011001200130014001500160017001800

D002

VIN = 24 VVIN = 3.5 VVIN = 60 V

Temperature (qC)

RD

S-O

N (

m:

)

-40 -20 0 20 40 60 80 100 120 14020

30

40

50

60

70

80

90

100

110

120

130

140

D001

HS SwitchLS Switch

10




6.9 Typical CharacteristicsUnless otherwise specified, VIN = 24 V, VOUT = 3.3 V, fSW = 500 kHz. Curves represent most likely parametric norm atspecified condition.

Figure 1. High-Side and Low-Side Switch RDS-ON Figure 2. Shutdown Quiescent Current

Figure 3. Feedback Voltage Figure 4. LM76003 High-Side and Low-Side Current Limits

Figure 5. LM76002 High-Side and Low-Side Current Limits Figure 6. Switching Frequency Set by RT Resistor



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Temperature (qC)

PG

OO

D T

hres

hold

(%

)

-40 -20 0 20 40 60 80 100 120 14085

90

95

100

105

110

115

D009

OV TrippingOV RecoveryUV RecoveryUV Tripping

Temperature (qC)

Sw

itchi

ng F

requ

ency

RT

ope

n (k

Hz)

-40 -20 0 20 40 60 80 100 120 140450

460

470

480

490

500

510

520

530

540

550

D007

VIN = 12 VVIN = 3.5 VVIN = 60 V

Temperature (qC)

Ena

ble

Thr

esho

lds

(V)

-40 -20 0 20 40 60 80 100 120 1400.2

0.4

0.6

0.8

1

1.2

1.4

D008

VEN_VOUT RisingVEN_VOUT FallingVEN_VCC RisingVEN_VCC Falling

11




Typical Characteristics (continued)Unless otherwise specified, VIN = 24 V, VOUT = 3.3 V, fSW = 500 kHz. Curves represent most likely parametric norm atspecified condition.

Figure 7. Switching Frequency With RT Open Figure 8. Enable Threshold

Figure 9. PGOOD Threshold



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REF

PVIN

BIAS

PGOOD

EN

CONTROL LOGIC

AGND

PGND

Oscillator

LDO

SYNC/MODE

VCC

SW

FB

HS I Sense

EA

RT

UVLO

HICCUP Detector

Internal SS

OV/UV Detector

+

PFM Detector

Slope Comp

+

±

PrecisionEnable

LS I Sense

PGood

FB

RC

CC

ISSC

+ ±

ICMD

ICMD

+±

VCC

CLK

FPWM

TSD

VBOOT

VBOOT

UVLO

SS/TRK


BOOT

12




7 Detailed Description

7.1 OverviewThe LM76002/LM76003 regulator is an easy-to-use synchronous step-down DC-DC converter that operates from3.5-V to 60-V supply voltage. The device is capable of delivering up to 2.5-A or 3.5-A DC load current withexceptional efficiency and thermal performance in a very small solution size.

The LM76002/LM76003 employs fixed-frequency peak-current-mode control with configurable discontinuousconduction mode (DCM) and pulse frequency modulation (PFM) mode at light load to achieve high efficiencyacross the load range. The device can also be configured as forced-PWM (FPWM) operation to keep constantswitching frequency over the load range. The device is internally compensated, which reduces design time andrequires fewer external components. The switching frequency is programmable from 300 kHz to 2.2 MHz by anexternal resistor. The LM76002/LM76003 is also capable of synchronization to an external clock operating withinthe 300-kHz to 2.2-MHz frequency range. The wide switching frequency range allows the device to meet a widerange of design requirements. It can be optimized to very small solution size with higher frequency or to veryhigh efficiency with lower switching frequency. It has very small minimum HS MOSFET on-time (tON-MIN) andminimum off-time (tOFF-MIN) to provide wide range of voltage conversion. Automated frequency foldback isemployed under tON-MIN or tOFF-MIN condition to further extend the operation range.

The LM76002/LM76003 also features a power-good (PGOOD) flag, precision enable, internal or adjustable soft-start rate, start-up with pre-bias voltage, and output voltage tracking. It provides a both flexible and easy-to-usesolution for wide range of applications. Protection features include thermal shutdown, VCC undervoltage lockout,cycle-by-cycle current limiting, and short-circuit hiccup protection.

The family requires very few external components and has a pinout designed for simple, optimum PCB layout forEMI and thermal performance. The LM76002/LM76003 device is available in a 30-pin WQFN lead-less package.

7.2 Functional Block Diagram



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VSW

VIN

D = tON/ TSW

tON tOFF

TSW

t

-VD

0

SW

Vol

tage

iL

IOUT

t0

Indu

ctor

Cur

rent ILPK

ûiL

13




7.3 Feature Description

7.3.1 Fixed-Frequency, Peak-Current-Mode ControlThe following operation description of the LM76002/LM76003 refers to the Functional Block Diagram and to thewaveforms in Figure 10. The LM76002/LM76003 supplies a regulated output voltage by turning on the internalhigh side (HS) and low side (LS) NMOS switches with varying duty cycle (D). During high-side switch on-timetON, the SW pin voltage VSW swings up to approximately VIN, and the inductor current iL increase with linearslope. The HS switch is off by the control logic. During the HS switch off-time, tOFF, the LS switch is turned on.Inductor current discharges through the LS switch, which forces the VSW to swing below ground by the voltagedrop across the LS switch. The regulator loop adjusts the duty cycle to maintain a constant output voltage. Thecontrol parameter of buck converter is defined as duty cycle D = tON / tSW. In an ideal buck converter, wherelosses are ignored, D is proportional to the output voltage and inversely proportional to the input voltage: D =VOUT / VIN.

Figure 10. SW Node and Inductor Current Waveforms inContinuous Conduction Mode

The LM76002/LM76003 synchronous buck converter employs peak current-mode control topology. A voltage-feedback loop is used to get accurate DC-voltage regulation by adjusting the peak current command based onvoltage offset. The peak inductor current is sensed from the HS switch and compared to the peak current tocontrol the on-time of the HS switch. The voltage feedback loop is internally compensated, which allows for fewerexternal components, makes it easy to design, and provides stable operation with almost any combination ofoutput capacitors. The regulator operates with fixed switching frequency in continuous conduction mode (CCM)and discontinuous conduction mode (DCM). At very light load, the LM76002/LM76003 operates in PFM tomaintain high efficiency, and the switching frequency decreases with reduced load current.

7.3.2 Light Load Operation Modes — PFM and FPWMDCM operation is employed in the LM76002/LM76003 when the inductor current valley reaches zero. TheLM76002/LM76003 is in DCM when load current is less than half of the peak-to-peak inductor current ripple inCCM. In DCM, the LS switch is turned off when the inductor current reaches zero. Switching loss is reduced byturning off the LS FET at zero current, and the conduction loss is lowered by not allowing negative currentconduction. Power conversion efficiency is higher in DCM than CCM under the same conditions.

In DCM, the HS switch on-time reduces with lower load current. When either the minimum HS switch on-time(tON-MIN) or the minimum peak inductor current (IPEAK-MIN) is reached, the switching frequency decreases tomaintain regulation. At this point, the LM76002/LM76003 operates in PFM. In PFM, switching frequency isdecreased by the control loop when load current reduces to maintain output voltage regulation. Switching loss isfurther reduced in PFM operation due to less frequent switching actions.



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ON_MAXOUT _MAX IN_MIN OUT DS_ ON_HS

ON_MAX OFF _MIN

tV V I R DCR

t t u u

FBFBB FBT

OUT FB

VR R

V V

VOUT

FB

RFBT

RFBB

14




Feature Description (continued)In PFM operation, a small positive DC offset is required at the output voltage to activate the PFM detector. Thelower the frequency is in PFM, the more DC offset is needed at VOUT. See Typical Characteristics for typical DCoffset at very light load. If the DC offset on VOUT is not acceptable for a given application, TI recommends a staticload at output to reduce or eliminate the offset. Lowering values of the feedback divider RFBT and RFBB can alsoserve as a static load. In conditions with low VIN and/or high frequency, the LM76002/LM76003 may not enterPFM mode if the output voltage cannot be charged up to provide the trigger to activate the PFM detector. Oncethe LM76002/LM76003 is operating in PFM mode at higher VIN, it remains in PFM operation when VIN isreduced.

Alternatively, the device can run in a forced pulse-width-modulation (FPWM) mode where the switchingfrequency does not lower with load, and no offset is added to affect the VOUT accuracy unless the minimum on-time of the converter is reached.

7.3.3 Adjustable Output VoltageThe voltage regulation loop in the LM76002/LM76003 regulates the FB voltage to be the same as the internalreference voltage. The output voltage of the LM76002/LM76003 is set by a resistor divider to program the ratiofrom VOUT to VFB. The resistor divider is connected from the output node to ground with the mid-point connectingto the FB pin.

Figure 11. Output Voltage Setting

The voltage reference system produces a precise ±1% voltage reference over temperature. TI recommendsusing divider resistors with 1% tolerance or better with temperature coefficient of 100 ppm or lower. Selection ofRFBT equal or lower than 100 kΩ is also recommended. RFBB can be calculated by Equation 1:

(1)

Larger RFBT and RFBB values reduce the current that goes through the divider, thus helping to increase light loadefficiency. However, larger values also make the feedback path more susceptible to noise. If efficiency at verylight load is not critical in a certain application, TI recommends RFBT = 10 kΩ to 100 kΩ. If the resistor divider isnot connected properly, output voltage cannot be regulated because the feedback loop is broken. If the FB pin isshorted to ground or disconnected, the output voltage is driven close to VIN because the regulator detects verylow voltage on the FB node. The load connected to VOUT could be damaged in this case. It is important to routethe feedback trace away from the noisy area of the PCB. For more layout recommendations, see Layout.

The minimum output voltage achievable equals VFB, with RFBB open. The maximum VOUT is limited by themaximum duty cycle at a given frequency:

DMAX = 1 – (tOFF_MIN / TSW)

where• tOFF_MIN is the minimum off time of the HS switch• TSW = 1 / fSW is the switching period (2)

Ideally, without frequency foldback, VOUT_MAX = VIN_MIN × DMAX

Maximum output voltage with frequency foldback can be estimated using Equation 3:

(3)



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EN_ VOUT _H ENTENB

IN_ ON_H EN_VOUT_H

V RR

V V

u

VIN

ENABLE

RENT

RENB

15




Feature Description (continued)7.3.4 Enable (EN Pin) and UVLOSystem UVLO by EN and VCC_UVLO voltage on the EN pin (VEN) controls the ON/OFF functionality of theLM76002/LM76003. Applying a voltage less than 0.3 V to the EN input shuts down the operation of theLM76002/LM76003. In shutdown mode the quiescent current drops to typically 1.2 µA at VIN = 24 V.

The internal LDO output voltage VCC is turned on when VEN_VOUT_H is higher than 1.15 V. TheLM76002/LM76003 switching action and output regulation are enabled when VEN is greater than 1.204 V(typical). The LM76002/LM76003 supplies regulated output voltage when enabled and output current up to 2.5A/3.5 A. The EN pin is an input and cannot be open circuit or floating. The simplest way to enable the operationof the LM76002/LM76003 is to connect the EN pin to PVIN pins directly. This allows self-start-up of theLM76002/LM76003 when VIN is within the operation range.

Many applications may benefit from the employment of an enable divider RENT and RENB (see Figure 12) toestablish a precision system UVLO level for the stage. System UVLO can be used for supplies operating fromutility power as well as battery power. It can be used for sequencing, ensuring reliable operation, or supplyprotection, such as a battery. An external logic signal can also be used to drive EN input for system sequencingand protection.

Figure 12. VIN UVLO

With a selected RENT, the RENB can be calculated by:

where• VIN_ON_H is the desired supply voltage threshold to turn on this device• VEN_VOUT_H could be taken from device data sheet (4)

Note that the divider adds to supply quiescent current by VIN / (RENT + RENB). Small RENT and RENB values addmore quiescent current loss. However, large divider values make the node more sensitive to noise. RENT in thehundreds of kΩ range is a good starting point.

7.3.5 Internal LDO, VCC UVLO, and Bias InputThe LM76002/LM76003 has an internal LDO generating VCC voltage for control circuitry and MOSFET drivers.The nominal voltage for VCC is 3.29 V. The VCC pin must have a 1-µF to 4.7-µF bypass capacitor placed asclose as possible to the pin and properly grounded. Do not load or short the VCC pin to ground during operation.Shorting the VCC pin to ground during operation may damage the device.

An UVLO prevents the LM76002/LM76003 from operating until the VCC voltage exceeds VCC_UVLO. The VCC_UVLOthreshold is 3.14 V and has approximately 575 mV of hysteresis, so the device operates until VCC drops below2.575 V (typical). Hysteresis prevents the device from turning off during power up if VIN droops due to inputcurrent demands.



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Load Current (A)

VC

C (

V)

0.001 0.01 0.1 1 552.5

2.6

2.7

2.8

2.9

3

3.1

3.2

3.3

3.4

3.5

D010

Auto ModeFPWM Mode

16




Feature Description (continued)The LDO can generate VCC from two inputs: the supply voltage VIN and the BIAS input. The LDO power loss iscalculated by ILDO × (VINLDO – VOUTLDO). The higher the difference between the input and output voltages of theLDO, the more losses occur to supply the same LDO output current. The BIAS input is designed to reduce thedifference of the input and output voltages of the LDO to improve efficiency, especially at light load. TIrecommends tying the BIAS pin to VOUT when the output voltage is equal to or greater than 3.3 V. Tie the BIASpin to ground for applications less than 3.3 V. BIAS can also tie to external voltage source if available to improveefficiency. When used, TI recommends a 1-µF to 10-µF high-quality ceramic capacitor be used to bypass theBIAS pin to ground. If there is high-frequency noise or voltage spikes present on VOUT (during transient events orfault conditions), TI recommends connecting a resistor (1 to 10 Ω) between VOUT and BIAS.

The VCC voltage is typically 3.27 V. When the LM76302/3 is operating in PFM mode with frequency foldback, VCCvoltage is reduced to 3.1 V (typical) to further decrease the quiescent current and improve efficiency at very lightloads. Figure 13 shows an example of VCC voltage change with mode change.

Figure 13. VCC Voltage Change With Mode Change

VCC voltage has an internal undervoltage lockout threshold, VCC_UVLO. When VCC voltage is higher than VCC_UVLOrising threshold, the device is active and in normal operation if VEN > VEN_VOUT_H. If VCC voltage droops belowVCC_UVLO falling threshold, the VOUT is shut down.

7.3.6 Soft Start and Voltage Tracking (SS/TRK)The LM76002/LM76003 has a flexible and easy-to-use start-up rate control pin: SS/TRK. The soft-start feature isto prevent inrush current impacting the LM76002/LM76003, and its supply when power is first applied. Soft startis achieved by slowly ramping up the target regulation voltage when the device is first enabled or powered up.The simplest way to use the device is to leave the SS/TRK pin open circuit or floating. The LM76002/LM76003employs the internal soft-start control ramp and starts up to the regulated output voltage in 6.3 ms typically. Inapplications with a large amount of output capacitors, higher VOUT, or other special requirements, the soft-starttime can be extended by connecting an external capacitor CSS from SS/TRK pin to AGND. Extended soft-starttime further reduces the supply current required to charge up output capacitors and supply any output loading.An internal current source (ISSC = 2.2 μA) charges CSS and generates a ramp from 0 V to VFB to control theramp-up rate of the output voltage. For a desired soft-start time tSS, the capacitance for CSS can be found byEquation 5:



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Enable

Internal SS Ramp

Ext Tracking Signal to SS pin

VOUT

SS/TRK

RTRT

RTRB

EXT RAMP

17




Feature Description (continued)CSS = ISSC × tSS

where• CSS = soft-start capacitor value (µF)• ISSC = soft-start charging current (µA)• tSS = desired soft-start time (s) (5)

The soft-start capacitor CSS is discharged by an internal FET when VOUT is shut down by hiccup protection orENABLE = logic low. When a large CSS is applied, and EN is toggled low only for a short period of time, CSS maynot be fully discharged. The next soft-start ramp follows internal soft-start ramp before reaching the leftovervoltage on CSS and then follows the ramp programmed by CSS. If this is not acceptable for a certain application,an R-C low-pass filter can be added to EN to slow down the shutting down of VCC, allowing more time todischarge CSS.

The LM76002/LM76003 is capable of start-up into pre-biased output conditions. When the inductor currentreaches zero, the LS switch is turned off to avoid negative current conduction. This operation mode is also calleddiode emulation mode. It is built in by the DCM operation in light loads. With a pre-biased output voltage, theLM76002/LM76003 waits until the soft-start ramp allows regulation above the pre-biased voltage and then followsthe soft-start ramp to the regulation level. When an external voltage ramp is applied to the SS/TRK pin, theLM76002/LM76003 FB voltage follows the ramp if the ramp magnitude is lower than the internal soft-start ramp.A resistor divider pair can be used on the external control ramp to the SS/TRK pin to program the tracking rate ofthe output voltage. The final voltage detected by the SS/TRK pin must not fall below 1.2 V to avoid abnormaloperation

VOUT tracked to an external voltage ramp has the option of ramping up slower or faster than the internal voltageramp. VFB always follows the lower potential of the internal voltage ramp and the voltage on the SS/TRK pin.Figure 14 shows resistive divider connection if external ramp tracking is desired.

Figure 14. Soft-Start Tracking External Ramp

Figure 15 shows the case when VOUT ramps more slowly than the internal ramp, while Figure 16 shows whenVOUT ramps faster than the internal ramp. Faster start-up time may result in inductor current tripping currentprotection during start-up. Use with special care.

Figure 15. Tracking With Longer Start-up Time Than The Internal Ramp



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Frequency (kHz)

RT

(k:

)

0 500 1000 1500 2000 25000

20

40

60

80

100

120

140

D008

T38400

R (k ) = Frequency(kHz) 14.33

:

Enable

Internal SS Ramp

Ext Tracking Signal to SS pin

VOUT

18




Feature Description (continued)

Figure 16. Tracking With Shorter Start-up Time Than The Internal Ramp

The LM76002/LM76003 is capable of start-up into pre-biased output conditions. During start-up the device setsthe minimum inductor current to zero to avoid discharging a pre-biased load.

7.3.7 Adjustable Switching Frequency (RT) and Frequency SynchronizationThe switching frequency of the LM76002/LM76003 can be programmed by the impedance RT from the RT pin toground. The frequency is inversely proportional to the RT resistance. The RT pin can be left floating, and theLM76002/LM76003 operates at 500-kHz default switching frequency. The RT pin is not designed to be shorted toground.

For an desired frequency, RT can be found by:

(6)

Figure 17. Switching Frequency vs RT

Table 1. Switching Frequency vs RTSWITCHING FREQUENCY (kHz) RT RESISTANCE (kΩ)

300 134.42400 99.57500 79.07750 52.201000 38.961500 25.852000 19.342200 17.57



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SYNC

RTERM

EXT CLOCK

19




The LM76002/LM76003 switching action can also be synchronized to an external clock from 300 kHz to 2.2 MHz.TI recommends connecting an external clock to the SYNC pin with appropriate termination resistor. Ground theSYNC pin if not used.

Figure 18. Frequency Synchronization

The recommendations for the external clock include high level no lower than 2 V, low level no higher than 0.4 V,duty cycle between 10% and 90%, and both positive and negative pulse width no shorter than 80 ns. When theexternal clock fails at logic high or low, the LM76002/LM76003 switches at the frequency programmed by the RTresistor after a time-out period. TI recommends connecting a resistor RT to the RT pin so that the internaloscillator frequency is the same as the target clock frequency when the LM76002/LM76003 is synchronized to anexternal clock. This allows the regulator to continue operating at approximately the same switching frequency ifthe external clock fails.

The choice of switching frequency is usually a compromise between conversion efficiency and the size of thecircuit. Lower switching frequency implies reduced switching losses (including gate charge losses, switchtransition losses, etc.) and usually results in higher overall efficiency. However, higher switching frequency allowsuse of smaller LC output filters and hence a more compact design. Lower inductance also helps transientresponse (higher large signal slew rate of inductor current), and reduces the DCR loss. The optimal switchingfrequency is usually a trade-off in a given application and thus needs to be determined on a case-by-case basis.It is related to the input voltage, output voltage, most frequent load current level(s), external component choices,and circuit size requirement. The choice of switching frequency may also be limited if an operating conditiontriggers tON-MIN or tOFF-MIN.

7.3.8 Minimum On-Time, Minimum Off-Time, and Frequency Foldback at Dropout ConditionsMinimum on-time, tON-MIN, is the smallest duration of time that the HS switch can be on. tON-MIN is typically 70 nsin the LM76002/LM76003. Minimum off-time, tOFF-MIN, is the smallest duration that the HS switch can be off. tOFF-MIN is typically 100 ns in the LM76002/LM76003. In CCM operation, tON-MIN and tOFF-MIN limits the voltageconversion range given a selected switching frequency. The minimum duty cycle allowed is:

DMIN = tON-MIN × fSW (7)

And the maximum duty cycle allowed is:DMAX = 1 – tOFF-MIN × fSW (8)

Given fixed tON-MIN and tOFF-MIN, the higher the switching frequency the narrower the range of the allowed dutycycle. In the LM76002/LM76003, frequency foldback scheme is employed to extend the maximum duty cyclewhen tOFF-MIN is reached. The switching frequency decreases once longer duty cycle is needed under low VINconditions. The switching frequency can be decreased to approximately 1/10 of the programmed frequency byRT or the synchronization clock. Such a wide range of frequency foldback allows the LM76002/LM76003 outputvoltage to stay in regulation with a much lower supply voltage VIN. This leads to a lower effective dropout voltage.See Typical Characteristics for more details.

Given an output voltage, the choice of the switching frequency affects the allowed input voltage range, solutionsize and efficiency. The maximum operational supply voltage can be found by:

VIN_MAX = VOUT / (fSW × tON-MIN) (9)

At lower supply voltage, the switching frequency decreases once tOFF-MIN is tripped. The minimum VIN withoutfrequency foldback can be approximated by:

VIN_MIN = VOUT / (fSW × tOFF-MIN) (10)

Considering power losses in the system with heavy load operation, VIN-MIN is higher than the result calculated inEquation 10. With frequency foldback, VIN-MIN is lowered by decreased fSW. When the device is operating in automode at voltages near maximum rated input voltage and light load conditions, an increased output voltage rippleduring load transient may be observed. For this reason TI recommends that device operating point be calculatedwith sufficient operational margin so that minimum on-time condition is not triggered.



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FB

RFBT

RFBB

CFF

VOUT

20




7.3.9 Internal Compensation and CFF

The LM76002/LM76003 is internally compensated with RC = 600 kΩ and CC = 35 pF as shown in the FunctionalBlock Diagram. The internal compensation is designed such that the loop response is stable over the entireoperating frequency and output voltage range. Depending on the output voltage, the compensation loop phasemargin can be low with all ceramic capacitors. TI recommends placing an external feed-forward cap CFF inparallel with the top resistor divider RFBT for optimum transient performance.

Figure 19. Feed-Forward Capacitor for Loop Compensation

The feed-forward capacitor CFF in parallel with RFBT places an additional zero before the crossover frequency ofthe control loop to boost phase margin. The zero frequency can be found by Equation 11:

fZ-CFF = 1 / (2π × RFBT × CFF) (11)

An additional pole is also introduced with CFF at the frequency of Equation 12:fP-CFF = 1 / (2π × CFF × (RFBT // RFBB)) (12)

Select the CFF so that the bandwidth of the control loop without the CFF is centered between fZ-CFF and fP-CFF. Thezero fZ-CFF adds phase boost at the crossover frequency and improves transient response. The pole fP-CFF helpsmaintaining proper gain margin at frequency beyond the crossover.

Electrolytic capacitors have much larger ESR and the ESR zero frequency would be low enough to boost thephase up around the crossover frequency.

fZ-ESR = 1 / (2π × ESR × COUT) (13)

Designs using mostly electrolytic capacitors at the output may not need any CFF. The CFF creates a time constantwith RFBT that couples in the attenuated output voltage ripple to the FB node. If the CFF value is too large, it cancouple too much ripple to the FB and affect VOUT regulation. It could also couple too much transient voltagedeviation and falsely trip PGOOD thresholds. Therefore, calculate CFF based on output capacitors used in thesystem. At cold temperatures, the value of CFF might change based on the tolerance of the chosen component.This may reduce its impedance and ease noise coupling on the FB node. To avoid this, more capacitance can beadded to the output or the value of CFF can be reduced. See Feed-Forward Capacitor for the calculation of CFF.

7.3.10 Bootstrap Voltage and VBOOT UVLO (BOOT PIN)The driver of the power switch (HS switch) requires bias higher than VIN when the HS switch is ON. Thecapacitor connected between CBOOT and SW works as a charge pump to boost voltage on the BOOT pin to (VSW+ VCC). The boot diode is integrated on the LM76002/LM76003 die to minimize physical size. TI recommends a0.47-µF, 6.3-V or higher capacitor for CBOOT. The VBOOT_UVLO threshold is typically 2.2 V. If the CBOOT capacitor isnot charged above this voltage with respect to SW, the device initiates a charging sequence using the low-sideFET.

7.3.11 Power-Good and Overvoltage Protection (PGOOD)The LM76002/LM76003 has a built-in power-good flag shown on PGOOD pin to indicate whether the outputvoltage is within its regulation level. The PGOOD signal can be used for start-up sequencing of multiple rails. ThePGOOD pin is an open-drain output that requires a pullup resistor to an appropriate logic voltage (any voltagebelow 12 V). The pin can sink 5 mA of current and maintain its specified logic low level. A typical range of pullupresistor value is 10 kΩ to 100 kΩ. When the FB voltage is within the power-good band, +6% above and –7%below the internal reference VREF typically, the PGOOD switch is turned off, and the PGOOD pin voltage is pulledto ground. When the FB is 2% (typical) closer to FB than the PGOOD threshold, the PGOOD switch is turned off,and the pin is pulled up to the voltage connected to the pullup resistor. Both rising and falling edges of thepower-good flag have a built-in 220-µs (typical) deglitch delay. To pull up PGOOD pin to a voltage higher than15 V, a resistor divider can be used to divide the voltage down.



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PGPGB PGT

PU PG

VR = R

V V

VPU

RPGT

RPGB

PGOOD

21




Figure 20. PGOOD Resistor Divider

For given pullup voltage VPU and desired voltage on PGOOD pin is VPG and with RPGT chosen, value for RPGBcan be calculated using Equation 14:

(14)

7.3.12 Overcurrent and Short-Circuit ProtectionThe LM76002/LM76003 is protected from overcurrent conditions by cycle-by-cycle current limiting on both peakand valley of the inductor current. Hiccup mode is activated if a fault condition persists to prevent overheating.

High-side MOSFET overcurrent protection is implemented by the nature of the peak current-mode control. TheHS switch current is sensed when the HS is turned on after a blanking time. The HS switch current is comparedto the either the minimum of a fixed current set point (ISC) or the output of the voltage regulation loop minus slopecompensation every switching cycle. The slope compensation increases with duty cycle and tends to lower theHS current limit above 60% duty cycle as it lowers below ISC. See Typical Characteristics.

When the LS switch is turned on, the current going through it is also sensed and monitored. Before turning offthe LS switch at the end of every clock cycle, the LS current is compared to the LS current limit. If the LS currentlimit is exceeded, the LS MOSFET stays on, and the HS switch is not turned on. The LS switch is kept ON sothat inductor current keeps ramping down, until the inductor current ramps below ILSLIMIT. The LS switch is turnedoff once the LS current falls below the limit, and the HS switch is turned on again after a dead time.

If the current of the LS switch is higher than the LS current limit for 128 consecutive cycles, and the feedbackvoltage falls 60% below regulation, hiccup current-protection mode is activated. In hiccup mode, the regulator isshut down and kept off for 40 ms typically before the LM76002/LM76003 tries to start again. If overcurrent or ashort-circuit fault condition still exists, hiccup repeats until the fault condition is removed. Hiccup mode reducespower dissipation under severe overcurrent conditions, and prevents overheating and potential damage to thedevice. Under non-severe overcurrent conditions when the feedback voltage has not fallen 60% below regulation,the LM76002/LM76003 reduces the switching frequency and keeps the inductor current valley clamped at the LScurrent limit level. This operation mode allows slight overcurrent operation during load transients without trippinghiccup.

If tracking was used for initial sequencing the device attempts to restart using the internal soft-start circuit untilthe tracking voltage is reached.

7.3.13 Thermal ShutdownThermal shutdown limits total power dissipation by turning off the internal switches when the device junctiontemperature exceeds 160°C (typical). After thermal shutdown occurs, hysteresis prevents the device fromswitching until the junction temperature drops to approximately 135°C. When the junction temperature falls below135°C, the LM76002/LM76003 attempts to soft start.



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22




7.4 Device Functional Modes

7.4.1 Shutdown ModeThe EN pin provides electrical on/off control for the LM76002/LM76003. When the EN pin voltage is below 0.3 V(typical), both the regulator and the internal LDO have no output voltages, and the device is in shutdown mode.In shutdown mode the quiescent current drops to typically 1.2 µA. The LM76002/LM76003 also employs UVLOprotection. If VCC voltage is below the UVLO level, the output of the regulator is turned off.

7.4.2 Standby ModeThe internal LDO has a lower EN threshold than the regulator. When the EN pin voltage is above below 1.1 V(maximum) and below the precision enable threshold for the output voltage, the internal LDO regulates the VCCvoltage at 3.29 V typically. The precision enable circuitry is ON once VCC is above the UVLO. The internalMOSFETs remain in tri-state unless the voltage on EN pin goes above the precision enable threshold. TheLM76002/LM76003 also employs UVLO protection. If VCC voltage is below the UVLO level, the output of theregulator is turned off.

7.4.3 Active ModeThe LM76002/LM76003 is in active mode when the EN pin and UVLO high threshold levels are satisfied. Thesimplest way to enable the operation of the LM76002/LM76003 is to connect the EN pin to VIN, which allows selfstart-up of the LM76002/LM76003 when the input voltage is in the operation range: 3.5 V to 60 V. See Enable(EN Pin) and UVLO for details on setting these operating levels.

In active mode, depending on the load current, the LM76002/LM76003 will be in one of five sub modes:1. CCM with fixed switching frequency with load between half of IMINPK to full load.2. DCM when the load current is lower than half of the inductor current ripple.3. Light load mode where the device uses pulse frequency modulation (PFM) and lowers the switching

frequency at load under half of IMINPK to improve efficiency.4. Foldback mode when switching frequency is reduced to maintain output regulation with supply voltages that

cause the minimum tON or tOFF to be exceeded.5. Forced-pulse-width modulation (FPWM) is similar to CCM with fixed switching frequency, but extends the

fixed frequency range of operation from full to no load.

7.4.4 CCM ModeCCM operation is employed in the LM76002/LM76003 when the load current is higher than ½ of the peak-to-peak inductor current. If the load current is decreased, the device enters DCM mode. In CCM operation, thefrequency of operation is constant and fixed unless the minimum tON or tOFF are exceeded which causes the partto enter fold back mode (refer to Internal LDO, VCC UVLO, and Bias Input for details). In these cases, PWM isstill maintained, but the frequency of operation is folded back (reduced) to maintain proper regulation.

7.4.5 DCM ModeDCM operation is employed in the LM76002/LM76003 when the load current is lower than ½ of the peak-to-peakinductor current. In DCM operation (also known as diode emulation mode), the LS FET is turned off when theinductor current drops below 0 A to keep operation as efficient as possible by reducing switching losses andpreventing negative current conduction. In PWM operation, the frequency of operation is constant and fixedunless the load current is reduced below IPEAK_MIN, which causes the part to enter light load mode, or if theminimum tON or tOFF are exceeded, which cause the device to enter foldback mode.

7.4.6 Light Load ModeAt light output current loads, PFM is activated for the highest efficiency possible. When the inductor current doesnot reach IPEAK_MIN during a switching cycle, the on-time is increased, and the switching frequency reduces asneeded to maintain proper regulation. The on-time has a maximum value of 8 µs to avoid large output voltageripple in dropout conditions. Efficiency is greatly improved by reducing switching and gate-drive losses. Duringlight-load mode of operation the LM76002/LM76003 operates with a minimum quiescent current of 10 to 15 µA(typical).



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23




Device Functional Modes (continued)7.4.7 Foldback ModeFoldback protection modes are entered when the duty cycle exceeds the minimum on- and off-times of thedevice. At very high duty cycles, where the minimum off-time is not satisfied, the frequency folds back to allowmore time for the peak current command to be reached. The maximum on-time is 8 µs, which limits themaximum duty cycle in dropout to 98%. At very low duty cycles when the minimum on-time is reached, thedevice maintains regulation by dropping the frequency to allow more time for the inductor current to dischargethe output capacitor. Foldback mode is exited once the minimum on-time and off-times are satisfied.

7.4.8 Forced Pulse-Width-Modulation ModeFPWM is employed when the FPWM pin is pulled high, or the device is synchronized to an external clock. In thismode, diode emulation is turned off, and the device emains in CCM over the full load range. In FPWM operation,the frequency of operation is constant and fixed unless the minimum tON or tOFF are exceeded, which cause thedevice to enter foldback mode. In these cases, PWM operation is still maintained, but the frequency of operationis folded back (reduced) to maintain proper regulation. DC accuracy is at a minimum in FPWM mode.

7.4.9 Self-Bias ModeFor highest efficiency of operation, TI recommends that the BIAS pin be connected directly to VOUT when 3.3 V ≤VOUT ≤ 24 V. In this self-bias mode of operation, the difference between the input and output voltages of theinternal LDO are reduced, and therefore the total efficiency of the LM76002/LM76003 is improved. Theseefficiency gains are more evident during light load operation. During this mode of operation, theLM76002/LM76003 operates with a minimum quiescent current of 15 µA (typical). See Internal LDO, VCC UVLO,and Bias Input for more details.



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SWPVIN

PGNDBOOT

VCC

BIAS

SYNC

RT

PGOOD

EN

SS/TRK

AGND

FB

LM76003

COUTCBOOT

CIN

CVCC

CBIAS

RFBT

RFBB

CFF

L

Tie BIAS to PGND when VOUT < 3.3 V

VIN VOUT


24




8 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

8.1 Application InformationThe LM76002/LM76003 is a step-down DC-DC converter. It is typically used to convert a higher DC voltage to alower DC voltage with a maximum output current of 3.5 A. The following design procedure can be used to selectcomponent values for the LM76002/LM76003. Alternately, the WEBENCH® software may be used to generate acomplete design. The WEBENCH software uses an iterative design procedure and accesses a comprehensivedatabase of components when generating a design (see Custom Design With WEBENCH® Tools).

8.2 Typical ApplicationsThe LM76002/LM76003 only requires a few external components to convert from a wide range of supply voltageto output voltage, as shown in Figure 21:

Figure 21. LM76002/LM76003 Basic Schematic

The LM76002/LM76003 also integrates a full list of features to aid system design requirements, such as VCCUVLO, programmable soft start, start-up tracking, programmable switching frequency, clock synchronization, anda power-good indication. Each system can select the features needed in a specific application. A comprehensiveschematic with all features utilized is shown in Figure 22:



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SWPVIN

PGND

BOOT

VCC

BIAS

SYNC

RT

PGOOD

EN

SS/TRK

AGND

FB

LM76003

COUTCBOOT

CIN

CVCC

CBIAS

RFBT

RFBB

CFF

L

CSS

RT

RSYNC

Tie BIAS to PGND when VOUT < 3.3 V

VIN VOUT

RENT

RENB

RPG

PGND


25




Typical Applications (continued)

Figure 22. LM76002/LM76003 Comprehensive Schematic

The external components must fulfill the requirements of the application, but also the stability criteria of thedevice control loop. The LM76002/LM76003 is optimized to work within a range of external components.Inductance and capacitance of the LC output filter each create poles that have to be considered in the control ofthe converter. Table 2 can be used to simplify the output filter component selection.

Table 2. L, COUT, and CFF Typical ValuesfSW (kHz) VOUT (V) L (µH) COUT (µF) RFBT (kΩ) RFBB (kΩ)

300 1 2.5 680 100 OPEN500 1 1.5 470 100 OPEN1000 1 0.68 200 100 OPEN2200 1 0.47 120 100 OPEN300 3.3 6.8 200 100 43.5500 3.3 4.7 150 100 43.51000 3.3 2.5 88 100 43.52200 3.3 1.2 44 100 43.5300 5 10 150 100 25500 5 6.8 100 100 251000 5 3.3 66 100 252200 5 1.5 44 100 25300 12 22 66 100 9.09500 12 15 44 100 9.091000 12 6.8 22 100 9.092200 12 3.3 22 100 9.09300 24 47 40 100 4.37500 24 27 33 100 4.371000 24 15 22 100 4.372200 24 6.8 22 100 4.37



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T38400

R (k ) = Frequency(kHz) 14.33

:

FBFBB FBT

OUT FB

VR R

V V

26




8.2.1 Design RequirementsDetailed Design Procedure is based on a design example. For this design example, use the parameters listed inTable 3 as the input parameters.

Table 3. Design Example ParametersDESIGN PARAMETER VALUE

Input voltage range 3.5 V to 60 VOutput voltage 3.3 V

Input ripple voltage 400 mVOutput ripple voltage 30 mVOutput current rating 3.5 AOperating frequency 500 kHz

8.2.2 Detailed Design Procedure

8.2.2.1 Custom Design With WEBENCH® ToolsClick here to create a custom design using the LM76002/03 device with the WEBENCH® Power Designer.1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-timepricing and component availability.

In most cases, these actions are available:• Run electrical simulations to see important waveforms and circuit performance• Run thermal simulations to understand board thermal performance• Export customized schematic and layout into popular CAD formats• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

8.2.2.2 Output Voltage SetpointThe output voltage of the LM76002/LM76003 device is externally adjustable using a resistor divider network. Inthe application circuit of Figure 22, this divider network is comprised of top feedback resistor RFBT and bottomfeedback resistor RFBB. Equation 15 is used to determine the output voltage of the converter:

(15)

Choose the value of the RFBT to be around 1 MΩ to minimize quiescent current during light load operation or100 kΩ to improve noise immunity. With the desired output voltage set to be 3.3 V and with a VFB = 1 V, the RFBBvalue can then be calculated using Equation 15. The formula yields a value of 434.78 kΩ. Choose the closestavailable value of 432 kΩ for the RFBB, or a combination of two resistors (432 kΩ + 2.74 kΩ) to increase initialaccuracy.

8.2.2.3 Switching FrequencyThe default switching frequency of the LM76002/LM76003 device is set at 500 kHz. If the RT is left open, theLM76002/LM76003 switches at 500 kHz in CCM mode. Use Equation 16 to calculate the required value for RT inorder to operate the LM76002/LM76003 at different frequencies.

(16)

The unit for the result is kΩ.



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https://webench.ti.com/wb5/WBTablet/PartDesigner/quickview.jsp?base_pn=LM76003&origin=ODS&litsection=application

http://www.ti.com/lsds/ti/analog/webench/overview.page?DCMP=sva_web_webdesigncntr_en&HQS=sva-web-webdesigncntr-vanity-lp-en

L

OUT

ir

I

'

IN OUT IN OUT

SW L-MAX SW L-MAX

(V V ) D (V V ) DL

0.4 f I 0.2 f I u u

d du u u u

IN OUTL

SW

(V V ) Di

L f u

' u

27




8.2.2.4 Input CapacitorsThe LM76002/LM76003 device requires an input decoupling and, depending on the application, a bulk inputcapacitor. The typical recommended value for the high frequency decoupling capacitor is 10 μF to 22 μF. TIrecommends a high-quality ceramic type X5R or X7R with sufficiency voltage rating. The voltage rating must begreater than the maximum input voltage. To compensate the derating of ceramic capacitors, a voltage rating oftwice the maximum input voltage is recommended. Additionally, some bulk capacitance can be required,especially if the LM76002/LM76003 circuit is not located within approximately 5 cm from the input voltage source.This capacitor is used to provide damping to the voltage spiking due to the lead inductance of the cable. Theoptimum value for this capacitor is four times the ceramic input capacitance with ESR close to the characteristicimpedance of the LC filter formed by the application input inductance and ceramic input capacitors.

For this design, two 4.7-μF, X7R dielectric capacitors rated for 100 V are used for the input decouplingcapacitance. A single capacitor has equivalent series resistance (ESR) of approximately 3 mΩ, and an RMScurrent rating of 3 A. Include a capacitor with a value of 47 nF for high-frequency filtering and place it as close aspossible to the device pins.

NOTEDC-Bias Effect: High capacitance ceramic capacitors have a DC-bias derating effect,which has a strong influence on the final effective capacitance. Therefore, choose the rightcapacitor value carefully. Package size and voltage rating in combination with dielectricmaterial are responsible for differences between the rated capacitor value and theeffective capacitance.

8.2.2.5 Inductor SelectionThe first criterion for selecting an output inductor is the inductance itself. In most buck converters, this value isbased on the desired peak-to-peak ripple current, ΔiL that flows in the inductor along with the load current. Aswith switching frequency, the selection of the inductor is a tradeoff between size and cost. Higher inductancemeans lower ripple current and hence lower output voltage ripple. Lower inductance results in smaller, lessexpensive devices. An inductance that gives a ripple current of 20% to 40% of the maximum output current is agood starting point. (ΔiL = (1/5 to 2/5) × IOUT). The peak-to-peak inductor current ripple can be found byEquation 17 and the range of inductance can be found by Equation 18 with the typical input voltage used as VIN.

(17)

(18)

D is the duty cycle of the converter which in a buck converter it can be approximated as D = VOUT / VIN,assuming no loss power conversion. By calculating in terms of amperes, volts, and megahertz, the inductancevalue comes out in micro henries. The inductor ripple current ratio is defined by:

(19)

The second criterion is the inductor saturation-current rating. The inductor must be rated to handle the maximumload current plus the ripple current:

IL-PEAK = ILOAD-MAX + Δ iL / 2 (20)

The LM76002/LM76003 has both valley current limit and peak current limit. During an instantaneous short, thepeak inductor current can be high due to a momentary increase in duty cycle. The inductor current rating shouldbe higher than the HS current limit. TI recommends selection of an inductor with a larger core saturation marginand preferably a softer roll off of the inductance value over load current.



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SW OUT

D' 1ESR < + 0.5

f C r·§

u ¨ ¸u © ¹

2

OUTSW OUT OUT

1 rC (1 D ) D (1 r)

(f r V / I ) 12

ª º·§c c! u u u « »¸¨ ¸u u' « »© ¹¬ ¼

28




In general, it is preferable to choose lower inductance in switching power supplies, because it usuallycorresponds to faster transient response, smaller DCR, and reduced size for more compact designs. However,too low of an inductance can generate too large of an inductor current ripple such that overcurrent protection atthe full load could be falsely triggered. It also generates more conduction loss because the RMS current isslightly higher relative that with lower current ripple at the same DC current. Larger inductor current ripple alsoimplies larger output voltage ripple with the same output capacitors. With peak-current-mode control, it is notrecommended to have an inductor current ripple that is too small. Enough inductor current ripple improves signal-to-noise ratio on the current comparator and makes the control loop more immune to noise.

Once the inductance is determined, the type of inductor must be selected. Ferrite designs have very low corelosses and are preferred at high switching frequencies, so design goals can concentrate on copper loss andpreventing saturation. Ferrite core material saturates hard, which means that inductance collapses abruptly whenthe peak design current is exceeded. The hard saturation results in an abrupt increase in inductor ripple currentand consequent output voltage ripple. Do not allow the core to saturate.

For the design example, a standard 10-μH inductor from Wurth, Coiltronics, or Vishay can be used for the 3.3-Voutput with plenty of current rating margin.

8.2.2.6 Output Capacitor SelectionThe device is designed to be used with a wide variety of LC filters. TI generally recommends using as little outputcapacitance as possible to keep cost and size down. Choose the output capacitor(s), COUT, with care as itdirectly affects the steady-state output-voltage ripple, loop stability, and the voltage over/undershoot during loadcurrent transients.

The output voltage ripple is essentially composed of two parts. One is caused by the inductor current ripple goingthrough the equivalent series resistance (ESR) of the output capacitors:

ΔVOUT-ESR = ΔiL × ESR (21)

The other is caused by the inductor current ripple charging and discharging the output capacitors:ΔVOUT-C = ΔiL / (8 × fSW × COUT) (22)

The two components in the voltage ripple are not in phase, so the actual peak-to-peak ripple is smaller than thesum of the two peaks.

Output capacitance is usually limited by transient performance specifications if the system requires tight voltageregulation in the presence of large current steps and fast slew rates. When a fast large load transient happens,output capacitors provide the required charge before the inductor current can slew to the appropriate level. Theinitial output voltage step is equal to the load current step multiplied by the ESR. VOUT continues to droop untilthe control loop response increases or decreases the inductor current to supply the load. To maintain a smallovershoot or undershoot during a transient, small ESR, and large capacitance are desired. But these also comewith higher cost and size. Thus, the motivation is to seek a fast control loop response to reduce the outputvoltage deviation.

For a given input and output requirement, Equation 23 gives an approximation for an absolute minimum outputcap required:

(23)

Along with this for the same requirement, calculate the maximum ESR as per Equation 24

where• r = Ripple ratio of the inductor ripple current (ΔiL / IOUT)• ΔVO = target output voltage undershoot• D’ = 1 – duty cycle• fSW = switching frequency• IOUT = load current (24)



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uS u

FFx FBT FBT FBB

1 1C

2 f R (R / /R )

XOUT OUT

15.46f

V C

u

29




A general guideline for COUT range is that COUT should be larger than the minimum required output capacitancecalculated by Equation 23, and smaller than 10 times the minimum required output capacitance or 1 mF. Inapplications with VOUT less than 3.3 V, it is critical that low ESR output capacitors are selected. This limitspotential output voltage overshoots as the input voltage falls below the device normal operating range. Tooptimize the transient behavior a feed-forward capacitor could be added in parallel with the upper feedbackresistor. For this design example, three 47-µF, 10-V, X7R ceramic capacitors are used in parallel.

8.2.2.7 Feed-Forward CapacitorThe LM76002/LM76003 is internally compensated and the internal R-C values are 400 kΩ and 50 pF,respectively. Depending on the VOUT and frequency FS, if the output capacitor COUT is dominated by low ESR(ceramic types) capacitors, it could result in low phase margin. To improve the phase boost an external feed-forward capacitor CFF can be added in parallel with RFBT. CFF is chosen such that phase margin is boosted at thecrossover frequency without CFF. A simple estimation for the crossover frequency without CFF (fx) is shown inEquation 25, assuming COUT has very small ESR.

(25)

The Equation 26 for CFF was tested:

(26)

If capacitors with high ESR are used CFF is not required. The CFF capacitor creates a time constant with RFBT thatcouples the attenuated output voltage ripple to the FB node. Using a value that is too large for CFF may coupletoo much ripple to FB node and affect output voltage regulation. For capacitors with medium ESR (20 – 200 mΩ)Equation 26 can be used as quick starting point. For the application in this design example, a 47-pF COGcapacitor is used.

8.2.2.8 Bootstrap CapacitorsEvery LM76002/LM76003 design requires a bootstrap capacitor, CBOOT. The recommended bootstrap capacitoris 0.47 μF and rated at 6.3 V or greater. The bootstrap capacitor is located between the SW pin and the BOOTpin. The bootstrap capacitor must be a high-quality ceramic type with X7R or X5R grade dielectric fortemperature stability.

8.2.2.9 VCC CapacitorsThe VCC pin is the output of an internal LDO for LM76002/LM76003. The input for this LDO comes from eitherVIN or BIAS (please refer to functional block diagram for LM76002/LM76003). To insure stability of the part,place a 1-µF to 2.2-µF, 10-V capacitor for this pin. Never short VCC pin to ground during operation.

8.2.2.10 BIAS CapacitorsFor an output voltage 3.3 V and greater, connect the BIAS pin to the output in order to increase light loadefficiency. The BIAS pin is one of the two inputs for the VCC LDO. When BIAS voltage is below VBIAS-ONthreshold, the input for the VCC LDO is internally connected to VIN. Because this is an LDO, the voltagedifferences between the input and output affects the efficiency of the LDO. If necessary, a capacitor with a valueof 1 μF can be added close to the BIAS pin as an input capacitor for the LDO.

8.2.2.11 Soft-Start CapacitorsThe SS pin can be left floating, and the LM76002/LM76003 implements a soft-start time of 6.3 ms. In order touse an external soft-start capacitor, the capacitor must be sized so that the soft-start time is greater than 6.3 ms.Use Equation 27 to calculate the soft-start capacitor value:

CSS = ISSC × tSS (27)

With a desired soft start time of 11 ms, a soft-start charging current of 2 µA, and an internal VREF of 1 V,Equation 27 yields a soft start capacitor value of 22 nF.



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30




8.2.2.12 Undervoltage Lockout SetpointThe undervoltage lockout (UVLO) is adjusted using the external voltage divider network of RENT and RENB. RENTis connected between the PVIN pin and the EN pin of the LM76002/LM76003. RENB is connected between theEN pin and the GND pin. The UVLO has two thresholds, one for power up when the input voltage is rising andone for power down or brownouts when the input voltage is falling. Equation 28 can be used to determine theVIN UVLO level.

VIN-UVLO-RISING = VENH × (RENB + RENT) / RENB (28)

The EN rising threshold (VENH) for LM76002/LM76003 is set to be 1.218 V (typical). Choose the value of RENB tobe 1 MΩ to minimize input current from the supply. If the desired VIN UVLO level is at 5 V, then the value of RENTcan be calculated using Equation 29:

RENT = (VIN-UVLO-RISING / VENH – 1) × RENB (29)

Equation 29 yields a value of 1.38 MΩ. The resulting falling UVLO threshold, can be calculated by Equation 30,where EN falling threshold (VENL) is 0.99 V (typical).

VIN-UVLO-FALLING = VENL × (RENB + RENT) / RENB (30)

8.2.2.13 PGOODA typical pullup resistor value is 10 kΩ to 100 kΩ from the PGOOD pin to a voltage no higher than 18 V. If it isdesired to pull up the PGOOD pin to a voltage higher than 18 V, a resistor can be added from the PGOOD pin toground to divide the voltage detected by the PGOOD pin to a value no higher than 18 V.

8.2.2.14 SynchronizationThe LM76002/LM76003 switching action can synchronize to an external clock from 300 kHz to 2.2 MHz. TIrecommends connecting an external clock to the SYNC pin with a 50-Ω to 100-Ω termination resistor. Ground theSYNC pin if not used.



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Load Current (A)

Effi

cien

cy (

%)

0.001 0.01 0.1 1 550

10

20

30

40

50

60

70

80

90

100

D016


Load Current (A)

Effi

cien

cy (

%)

0 0.5 1 1.5 2 2.5 3 3.5 40

10

20

30

40

50

60

70

80

90

100

D016


Load Current (A)

Effi

cien

cy (

%)

0.001 0.01 0.1 1 550

10

20

30

40

50

60

70

80

90

100

D014


Load Current (A)

Effi

cien

cy (

%)

0 0.5 1 1.5 2 2.5 3 3.5 450

55

60

65

70

75

80

85

90

95

100

D014


Load Current (A)

Effi

cien

cy (

%)

0.001 0.01 0.1 1 550

10

20

30

40

50

60

70

80

90

100

D011

VIN = 8 VVIN = 12 VVIN = 18 VVIN = 24 V

Load Current (A)

Effi

cien

cy (

%)

0 0.5 1 1.5 2 2.5 3 3.5 450

55

60

65

70

75

80

85

90

95

100

D011


31




8.2.3 Application CurvesUnless otherwise specified the following conditions apply:

VOUT = 3.3 V fSW = 500 kHz Auto Mode

Figure 23. LM76003 Efficiency

VOUT = 3.3 V fSW = 500 kHz FPWM Mode


VOUT = 5 V fSW = 500 kHz Auto Mode


VOUT = 5 V fSW = 500 kHz FPWM Mode








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Load Current (A)

Effi

cien

cy (

%)

0.001 0.01 0.1 1 550

20

40

60

80

100

120

D022


Load Current (A)

Effi

cien

cy (

%)

0 0.5 1 1.5 2 2.5 3 3.5 40

20

40

60

80

100

120

D022


Load Current (A)

Effi

cien

cy (

%)

0.001 0.01 0.1 1 550

20

40

60

80

100

120

D020


Load Current (A)

Effi

cien

cy (

%)

0 0.5 1 1.5 2 2.5 3 3.5 40

20

40

60

80

100

120

D020


Load Current (A)

Effi

cien

cy (

%)

0.001 0.01 0.1 1 550

10

20

30

40

50

60

70

80

90

100

D018


Load Current (A)

Effi

cien

cy (

%)

0 0.5 1 1.5 2 2.5 3 3.5 40

10

20

30

40

50

60

70

80

90

100

D018


32




Unless otherwise specified the following conditions apply:















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Load Current (A)

Out

put V

olta

ge (

V)

0.001 0.01 0.1 1 554.8

4.84

4.88

4.92

4.96

5

5.04

5.08

5.12

5.16

5.2

D015


Load Current (A)

Out

put V

olta

ge (

V)

0 0.5 1 1.5 2 2.5 3 3.5 44.9

4.92

4.94

4.96

4.98

5

5.02

5.04

5.06

5.08

5.1

D015


Load Current (A)

Out

put V

olta

ge (

V)

0.01 0.1 1 553.2

3.22

3.24

3.26

3.28

3.3

3.32

3.34

3.36

3.38

3.4

D012


Load Current (A)

Out

put V

olta

ge (

V)

0 0.5 1 1.5 2 2.5 3 3.5 43.2

3.22

3.24

3.26

3.28

3.3

3.32

3.34

3.36

3.38

3.4

D012


Load Current (A)

Effi

cien

cy (

%)

0.001 0.01 0.1 1 550

10

20

30

40

50

60

70

80

90

100

D024


Load Current (A)

Effi

cien

cy (

%)

0 0.5 1 1.5 2 2.5 30

10

20

30

40

50

60

70

80

90

100

D024


33










Figure 37. LM76003 Load and Line Regulation

VOUT = 3.3 V fSW = 500 kHz FPWM Mode








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Load Current (A)

Out

put V

olta

ge (

V)

0.001 0.01 0.1 1 5511.8

11.85

11.9

11.95

12

12.05

12.1

12.15

12.2

12.25

12.3

12.35

12.4

D021


Load Current (A)

Out

put V

olta

ge (

V)

0 0.5 1 1.5 2 2.5 3 3.5 411.8

11.85

11.9

11.95

12

12.05

12.1

12.15

12.2

12.25

12.3

12.35

12.4

D021


Load Current (A)

Out

put V

olta

ge (

V)

0.001 0.01 0.1 1 554.8

4.84

4.88

4.92

4.96

5

5.04

5.08

5.12

5.16

5.2

D019


Load Current (A)

Out

put V

olta

ge (

V)

0 0.5 1 1.5 2 2.5 3 3.5 44.9

4.92

4.94

4.96

4.98

5

5.02

5.04

5.06

5.08

5.1

D019


Load Current (A)

Out

put V

olta

ge (

V)

0.001 0.01 0.1 1 554.8

4.84

4.88

4.92

4.96

5

5.04

5.08

5.12

5.16

5.2

D017


Load Current (A)

Out

put V

olta

ge (

V)

0 0.5 1 1.5 2 2.5 3 3.5 44.9

4.92

4.94

4.96

4.98

5

5.02

5.04

5.06

5.08

5.1

D017


34



















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Input Voltage (V)

Out

put V

olta

ge (

V)

3 3.5 4 4.5 5 5.5 6 6.52.5

2.6

2.7

2.8

2.9

3

3.1

3.2

3.3

3.4

3.5

D026

ILOAD = 10 mAILOAD = 1 AILOAD = 2.5 AILOAD = 3.5 A

Input Voltage (V)

Out

put V

olta

ge (

V)

4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.53.8

4

4.2

4.4

4.6

4.8

5

5.2

5.4

5.6

D027


Load Current (A)

Out

put V

olta

ge (

V)

0.001 0.01 0.1 1 554.8

4.84

4.88

4.92

4.96

5

5.04

5.08

5.12

5.16

5.2

D025


Load Current (A)

Out

put V

olta

ge (

V)

0 0.5 1 1.5 2 2.5 34.9

4.92

4.94

4.96

4.98

5

5.02

5.04

5.06

5.08

5.1

D025


Load Current (A)

Out

put V

olta

ge (

V)

0.001 0.01 0.1 1 5523.6

23.7

23.8

23.9

24

24.1

24.2

24.3

24.4

24.5

D023


Load Current (A)

Out

put V

olta

ge (

V)

0 0.5 1 1.5 2 2.5 3 3.5 423.6

23.7

23.8

23.9

24

24.1

24.2

24.3

24.4

24.5

D023


35














Figure 51. LM76003 Dropout Curve





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Input Voltage (V)

Out

put V

olta

ge (

V)

23.5 24 24.5 25 25.5 26 26.5 2722

22.5

23

23.5

24

24.5

25

D032


VOUT

VSW

(500 mA/DIV)

Time (1 ms/DIV)

IINDUCTOR

(20 mV/DIV)

(5 V/DIV)

Input Voltage (V)

Out

put V

olta

ge (

V)

4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.53.8

4

4.2

4.4

4.6

4.8

5

5.2

5.4

5.6

D030

ILOAD = 100 mAILOAD = 1 AILOAD = 2.5 A

Input Voltage (V)

Out

put V

olta

ge (

V)

11.5 12 12.5 13 13.5 14 14.5 1510.6

10.8

11

11.2

11.4

11.6

11.8

12

12.2

12.4

D031


Input Voltage (V)

Out

put V

olta

ge (

V)

4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.53.8

4

4.2

4.4

4.6

4.8

5

5.2

5.4

5.6

D028


Input Voltage (V)

Out

put V

olta

ge (

V)

4.5 4.75 5 5.25 5.5 5.75 6 6.25 6.53.8

4

4.2

4.4

4.6

4.8

5

5.2

5.4

5.6

D029


36















VIN = 12 V VOUT = 5 V fSW = 500 kHzNo Load Auto Mode

Figure 58. LM76003 Switching Waveform and OutputRipple



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VOUT

PGOOD

(2 A/DIV)

Time (5 ms/DIV)

IINDUCTOR

(2 V/DIV)

(2 V/DIV)

Enable(2 V/DIV)

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(2 V/DIV)

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(500 mA/DIV)

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(20 mV/DIV)

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PGOOD

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(2 V/DIV)

Enable(2 V/DIV)

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(500 mA/DIV)

Time (2 µs/DIV)

IINDUCTOR

(20 mV/DIV)

(5 V/DIV)

VOUT

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(500 mA/DIV)

Time (2 µs/DIV)

IINDUCTOR

(20 mV/DIV)

(5 V/DIV)

37





VIN = 12 V VOUT = 5 V fSW = 500 kHzNo Load FPWM Mode


VIN = 12 V VOUT = 5 V fSW = 500 kHz100-mA Load Auto Mode


VIN = 12 V VOUT = 5 V fSW = 500 kHz100-mA Load FPWM Mode


VIN = 12 V VOUT = 3.3 V fSW = 500 kHzNo Load Auto Mode

Figure 62. LM76003 Start-up Waveform

VIN = 12 V VOUT = 3.3 V fSW = 500 kHzNo Load FPWM Mode






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VOUT

PGOOD

(2 A/DIV)

Time (5 ms/DIV)

IINDUCTOR

(2 V/DIV)

(2 V/DIV)

Enable(2 V/DIV)

VOUT

PGOOD

(2 A/DIV)

Time (5 ms/DIV)

IINDUCTOR

(2 V/DIV)

(2 V/DIV)

Enable(2 V/DIV)

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(2 V/DIV)

Enable(2 V/DIV)

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Time (5 ms/DIV)

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Enable(2 V/DIV)

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VIN = 12 V VOUT = 3.3 V fSW = 500 kHz3.5-A Load


VIN = 12 V VOUT = 5 V fSW = 500 kHz3.5-A Load




VIN = 12 V VOUT = 5 V fSW = 500 kHz2.5-A Load



Figure 70. LM76003 Start-up With Pre-Biased Output



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VOUT

ILOAD

(2 A/DIV)

Time (100 µs/DIV)

IINDUCTOR

(200 mV/DIV)

(2 A/DIV)

VOUT

ILOAD

(2 A/DIV)

Time (100 µs/DIV)

IINDUCTOR

(200 mV/DIV)

(2 A/DIV)

VOUT

ILOAD

(2 A/DIV)

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(200 mV/DIV)

(2 A/DIV)

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(2 A/DIV)

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IINDUCTOR

(200 mV/DIV)

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PGOOD

(2 A/DIV)

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IINDUCTOR

(2 V/DIV)

(2 V/DIV)

Enable(2 V/DIV)

VOUT

VSW

(2 A/DIV)

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IINDUCTOR

(1 V/DIV)

(5 V/DIV)

39






Figure 71. LM76002 Start-up With Pre-Biased Output

VIN = 12 V VOUT = 5 V fSW = 500 kHzAuto Mode

Figure 72. LM76003 Short-Circuit Behavior With Hiccup

VIN = 12 V VOUT = 3.3 V fSW = 500 kHz10 mA to 3.5 A to 10 mA Auto Mode

Figure 73. LM76003 Load Transient

VIN = 12 V VOUT = 3.3 V fSW = 500 kHz10 mA to 3.5 A to 10 mA FPWM Mode


VIN = 12 V VOUT = 5 V fSW = 500 kHz10 mA to 3.5 A to 10 mA Auto Mode


VIN = 12 V VOUT = 5 V fSW = 500 kHz10 mA to 3.5 A to 10 mA FPWM Mode




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VOUT

ILOAD

(2 A/DIV)

Time (100 µs/DIV)

IINDUCTOR

(500 mV/DIV)

(2 A/DIV)

VOUT

ILOAD

(2 A/DIV)

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(500 mV/DIV)

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(2 A/DIV)

VOUT

ILOAD

(2 A/DIV)

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IINDUCTOR

(200 mV/DIV)

(2 A/DIV)

40



















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VOUT

ILOAD

(2 A/DIV)

Time (100 µs/DIV)

IINDUCTOR

(200 mV/DIV)

(1 A/DIV)

VOUT

ILOAD

(2 A/DIV)

Time (100 µs/DIV)

IINDUCTOR

(200 mV/DIV)

(1 A/DIV)

41











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42




9 Power Supply RecommendationsThe LM76002/LM76003 is designed to operate from an input voltage supply range between 3.5 V and 60 V. Thisinput supply must be able to withstand the maximum input current and maintain a voltage above 3.5 V. Theresistance of the input supply rail must be low enough that an input current transient does not cause a highenough drop at the LM76002 supply voltage that can cause a false UVLO fault triggering and system reset.

If the input supply is located more than a few inches from the LM76002/LM76003 additional bulk capacitancemay be required in addition to the ceramic bypass capacitors. The amount of bulk capacitance is not critical, buta 47-µF or 100-µF electrolytic capacitor is a typical choice.

10 Layout

10.1 Layout GuidelinesThe performance of any switching converter depends as much upon the layout of the PCB as the componentselection. The following guidelines will help the user design a circuit with maximum rejection of outside EMI andminimum generation of unwanted EMI.1. Place ceramic high frequency bypass CIN as close as possible to the LM76002/LM76003 PVIN and PGND

pins. Grounding for both the input and output capacitors should consist of localized top side planes thatconnect to the PGND pins and PAD.

2. Place bypass capacitors for VCC and BIAS close to the pins and ground the bypass capacitors to deviceground.

3. Minimize trace length to the FB pin. Both feedback resistors, RFBT and RFBB must be located close to the FBpin. Place CFF directly in parallel with RFBT. If VOUT accuracy at the load is important, make sure VOUT senseis made at the load. Route VOUT sense path away from noisy nodes and preferably through a layer on theother side of a shielding layer.

4. Use ground plane in one of the middle layers as noise shielding and heat dissipation path. Have a singlepoint ground connection to the plane. Route the ground connections for the feedback, soft start, and enablecomponents to the ground plane. This prevents any switched or load currents from flowing in the analogground traces. If not properly handled, poor grounding can result in degraded load regulation or erratic outputvoltage ripple behavior.

5. Make VIN, VOUT and ground bus connections as wide as possible. This reduces any voltage drops on theinput or output paths of the converter and maximizes efficiency.

6. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to theground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also beconnected to inner layer heat-spreading ground planes. Ensure enough copper area is used for heat-sinkingto keep the junction temperature below 125°C.

10.1.1 Layout Highlights1. Minimize area of switched current loops. From an EMI reduction standpoint, it is imperative to minimize the

high di/dt paths during PC board layout as shown in the figure above. The high current loops that do notoverlap have high di/dt content that causes observable high frequency noise on the output pin if the inputcapacitor CIN is placed at a distance away from the LM76002/LM76003. Therefore, place CIN as close aspossible to the LM76002/LM76003 PVIN and PGND pins. This minimizes the high di/dt area and reduceradiated EMI. Additionally, grounding for both the input and output capacitor must consist of a localized top-side plane that connects to the PGND pin.

2. Have a single point ground. The ground connections for the feedback, soft-start, and enable componentsshould be routed to the AGND pin of the device. This prevents any switched or load currents from flowing inthe analog ground traces. If not properly handled, poor grounding can result in degraded load regulation orerratic output voltage ripple behavior.

3. Minimize trace length to the FB pin net. Place both feedback resistors, RFBT and RFBB, close to the FB pin.Because the FB node is high impedance, maintain the copper area as small as possible. Route the tracesfrom RFBT, RFBB away from the body of the LM76002/LM76003 to minimize possible noise pickup. Place Cffdirectly in parallel with RFBT.

4. Make input and output bus connections as wide as possible. This reduces any voltage drops on the input oroutput of the converter and maximizes efficiency. To optimize voltage accuracy at the load, ensure that a



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SWPVIN

PGNDPGND

CIN

VIN

COUT

VOUTL

High di/dt current

BUCK CONVERTER

43




Layout Guidelines (continued)separate feedback voltage sense trace is made to the load. Doing so corrects for voltage drops and provideoptimum output accuracy.

5. Provide adequate device heat-sinking. Use an array of heat-sinking vias to connect the exposed pad to theground plane on the bottom PCB layer. If the PCB has multiple copper layers, these thermal vias can also beconnected to inner layer heat-spreading ground planes. For best results use a 10 × 10 via array (or greater)with a minimum via diameter of 12 mil thermal vias spaced 46.8 mil apart. Ensure enough copper area isused for heat-sinking to keep the junction temperature below 125°C.

10.1.2 Compact Layout for EMI ReductionRadiated EMI is generated by the high di/dt components in pulsing currents in switching converters. The largerarea covered by the path of a pulsing current, the more electromagnetic emission is generated. The key tominimize radiated EMI is to identify the pulsing current path and minimize the area of the path. In Buckconverters, the pulsing current path is from the VIN side of the input capacitors to HS switch, to the LS switch,and then return to the ground of the input capacitors, as shown in Figure 85.

Figure 85. Buck Converter High di / dt Path

High frequency ceramic bypass capacitors at the input side provide primary path for the high di/dt components ofthe pulsing current. Placing ceramic bypass capacitor(s) as close as possible to the PVIN and PGND pins is thekey to EMI reduction. The SW pin connecting to the inductor should be as short as possible, and just wideenough to carry the load current without excessive heating. Short, thick traces or copper pours (shapes) shouldbe used for high current condution path to minimize parasitic resistance. The output capacitors should be placeclose to the VOUT end of the inductor and closely grounded to PGND pin and exposed PAD. Place the bypasscapacitors on VCC and BIAS pins as close as possible to the pins respectively and closely grounded to PGNDand the exposed PAD.

10.1.3 Ground Plane and Thermal ConsiderationsTI recommends using one of the middle layers as a solid ground plane. Ground plane provides shielding forsensitive circuits and traces. It also provides a quiet reference potential for the control circuitry. Connect theAGND and PGND pins to the ground plane using vias right next to the bypass capacitors. PGND pins areconnected to the source of the internal LS switch; connect the PGND pins directly to the grounds of the input andoutput capacitors. The PGND net contains noise at the switching frequency and may bounce due to loadvariations. The PGND trace, as well as PVIN and SW traces, should be constrained to one side of the groundplane. The other side of the ground plane contains much less noise — use for sensitive routes.

Provide adequate device heat sinking by utilizing the PAD of the device as the primary thermal path. Use aminimum 4 by 4 array of 10 mil thermal vias to connect the PAD to the system ground plane for heat sinking.Distribute the vias evenly under the PAD. Use as much copper as possible for system ground plane on the topand bottom layers for the best heat dissipation. TI recommends using a four-layer board with the copperthickness, for the four layers, starting from the top one, 2 oz / 1 oz / 1 oz / 2 oz. Four layer boards with enoughcopper thickness and proper layout provides low current conduction impedance, proper shielding and lowerthermal resistance.

The thermal characteristics of the LM76002/LM76003 are specified using the parameter RθJA, which characterizethe junction temperature of the silicon to the ambient temperature in a specific system. Although the value of RθJAis dependant on many variables, it still can be used to approximate the operating junction temperature of thedevice.

To obtain an estimate of the device junction temperature, one may use the following relationship:



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10

12

14

16

18

20

22

24

26

28

30

20 30 40 50 60 70 80

1W @0 fpm - 2layer

1W @0 fpm - 4layer

2W @0 fpm - 2layer

2W @0 fpm - 4layer

Copper Area

R,

JA (

°C/W

)

30mm × 30mm 40mm × 40mm 50mm × 50mm 70mm ×70mm

44




Layout Guidelines (continued)TJ = PD × RθJA + TA

where• TJ = junction temperature in °C• PD = VIN × IIN × (1 − efficiency) − 1.1 × IOUT × DCR• DCR = inductor DC parasitic resistance in Ω• RθJA = junction-to-ambient thermal resistance of the device in °C/W• TA = ambient temperature in °C. (31)

The maximum operating junction temperature of the LM76002/LM76003 is 125°C. RθJA is highly related to PCBsize and layout, as well as environmental factors such as heat sinking and air flow. Figure 86 shows measuredresults of RθJA with different copper area on a 2-layer board and a 4-layer board.

Figure 86. Measured RθJA vs PCB Copper Area on a 2-Layer Board and a 4-Layer Board

10.1.4 Feedback ResistorsTo reduce noise sensitivity of the output voltage feedback path, it is important to place the resistor divider andCFF close to the FB pin, rather than close to the load. The FB pin is the input to the error amplifier, so it is a highimpedance node and very sensitive to noise. Placing the resistor divider and CFF closer to the FB pin reduces thetrace length of FB signal and reduces noise coupling. The output node is a low impedance node, so the tracefrom VOUT to the resistor divider can be long if short path is not available.

If voltage accuracy at the load is important, make sure voltage sense is made at the load. Doing so corrects forvoltage drops along the traces and provide the best output accuracy. The voltage sense trace from the load tothe feedback resistor divider should be routed away from the SW node path, the inductor and VIN path to avoidcontaminating the feedback signal with switch noise, while also minimizing the trace length. This is mostimportant when high value resistors are used to set the output voltage. TI recommends routing the voltage sensetrace on a different layer than the inductor, SW node and VIN path, such that there is a ground plane in betweenthe feedback trace and inductor / SW node / VIN polygon. This provides further shielding for the voltagefeedback path from switching noises.



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45




10.2 Layout Example

Figure 87. Layout



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22

CA

500 C cmBoard Area_cm

R WT

q ud u

CA125 C 85 C

R < 1.7 C/W < 12.84 C/W2.75 WT

q q q q

J-MAX A-MAXCA CA

IC _LOSS

T T R < R

PT T

46




10.3 Thermal DesignWhen calculating module dissipation use the maximum input voltage and the average output current for theapplication. Many common operating conditions are provided in the characteristic curves such that less commonapplications can be derived through interpolation. In all designs, the junction temperature must be kept below therated maximum of 125°C. For the design case of VIN = 12 V, VOUT = 5 V, IOUT = 3.5 A, fSW = 2100 kHz, and TA-MAX = 85°C, the part must see a thermal resistance from exposed pad (case) to ambient (RθCA)

(32)

The typical thermal impedance from junction to case is 1.7°C/W. Use the 125°C power dissipation curves inTypical Characteristics section to estimate the PIC-LOSS for the application being designed. In this application it is3 W. The inductor losses must be subtracted from this number and can be estimated as:

(33)

To reach RθCA = 12.84°C/W, the PCB is required to dissipate heat effectively. With no airflow and no externalheat-sink, a good estimate of the required board area covered by 2 oz. copper on both the top and bottom metallayers is:

(34)

As a result, approximately 38.95 square cm of 2 oz. copper on top and bottom layers is the minimum requiredarea for the example PCB design. This is a 6.25 cm (2.45 inch) square. The PCB copper heat sink must beconnected to the pins of the device and to the exposed pad with multiple thermal vias to the bottom copper. Foran example of a high thermal performance PCB layout refer to AN-2020 Thermal Design By Insight, NotHindsight and the evaluation board documentation.



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http://www.ti.com/lit/pdf/SNVA419

http://www.ti.com/lit/pdf/SNVA419

47




11 Device and Documentation Support

11.1 Device Support

11.1.1 Development Support

11.1.1.1 Custom Design With WEBENCH® ToolsClick here to create a custom design using the LM76002 or LM76003 device with the WEBENCH® PowerDesigner.1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-timepricing and component availability.

In most cases, these actions are available:• Run electrical simulations to see important waveforms and circuit performance• Run thermal simulations to understand board thermal performance• Export customized schematic and layout into popular CAD formats• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

11.2 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates, navigate to the device product folder on ti.com. In the upperright corner, click on Alert me to register and receive a weekly digest of any product information that haschanged. For change details, review the revision history included in any revised document.

11.3 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

11.4 TrademarksE2E is a trademark of Texas Instruments.WEBENCH is a registered trademark of Texas Instruments.All other trademarks are the property of their respective owners.

11.5 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

11.6 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.



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12 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.



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49






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EXAMPLE STENCIL DESIGN

22X (0.75)

30X (0.25)

26X (0.5)

(3.65)

(5.8)

(0.57)TYP

8X (0.8)

(R ) TYP0.05

8X(0.94)

8X (0.6)

(0.5) TYP

(1.14)TYP

WQFN - 0.8 mm max heightRNP0030BPLASTIC QUAD FLATPACK - NO LEAD

4222784/A 02/2016

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternatedesign recommendations.

SYMM

METALTYP

BASED ON 0.125 mm THICK STENCILSOLDER PASTE EXAMPLE

EXPOSED PAD 31:74.3% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

SYMM

1

11

12 15

16

26

2730

31

50






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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

LM76002RNPR ACTIVE WQFN RNP 30 3000 Green (RoHS& no Sb/Br)

CU SN Level-2-260C-1 YEAR -40 to 125 LM76002RNP

LM76002RNPT ACTIVE WQFN RNP 30 250 Green (RoHS& no Sb/Br)


LM76003RNPR ACTIVE WQFN RNP 30 3000 Green (RoHS& no Sb/Br)


LM76003RNPT ACTIVE WQFN RNP 30 250 Green (RoHS& no Sb/Br)


(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

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PACKAGE OPTION ADDENDUM

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continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

IMPORTANT NOTICE

Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to itssemiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyersshould obtain the latest relevant information before placing orders and should verify that such information is current and complete.TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integratedcircuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products andservices.Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and isaccompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduceddocumentation. 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IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES INCONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEENADVISED OF THE POSSIBILITY OF SUCH DAMAGES.Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, suchproducts are intended to help enable customers to design and create their own applications that meet applicable functional safety standardsand requirements. Using products in an application does not by itself establish any safety features in the application. Designers mustensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products inlife-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., lifesupport, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, allmedical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applicationsand that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatoryrequirements in connection with such selection.Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s non-compliance with the terms and provisions of this Notice.

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