ln 11 system design methodology
TRANSCRIPT
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-1
Chapter 11: System Design Methodology
Department of Electronic Engineering
National Taiwan University of Science and Technology
Prof. Ming-Bo Lin
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-2
Syllabus
ObjectivesFinite-state machine (FSM)RTL designRTL implementation options
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-3
ObjectivesAfter completing this chapter, you will be able to:
Describe the features of finite-state machines (FSMs)Understand how to model FSMsDescribe basic structures of register-transfer designsDescribe basic structures and features of algorithmic-state machine (ASM) chartsUnderstand how to model ASMsDescribe the features and structures of datapath and control designsDescribe the realizations of RTL designsUnderstand the relationship between iterative logic and FSMs
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-4
Syllabus
ObjectivesFinite-state machine (FSM)
DefinitionTypes of FSMModeling styles
RTL designRTL implementation options
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-5
Finite-State Machines (FSMs)
A finite-state machine (FSM) M = (I, O, S, δ, λ)
I , O, and S are finite, nonempty sets of inputs, outputs, and states
State transition function; δ: Ι × S → S λ
Output function λ : I × S → O (Mealy machine)
λ : S → O (Moore machine)
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-6
Types of Sequential Circuits
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-7
State Encoding
Common FSM encoding options:One-hot code Binary code Gray code Random code
One-hot encoding usually used in FPGA-based designs
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-8
Syllabus
ObjectivesFinite-state machine (FSM)
DefinitionTypes of FSMModeling styles
RTL designRTL implementation options
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-9
How to Realize an FSM?
Explicit fsmEasy to write Widely used
Implicit fsmInferred from the activity within a cyclic (always …) behaviorHard to write Not every synthesis tool supports this type FSM
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-10
Explicit vs. Implicit FSMs
// an implicit FSM examplemodule sum_3data_implicit(clk, data, total);parameter N = 8;input clk;input [N-1:0] data;output [N-1:0] total;reg [N-1:0] total;// we do not declare state registers.always begin
@(posedge clk) total <= data;@(posedge clk) total <= total + data;@(posedge clk) total <= total + data;
endendmodule
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-11
Explicit vs. Implicit FSMs
// an explicit FSM exampleparameter N = 8;input clk, reset;input [N-1:0] data;output [N-1:0] total;reg [N-1:0] total;reg [1:0] state; // declare state registers explicitlyparameter A = 2'b00, B =2'b01, C = 2'b10;always @(posedge clk)
if (reset) state <= A; elsecase (state)
A: begin total <= data; state <= B; endB: begin total <= total + data; state <= C; endC: begin total <= total + data; state <= A; end
endcase
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-12
Syllabus
ObjectivesFinite-state machine (FSM)
DefinitionTypes of FSMModeling styles
RTL designRTL implementation options
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-13
(Explicit) FSM Realization
Two realization issuesstate-registernext-state and output functions
State register one registertwo registers
Output and next state functionscontinuous assignmentfunctionalways blocka combination of the above
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-14
FSM Modeling StylesStyle 1: one state register
part 1: initialize and update the state register always @(posedge clk or negedge reset_n)
if (!reset_n) state <= A;else state <= next_state (state, x) ;
part 2: determine next state using functionfunction next_state (input present_state, x)
case (present_state ) …endcase endfunction
part 3: determine output functionalways @(state or x) case (state) … orassignment statements
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-15
FSM Modeling Styles
Style 2: two state registerspart 1: initialize and update the state register
always @(posedge clk or negedge reset_n)if (!reset_n) present_state <= A; else present_state <= next_state;
part 2: determine next state
always @(present_state or x) case (present_state ) … orassignment statementspart 3: determine output function
always @(present_state or x) case (present_state ) … orassignment statements
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-16
A 0101 Sequence DetectorDesign an FSM to detect the pattern 0101 in the input sequence x
Assume that overlapping pattern is allowed
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-17
The 0101 Sequence Detector: Style 1a
// Mealy machine example --- Use only state register and one always block.module sequence_detector_mealy (clk, reset_n, x, z);….reg [1:0] state; // Use for both ps and nsparameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;// the body of sequence detector --- Use only one always block.always @(posedge clk or negedge reset_n) begin
if (!reset_n) state <= A; else state <= fsm_next_state(state, x); endfunction [1:0] fsm_next_state (input [1:0] present_state, input x);reg [1:0] next_state;begin case (present_state)
A: if (x) next_state = A; else next_state = B; ….
endcasefsm_next_state = next_state;
end endfunctionassign z = (x == 1 && state == D);
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-18
The 0101 Sequence Detector: style 1b
// a b ehavioral description of 0101 sequence detector: style 1b input x, clk, reset_n;…reg [1:0] state; // Use for both ps and nsparameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;// the body of sequence detector --- use two always blocksalways @(posedge clk or negedge reset_n) begin
if (!reset_n) state <= A; else state <= fsm_next_state(state, x); endfunction [1:0] fsm_next_state (input [1:0] present_state, input x);
…. Same as that of style 1a end endfunctionalways @(state or x) case (state) // evaluate output function z
A: if (x) z = 1'b0; else z = 1'b0; B: if (x) z = 1'b0; else z = 1'b0;C: if (x) z = 1'b0; else z = 1'b0; D: if (x) z = 1'b1; else z = 1'b0;
endcase
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-19
The 0101 Sequence Detector: style 2
// a behavioral description of 0101 sequence detector: style 2module sequence_detector_mealy (clk, reset_n, x, z);input x, clk, reset_n;output z;// local declarationreg [1:0] present_state, next_state; // present state and next statereg z;parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;// part 1: initialize to state A and update state registeralways @(posedge clk or negedge reset_n)
if (!reset_n) present_state <= A;else present_state <= next_state; // update present state
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-20
The 0101 Sequence Detector: style 2
// part 2: determine next statealways @(present_state or x)
case (present_state)A: if (x) next_state = A; else next_state = B;B: if (x) next_state = C; else next_state = B;…
endcase// part 3: evaluate output function zalways @(present_state or x)
case (present_state)A: if (x) z = 1'b0; else z = 1'b0;…D: if (x) z = 1'b1; else z = 1'b0;
endcaseendmodule
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-21
The 0101 Sequence Detector
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-22
Syllabus
ObjectivesFinite-state machine (FSM)RTL design
ASM chartASM modeling stylesDatapath and controller design
RTL implementation options
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-23
Register-Transfer-Level (RTL) Design
Features of RTL designsSequential machinesStructuralFunctionality only
Two types of RTL design ASM (algorithmic-state machine) chartDatapath and controller (FSMD)
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-24
ASM Charts
ASM (algorithmic state machine) chartsSpecify RTL operations on the per-cycle basisShow clearly the flow of control from state to state
An ASM chart is composed ofState blockDecision blockConditional output block
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-25
ASM State Blocks
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-26
ASM Blocks
An ASM block
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-27
Invalid ASM Blocks
Examples
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-28
Syllabus
ObjectivesFinite-state machine (FSM)RTL design
ASM chartASM modeling stylesDatapath and controller design
RTL implementation options
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-29
ASM Modeling Styles
Style 1a: one state register and one always block (Not a good style!!!)
part 1: initialize, determine, update the state register, and determine RTL operations
always @(posedge clk or negedge start_n)if (!start_n) state <= A; else state <= …;
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-30
ASM Modeling Styles
Style 1b: one state register and two always blockspart 1: initialize, determine, and update the state register
always @(posedge clk or negedge start_n)if (!start_n) state <= A; else state <= …;
part 2: determine RTL operationsalways @(posedge clk) case (state ) … orassignment statements
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-31
ASM Modeling StylesStyle 2: two state registers and three always blocks (the best style !!!!)
part 1: initialize and update the state register always @(posedge clk or negedge start_n)
if (!start_n) present_state <= A; else present_state <= next_state;
part 2: determine next state
always @(present_state or x) case (present_state ) … or assignment statementspart 3: determine RTL operations
always @(posedge clk) case (present_state ) … orassignment statements
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-32
An ASM Example --- Booth Multiplier
Booth multiplication algorithm
At ith step
Assume that: 0121 xxxxX nn −−=
0121 yyyyY nn −−=
• Add 0 to partial product P if• Add Y to partial product P if• Subtract Y from partial product P if• Add 0 to partial product P if
001 =−ii xx
111 =−ii xx
011 =−ii xx101 =−ii xx
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-33
An ASM Example --- Booth Multiplier
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-34
An ASM Example --- Booth Multiplier
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-35
An ASM Example --- Booth Multiplier: Style 2 (1/3)
// Booth multiplier: style 2 --- using three always blocksmodule booth (clk, start_n, multiplier, multiplicand, product, finish);parameter W = 8; // word size parameter N = 3; // N = log2(W)input clk, start_n;input [W-1:0] multiplier, multiplicand;output [2*W-1:0] product;wire [2*W-1:0] product; reg [W-1:0] mcand, acc; reg [N-1:0] cnt; reg [W:0] mp; // one extra bitreg [1:0] ps, ns;output reg finish; // finish flagparameter idle = 2'b00, load = 2'b01, compute = 2'b10, shift_right = 2'b11;
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-36
An ASM Example --- Booth Multiplier: Style 2 (2/3)
// part 1: initialize and update state registersalways @(posedge clk or negedge start_n)
if (!start_n) ps <= idle; else ps <= ns;
// part 2: determine next statealways @(*) case (ps)
idle: if (!finish) ns = load; else ns = idle;load: ns = compute;compute: ns = shift_right;shift_right: if (cnt == 0) ns = idle; else ns = compute;
endcase// part 3: execute RTL operationsalways @(posedge clk) begin
if (!start_n) finish <= 0;case (ps)
idle: ;
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-37
An ASM Example --- Booth Multiplier: Style 2 (3/3)
load: beginmp <= {multiplier,1'b0}; mcand <= multiplicand; acc <= 0; cnt <= W - 1; end
compute: begincase (mp[1:0])
2'b01: acc <= acc + mcand;2'b10: acc <= acc - mcand;default: ; // do nothing
endcase endshift_right: begin
{acc, mp} <= {acc[W-1], acc, mp[W:1]}; cnt <= cnt - 1; if (cnt == 0) finish <= 1; end
endcaseendassign product = {acc, mp[W:1]};endmodule
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-38
An ASM Example ---Booth Multiplier
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-39
Syllabus
ObjectivesFinite-state machine (FSM)RTL design
ASM chartASM modeling stylesDatapath and controller design
RTL implementation options
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-40
dp+cu Architecture Design
Three major partsdata pathMemorycontrol unit
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-41
A dp+cu Approach Example --- Booth Multiplier
Datapathpart 3: the registers and function units in RTL operation block
Controllerpart 1 and 2: the next state function part 3: the control signals in the RTL operation block
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-42
A dp+cu Approach Example --- Booth Multiplier
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-43
A Three-Step Paradigm
1. Model the design (ASM chart)2. Extract the datapath3. Extract control-unit module and construct top
module
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-44
Syllabus
ObjectivesFinite-state machine (FSM)RTL designRTL implementation options
Single-cycle structureMultiple-cycle structurePipeline structureFSM versus iterative logic
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-45
Realization Options of RTL Design
A tradeoff amongperformance (throughput, operating frequency)space (area, hardware cost)power consumption
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-46
Realization Options of RTL Design
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-47
A Single-Cycle Example
// a single-cycle exampleparameter N = 8;input clk;input [N-1:0] data_a, data_b, data_c;output reg [N-1:0] total;// compute total = data_c - (data_a + data_b)always @(posedge clk) begin
total <= data_c - (data_a + data_b); end
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-48
Syllabus
ObjectivesFinite-state machine (FSM)RTL designRTL implementation options
Single-cycle structureMultiple-cycle structurePipeline structureFSM versus iterative logic
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-49
Multiple-Cycle Structure
Linear structureNonlinear (feedback or feed-forward) structure
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-50
A Multiple-Cycle Example// a multiple cycle example --- an implicit FSMparameter N = 8;input clk;input [N-1:0] data_a, data_b, data_c;output reg [N-1:0] total;reg [N-1:0] qout_a, qout_b;// compute total = data_c - (data_a + data_b)always @(posedge clk) begin
qout_a <= data_a;@(posedge clk) qout_b <= qout_a + data_b;@(posedge clk) total <= data_c - qout_b;
end
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-51
Syllabus
ObjectivesFinite-state machine (FSM)RTL designRTL implementation options
Single-cycle structureMultiple-cycle structurePipeline structureFSM versus iterative logic
![Page 52: Ln 11 System Design Methodology](https://reader030.vdocument.in/reader030/viewer/2022032512/55cf9b7b550346d033a63c7c/html5/thumbnails/52.jpg)
Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-52
Pipeline Structure
PipelineStream data inputPipeline latencyOne output per clock period
1,, +−++> iskewidsetupFFi ttttT
},...,2,1|max{ miTT ipipe ==
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-53
Pipeline Principles
ParametersPipeline depthPipeline latencyClock period
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-54
A Simple Pipeline Example --- Not a Good One// a simple pipeline example --- Not a good onemodule simple_pipeline(clk, data_a, data_b, data_c, total);parameter N = 8;…input [N-1:0] data_a, data_b, data_c;output reg [N-1:0] total;reg [N-1:0] qout_a, qout_b;// compute total = data_c - (data_a + data_b)always @(posedge clk) begin
qout_a <= data_a;qout_b <= qout_a + data_b;total <= data_c - qout_b;
end
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-55
A Simple Pipeline Example
// a simple pipeline exampleparameter N = 8;…input [N-1:0] data_a, data_b, data_c;output reg [N-1:0] total;reg [N-1:0] qout_a, qout_b, qout_c, qout_d, qout_e;// compute total = data_c - (data_a + data_b)always @(posedge clk) begin
qout_a <= data_a; qout_b <= data_b; qout_c <= data_c;qout_d <= qout_a + qout_b;qout_e <= qout_c;
total <= qout_e - qout_d;end
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-56
Syllabus
ObjectivesFinite-state machine (FSM)RTL designRTL implementation options
Single-cycle structureMultiple-cycle structurePipeline structureFSM versus iterative logic
![Page 57: Ln 11 System Design Methodology](https://reader030.vdocument.in/reader030/viewer/2022032512/55cf9b7b550346d033a63c7c/html5/thumbnails/57.jpg)
Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-57
FSM vs. Iterative LogicAn FSM expansion in timeAn example of 1-D iterative logic
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-58
An Example --- A 0101 Sequence Detector
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-59
An Example --- A 0101 Sequence Detector
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-60
An Example --- A 0101 Sequence Detector
// Behavioral description of 0101 sequence detector parameter n = 6; // define the size of 0101 sequence detectorinput [n-1:0] x;output wire [n-1:0] z;wire [n-1:0] next_state_1, next_state_0 ;parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;…generate for(i = 0; i < n; i = i + 1) begin: detector_0101
if (i == 0)begin: LSB // describe LSB cellbasic_cell bc (x[i], A, z[i], {next_state_1[i], next_state_0[i]}); end
else begin: rest_bits // describe the rest bitsbasic_cell bc (x[i], {next_state_1[i-1], next_state_0[i-1]}, z[i],
{next_state_1[i], next_state_0[i]}); endend endgenerate
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-61
An Example --- A 0101 Sequence Detector// Determine next state using function next_state.module basic_cell (x, present_state, output_z, next_state);input x; input [1:0] present_state; output reg [1:0] next_state;output reg output_z;parameter A = 2'b00, B = 2'b01, C = 2'b10, D = 2'b11;// Determine the next statealways @(present_state or x) case (present_state)
A: if (x) next_state = A; else next_state = B; ……
endcase// Determine the output valuealways @(present_state or x) case (present_state)
A: if (x) output_z = 1'b0; else output_z = 1'b0;……
endcase
Exactly the same as the next state logic of FSM.
Exactly the same as the output logic of FSM.
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-62
2D-Iterative Logic Example --- Booth Multiplier
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Chapter 11: System Design Methodology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 11-63
2D-Iterative Logic Example --- Booth Multiplier