Emerging Challenges in Evaluation of Silicon Carbide Materials-Device Interactions

M.J. Loboda*, G. Chung* *Dow Corning Corporation, Midland, MI 48686; mark.loboda@dowcorning.com; gil.chung@dowcorning.com;

ABSTRACT The last five years have produced significant advances in technology for silicon carbide power devices. Substrates

with diameter of 100 mm are now widely used in production and industry now has started the transition to 150 mm diameter SiC substrates. Bulk crystal originated defects such as screw and basal dislocation have generally dropped >10x in concentration to levels in the 103/cm2 range. Today, micropipes are essentially concern of the past. Now there is more focus on surface contamination and defects originated in CVD epitaxy, the latter representing the materials-related defect most commonly impacting device performance and manufacturing yields.

Improvements in substrates and device technology now deliver larger area power devices. Recent news of new suppliers of SiC MOSFETs is likely to queue increased growth in adoption of SiC power devices in system applications. As a result there is still focus on how to grow understanding in materials-device interactions that will help improve manufacturing yields and understand device reliability. The increase in device complexity and area brings new challenges to develop improved understanding for materials device correlations. This presentation will review the state of the art in SiC substrates and several emerging issues pertaining to evaluation of materials-device interactions that are pertinent to current trends in SiC devices. Among the list of critical issues are statistical approaches, the impact of defect clustering, match of materials characterization strategy to device fabrication and nano-scale surface perturbations. It is the authors’ objectives to increase awareness of these new issues in order to work with the community to help prioritize strategies and understand the impact the issues have on device performance and yield.

Keywords: SiC, power electronics, material-device correlations.

Introduction

All power device operation is intimately influenced by the substrate properties. The key substrate properties are wafer resistivity, wafer thickness, epitaxy layer doping, epitaxy layer thickness, epitaxy layer mobility and epitaxy defects. Among these metrics, the first four can vary widely in value depending on the location within the substrate. Defects which perturb the epitaxy surface usually render devices inoperative.

In the case of 4H-SiC substrates, the range of within substrate variations of the key metrics are generally larger than in silicon substrates. This characteristic of SiC substrates is generally regarded as leading to difficulty to achieve consistent device operation and fabrication yields. We will discuss current perspectives on surface defects and within wafer metric variations as it pertains to power device fabrication.

SiC Epitaxy Surface Defects – Power Device Interactions

Surface perturbations in SiC epitaxy films are known killer defects for power devices. A detailed study was performed in 2013 to check the influence of surface defects on breakdown voltage failures in devices and the ability of non destructive wafer inspection systems to grade the defect density accurately enough to predict the device breakdown failures. Many different high quality SiC epitaxy substrates were randomly selected for the test. Laser light scattering spectrometry (LLS) defect density measurements performed on randomly selected of the wafers in the set. The substrates were populated with junction Schottky barrier diodes of various areas including 2x2 mm2 and 4x4 mm2 using a commercially proven process flow. All diodes on the wafers were probed for breakdown failures. Based on the breakdown voltage yields, or LLS site yields, as a function of die area the characteristic defect density can be estimated by fitting the LOG(yield) vs. device area data and assuming a Poisson distribution. Figure 1 compares the results.

Invited Paper Workshop on Defects in Wide Band Gap Semiconductor September 23rd, 2014 - University of Maryland, College Park

Inspection of Figure 1 shows good agreement between the defect density that was measured electrically and that from the automated light scattering inspection. Analysis of failures indicates the mean value of defect density is about 1.5/cm2. Since the defect density values measured by both techniques are comparable it can be concluded that epitaxy surface defects represent the defect that resulted in the breakdown voltage failures.

As the capability of surface defect inspection improves, it is now possible to resolve smaller features on the surface of the epitaxy substrate. Recently a defect represented by very small depressions has been detected on SiC epitaxy substrates. The defect, referred to as a “micropit,” is shown in Figure 2. AFM analysis (Fig. 2c) indicates a typical depth of <100 nm. KOH molten salt etching has been performed and indicates the pit is tied to a threading screw dislocation (Fig. 2b). Theoretical simulation and local emission microscope data was reported to show leakage current increase with micropits [1,2]. Fully processed diodes and MOS capacitors with micropits in the active area, however, show no difference in reverse breakdown and time zero dielectric breakdown values when compared to devices free of the defects, respectively. Any impact of these defects on device reliability is not yet established.

Trends in SiC power devices continue to achieve device designs capable of higher voltage and current. As the device active area is increased, there is likely to be clusters of similar defects in the active region. The clustering will

Figure 3. Correlations between high voltage JBS diode breakdown and leakage current with screw dislocation density in the anode region. All of the devices in the right figure were measured on the same

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Pre-fabrication LLS Test on epiwafers. Assumes die uniformly distributed on device wafer

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Images of “micropits” detected on the surface of 4H-SiC epitaxy wafers: (a) laser interferometer; (b) KOH etched epitaxy surface; (c) atomic force microscope analysis.

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Figure 1. Defect density values for 4H-SiC wafers fabricated with junction barrier Schottky diodes. The left side is determined from electrical failures, the right side from automated laser light scattering epitaxy surface defect measurements.

make it difficult to interpret the impact of substrate crystalline or epitaxy defects on device operation. The presence of any epitaxy surface defect in the active device area will inhibit proper device operation. But what is the impact of clusters of crystalline defects on device operation when surface defects are absent? Figure 3 shows analyses of high voltage JBS diodes, which are a favorable platform to explore impact of defect clusters. All of the diodes analyzed in Figure 3 were free of epitaxy surface defects. Once probed for reverse bias leakage, the anodes were removed and the screw dislocation defect density was measured in the anode region by molten salt etching and x-ray topography. Figure 3 shows that in these devices were the screw dislocation density was between 0-5000/cm2, it was not the primary factor which correlated to the device breakdown or leakage currents. The data in Fig. 3 is strong evidence that in the absence of epitaxy surface defects in the active region of a power device, the identification defects limiting operation of SiC devices is a complex task and will require large sample sets and significant analysis to resolve.

Impact of Substrate Metrics on Device Operation

When designing SiC devices for commercial production, what is the correct expectation for the distribution of device performance within wafer in the absence of defects? Power device OEMs use technology computer aided design (TCAD) modeling software to work up device designs for their products. Often design engineers are limited to put in values into the model for the SiC electrical properties that are found in reference books [3] and find their models are not delivering predictions of manufacturing processes to expectations. It is generally regarded that TCAD models for wide band gap materials are not as accurate for silicon devices. What’s more the models may not account for the within wafer (WIW) and wafer to wafer (W2W) variations of the electrical properties that impact the device performance. The challenge becomes the need to rationalize the device model results with measured variation in device performance. Often the mismatch of device performance shortfalls is instinctively assigned to the substrate material without evidence.

While the quality of SiC substrates is still not yet as good as silicon substrates, the consistency of commercially available substrate properties is good enough to be represented by standard probability statistics. Using well established physics models which link the substrate properties to the device performance, a method has been developed to assess the impact of WIW variations on SiC device performance. A Monte Carlo analysis program (Oracle ® Crystal Ball) is used to link the SiC electrical WIW property distributions to variations of device performance that can be expected for devices fabricated on SiC wafers. Comparison of the device performance probability with measurements performed on wafers populated with simple diodes shows that the simulations can provide a close match to the measured within wafer device parameter distributions. This simulation strategy can be used to help understand which of the substrate electrical metrics most impact device performance, and also predict how much change in the substrate is needed to achieve measureable improvements in device performance. This simulation strategy can help device designers to better align their designs with the properties of the available SiC wafer product in order to get predictable product performance.

In order to execute the model, it is necessary to assign to each of the substrate metrics a mathematical distribution function. Using large datasets obtained from measurements on 100 mm and 150 mm diameter 4H-SiC polished wafers and epitaxy wafers, a “best fit” distribution function was assigned to the wafer thickness, wafer resistivity, epitaxy film thickness and epitaxy film thickness. A Normal distribution was a suitable fit for all metrics except the wafer resistivity. This is because of the presences of the growth facet [4] on the wafer. In the region of the facet the nitrogen incorporation in the wafer is higher than the rest of the wafer and as a result the facet region shows lower resistivity values than the rest of the wafer. This creates an asymmetry in the resistivity distribution and a “min-extreme” distribution was employed.

The calculation of pure Schottky diode performance was derived from physics of power device operation [5,6,7]. A Microsoft Excel spreadsheet was used to calculate the room temperature device breakdown performance and series resistance, the two critical parameters for device designs. The Crystal Ball software was configured to use Monte Carlo analysis to determine the probability distribution of these two metrics based on the variability of the substrate metrics wafer resistivity, wafer thickness, epitaxy layer doping, epitaxy layer thickness. Four thousand iteration cycles were used in the Monte Carlo analysis.

The simulation was first employed to predict the probability distribution of breakdown voltage and series resistance of a 100 mm diameter, 4H-SiC epiwafer produced at Dow Corning. The substrate was populated with pure Schottky variable diodes by sputtering Ni metal on the surface using a shadow mask. The anode area was 0.125 cm2. The backside of the wafer was metalized with Ti to achieve good electrical connection during wafer probe measurements of current-voltage which are used to determine breakdown voltage and series resistance. The criteria used for device breakdown was 1mA.

The results of the model and measurements are shown in Figs. 4-5. Table 1 compares the distribution of results from the model with the measurements on the diodes made on the wafer.

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Figure 4. Comparison of the model (left) and measured (right) breakdown voltage probability distribution for Schottky diode made on a 100 mm diameter 4H-SiC wafer.

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Figure 5. Comparison of the model (left) and measured (right) total series resistance probability distribution for Schottky diode made on a 100 mm diameter 4H-SiC wafer.

Table 1 – Comparison of the model and measured breakdown and total series resistance distributions.

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The model effectively predicts the distribution of breakdown voltage measured on diodes. It is also predicting the lower half of the series resistance distribution. The higher than predicted resistance values are most likely due to a non-optimal metallization process in the laboratory and lack of backside ohmic contact formation in the diode fabrication. The Monte Carlo analysis does not account for resistance due to metal contacts to the diode. It is interesting to note the wide range of VBR that is achieved on the wafer and also predicted by the model.

Next the analysis was repeated for the case of 150 mm 4H SiC epiwafers. Figure 6 shows the inputs to the analysis derived from commercial 150 mm diameter SiC substrate product and the probability distributions of breakdown voltage and total series resistance.

Wafer Thk= 350 umTTV= 5 umResistivity Ave= 21.4 m-ohmResistivity Scale= 0.71Goal= 1200 V

Design= 1600 VEpi tf= 13 umEpi WIW sigma= 3%Nd= 9.7E15/cm3Epi Nd sigma= 4.3%

Epi Mobility= 825 cm2/V-secDie Size= 1 cm2Trials= 4000

The parameters selections for the model inputs in Figure 6 were developed as follows. The value for epitaxy film doping target was chosen based on experience of what is commonly used for 1200 V designs. Next, epitaxy thickness was determined from the design voltage and the critical field. The critical electric field for SiC was determined as described in [6] where the critical field is derived from an empirically developed dependence on film doping. Finally, the design voltage in Table 1 were chosen to be sure the smallest value of breakdown voltage at any possible combination of parameters was >=1200 V. This selection process of the design target thus impacts the epitaxy film thickness, and inherently impacts the total series resistance. The results show that the minimum breakdown voltage expected from the model is about 75% of the device breakdown design target, while the maximum voltage expected is about 120% of the target. The software also highlights the correlations between substrate and device parameters. Epitaxy thickness variations of 3% standard deviation account for 66% of the VBR variation and epitaxy doping variations of 4.3% standard deviation account for 33% of the VBR variation and 51% of the Rs variation.

This result is interesting when put in perspective of the current capability in state of the art SiC CVD epitaxy today. The input epitaxy and wafer variations are typical of 150 mm diameter substrates available today. The question to ask is what gains are there to be obtained if the within wafer epitaxy film thickness and doping are reduced. If the standard deviations are reduced from the values in Fig. 6 to 1% for both thickness and doping respectively, the mean predicted value of breakdown voltage stays the same at 1506V, but the range is reduced to 1400-1600V with little effect on Rs. This implies the design target can be reduced from 1600 V to shift the mean breakdown voltage lower, and reduce the epitaxy thickness. A design target of 1475V results in a breakdown range of 1200-1360V, and corresponds to reducing the thickness from 13 um in the base case (1600V design) to 12 um (1400 V design). This thickness change has very little impact on series resistance. So even if the with wafer standard deviations can be reduced from today’s values for 150 mm wafers of 3 % for film thickness and 4.3 % for doping to less than or equal to 1%, the savings in substrate manufacturing cost is very small.

Summary

Review of the state of the art for surface defects created during SiC epitaxy on commercial substrate products show these defects are the most important defect limiting SiC power device manufacturing yields. Current typical industry epitaxy defect levels 100 mm substrates are about 1.5/cm2. New automated surface analysis techniques are finding new, smaller defects on epitaxy surfaces, but the impact of these defects still needs to be determined. Analysis of large, high voltage diodes shows that when the screw dislocation density in the anode region is below 5000/cm2 these defect density

Figure 6. Monte Carlo analysis of breakdown voltage VBR and total series resistance, Rs for a Schottky diode based on

values do not correlate with the breakdown voltage or the device leakage at the breakdown condition. Analysis of the interaction of SiC substrate metrics and prediction of the breakdown and series resistance of devices fabricated on the substrates shows that a wide range of within wafer breakdown voltage is expected even when the within wafer epitaxy variations are relatively small and controlled.

Putting these observations into the context of studies focused to identify the effects of defects like screw and threading edge dislocations on device performance is a difficult task. In order to isolate of the impact of individual defect types without cross term effects, experiments require analysis of very large numbers of devices, including comparisons between matched devices that are free of, or contain the defect of interest. Considering the recent advances in SiC device technology and that the industry is poised for growth, it is recommended that the SiC community focus its combined capability to improve SiC epitaxy equipment and processes in order reduce surface defects and increase both substrate product yields and device yields. Such gains will bolster volume production of SiC devices including larger current and voltage products, and these gains can become the statistical foundation to effectively study the next discovered factor to improve SiC technology.

References

1. T.Ishikawa et. al, Materials Science Forum, Vols. 717-720 (2012) p.371

2. T. Katsuno et. al, Materials Science Forum, Vols. 717-720 (2012) p.375

3. M. Levinshtein, S. Rumyantsev, M. Shur, “Properties of Advanced Semiconductor Materials GaN, AlN, InN, BN, SiC, SiGe,” Wiley, ©2001

4. I.D. Matukov, et. al, Journal of Crystal Growth 266 (2004), p.313

5. Schoen, et. al, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 45, NO. 7, (1998) p.1595

6. R. Singh, J. Cooper, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 4, (2002) p.665,

7. M. Bhatnagar and B. J. Baliga, IEEE TRANSACTIONS ON ELECTRON DEVICES Vol.40 NO. 3 (1993), p.645