logic and-or gate vlsi design
TRANSCRIPT
-
8/9/2019 Logic AND-OR Gate VLSI Design
1/8
LABORATORY REPORT 2
LOGIC GATE AND-OR
ECE 135
Gerfel Philip C. Gonzle!
"EBR#ARY$ 2%15
-
8/9/2019 Logic AND-OR Gate VLSI Design
2/8
O&'e()i*e: Layout a LOGIC GATE with the given specifcations
+pe(i,()ion!
This are the specifcations given. I made the logic gate with only this specifcationsut the presimulation was etter than the postsimulation. Thus! the layout was not goodenough. There"ore! I made another logic gate with using # multiples on the inverter.
In*er)er +(he)i( Di/r n0 +&ol
NOR G)e +(he)i( Di/r n0 +&ol
NAND G)e +(he)i( Di/r n0 +&ol
-
8/9/2019 Logic AND-OR Gate VLSI Design
3/8
AND-OR +(he)i( Di/r
AND-OR Lo)
-
8/9/2019 Logic AND-OR Gate VLSI Design
4/8
De!i/n Rle Che( Lo) 4er!! +(he)i(
-
8/9/2019 Logic AND-OR Gate VLSI Design
5/8
Lo) Pr!i)i( E)r()ion
Te!)&en(h
6*efor Re!l)
-
8/9/2019 Logic AND-OR Gate VLSI Design
6/8
$hown aove are the wave"orms output O%T&%T! input A! input '! and input C.
Tr)h T&le
A B C O#TP#T
% % % %% % 1 1% 1 % %% 1 1 11 % % %1 % 1 11 1 % 11 1 1 1
$hown aove is the computed truth tale o" the logic gate A()*O+.
"ro )he 7*efor !ho7n &o*e n0 )he )r)h )&le$ )herefore$ )he,ni!he0 lo) of )he lo/i( /)e AND-OR i! (orre().
Copri!on
-
8/9/2019 Logic AND-OR Gate VLSI Design
7/8
$hown aove is are the wave"orms o" the presimulation and postsimulation. Also!
the rise time and "all time are measured. The postsimulation has lesser rise time and "all
time than the presimulation. Thus! clearly! the layout is etter than the r",-l.
/oomed on the +ising Edge
&resimulation
&ostsimulation
-
8/9/2019 Logic AND-OR Gate VLSI Design
8/8
PRE+I8#LATION PO+T+I8#LATION
RI+E TI8E 10.4ns 3.77ns
"ALL TI8E 4.46
ns 4
ns+LE6 RATE RI+E
TI8E SW =
1.8V
(10.4ns ) (1 x106 )
¿173.08V / μs
SW = 1.8V
(3.77ns ) (1 x106 )
¿477.45V / μs
+LE6 RATE
"ALL TI8E SW =
1.8V
(4.46ns ) (1 x106 )
¿403.59V / μs
SW = 1.8V
(4 ns) (1 x 106 )
¿450.00V / μs
Con(l!ion
The specifcation that was assigned has - multipliers. I made the logic gate with
only this specifcations ut the presimulation was etter than the postsimulation indicating
that the layout was not good. There"ore! I made another logic gate using # multiples on
the inverter. The result was astonisihing. &ostsimulation got etter.
The per"ormace o" a logic gate is measured y the slew rate or the rise time and "all
time o" the signal output. The greater the slew rate! the etter the device. $lew rate is the
ma0imum rate o" change o" the output amplitude per unit time. The lessser the rise time
or "all time! the etter the device.
As shown in the tale o" comparison aove! clearly! the postsimulation o" the logic
gate has greater slew rate than the presimulation. Also! the rise time and "all time o" the
postsimulation are lesser than the presimulation. There"ore! with the data gathered! the
postsimulation or the layouted logic A()*O+ Gate is etter than the presimulation.
I also made another conclusion! the more the multiplier! the etter is the transistor.