logic design ii (17.342) spring 2012 lecture...
TRANSCRIPT
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Logic Design II (17.342)
Spring 2012
Lecture Outline
Class # 03
February 09, 2012
Dohn Bowden
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Today’s Lecture
• Registers and Counters … Chapter 12
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Course Admin
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Administrative
• Admin for tonight … – Syllabus review
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Syllabus Review
Week Date Topics Chapter Lab Report Due
1 01/26/12 Review of combinational circuits 1-10
2 02/02/12 Intro to sequential circuits. Latches and flip-flops 11
3 02/09/12 Registers and Counters 12
4 02/16/12 Analysis of Clocked Sequential Circuits 13
5 02/23/12 Derivation of State Graphs and Tables 14 1
6 03/01/12 Examination 1
7 03/08/12 Reduction of State Tables State Assignments 15
X 03/15/12 NO CLASSES – Spring Break
8 03/22/12 Sequential Circuit Design 16 2
9 03/29/12 VHDL for Sequential Logic 17
10 04/05/12 Circuits for Arithmetic Operations 18
11 04/12/12 Examination 2 3
12 04/19/12 State Machine Design with SM Charts 19
13 04/26/12 Course Project – Build/Troubleshoot in Lab Project 4
14 05/03/12 Final Exam/Course Project Brief & Demo Demo
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Questions?
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Chapter 12
REGISTERS AND COUNTERS
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Objectives
Objectives
1. Explain the operation of registers … – Show how to transfer data between registers using a tri -state
bus
2. Explain the operation of shift registers … show how to build them using flip-flops … and … analyze their operation – Construct a timing diagram for a shift register
3. Explain the operation of binary counters … show how to build them
using flip-flops and gates … and … analyze their operation
4. Given the present state and desired next state of a flip-flop … determine the required flip-flop inputs
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Objectives
5. Given the desired counting sequence for a counter … derive the flip-flop input equations
6. Explain the procedures used for deriving flip-flop input equations
7. Construct a timing diagram for a counter by tracing signals through the circuit
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Introduction
Introduction
• A register consists of a group of flip-flops with a common clock input
• Registers are commonly used to store and shift binary data
• Counters are another simple type of sequential circuits.
• A counter is usually constructed from two or more flip-flops which … change states in a prescribed sequence when input pulses are received
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Registers and Register Transfers
Registers and Register Transfers
• Several D flip-flops may be grouped together with a common clock to form a register
• Each flip-flop can store one bit of information
• A register with four D flip-flops can store four bits of information
• A load signal can be ANDed with the clock to enable and disable loading the registers
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Registers and Register Transfers
• 4-Bit D Flip-Flop Registers with … Data … Load … Clear … and … Clock Inputs
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Registers and Register Transfers
• Load = 0 … the register is not clocked … and … holds its present value
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Registers and Register Transfers
• Load =1 … load data into the register – Load is set to 1 for one clock period
– When Load = 1 … the clock signal (Clk) is transmitted to the
flip-flop clock inputs and the data applied to the D inputs will be loaded into the flip-flops on the falling edge of the clock
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Registers and Register Transfers
• Example … Q outputs are 0000 … and … data inputs are 1101
• After the falling edge Q will change from 0000 to 1101
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Registers and Register Transfers
• The flip-flops in the register have asynchronous clear inputs that are connected to a common clear signal … ClrN
• A logic 0 is required to clear the flip-flops
• ClrN is normally 1 … if changed momentarily to 0 … the Q outputs of all four flip-flops will become 0
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Registers and Register Transfers
(Flip-Flops with Clock Enable)
Registers and Register Transfers
• If flip-flops with clock enable are available … the register can be designed as indicated below
• Symbol for the 4-bit register using bus notation for the D inputs and Q outputs
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Registers and Register Transfers
• Load = 0 … clock disabled … register holds its data • Load = 1 … clock is enabled … data applied to the D inputs will be
loaded into the flip-flops following the falling edge of the clock
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Data Transfer Between Registers
Data Transfer Between Registers
• Transferring data between registers is a common operation in digital systems
• Data can be transferred from the output of one of two registers into a third register using tri-state buffers
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Data Transfer Between Registers
• If En = 1 … and … Load = 1 … – The output of register A is enabled onto the tri-state bus … and
… – The data in register A will be stored in Q after the rising edge of
the clock
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Data Transfer Between Registers
• If En = 0 … and … Load = 1 … – The output of register B is enabled onto the tri-state bus … and
… – The data in register B will be stored in Q after the rising edge of
the clock
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Data Transfer Between Registers
(8-Bit Register with Tri-State Output)
Data Transfer Between Registers
• Below is an integrated circuit register that contains eight D flip-flops with tri-state buffers at the flip-flop outputs
• Buffers are enabled when En = 0
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Data Transfer Between Registers
• Symbol for this 8-bit register
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Data Transfer Using a Tri-State Bus
Data Transfer Using a Tri-State Bus
• Below … data can be transferred from one of four 8-bit registers into … one of two other registers
• Registers A … B … C … and … D are … 8-Bit Registers with Tri-State Output
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Data Transfer Using a Tri-State Bus
• Below … data can be transferred from one of four 8-bit registers into … one of two other registers
• Registers A … B … C … and … D are … 8-Bit Registers with Tri-State Output
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Data Transfer Using a Tri-State Bus
• Registers A … B … C … and … D outputs are all connected in parallel to a common tri-state bus
• The flip-flop inputs of registers G and H are also connected to the bus
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Data Transfer Using a Tri-State Bus
• After the rising clock edge … if … – LdG = 1 … signals on the bus loaded into register G – LdH = 1 … signals on the bus loaded into register H
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Data Transfer Using a Tri-State Bus
• The four enable signals may be generated by a decoder … the operation can be summarized as follows …
If EF = 00 … A is stored in G (or H) If EF = 01 … B is stored in G (or H) If EF = 10 … C is stored in G (or H) If EF = 11 … D is stored in G (or H)
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Parallel Adder with Accumulator
Parallel Adder with Accumulator
• Accumulator … a register of flip-flops
• Frequently it is desirable to … – Store one number in an accumulator … and …
– Add a second number to it …
• Leaving the result stored in the accumulator
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Parallel Adder with Accumulator
• N-Bit Parallel Adder with Accumulator – Registers connected to Full Adders
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Parallel Adder with Accumulator
• The number X … is stored in the accumulator • The number Y … is applied to the full adder inputs
– After the carry has propagated through the adders … the sum of
X and Y appears at the adder outputs
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Parallel Adder with Accumulator
• An add signal … Ad … is used to load the adder outputs … into … the accumulator flip-flops on the rising clock edge
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Parallel Adder with Accumulator
• The adder with accumulator is an iterative structure that consists of a number of identical cells
• Each cell contains … a full adder … and … an associated accumulator flip-flop
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Parallel Adder with Accumulator
• Before addition can take place … the accumulator must be loaded with X – First clear the accumulator using the asynchronous clear inputs
on the flip-flops … and … then put the X data on the Y inputs to the adder and add the accumulator in the normal way
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Adder Cell with Multiplexer
• Alternatively … we could add multiplexers at the accumulator inputs so that we could select either the Y input data or the adder output to load into the accumulator
• Eliminates the extra step of clearing the accumulator … but … – Would add to the hardware complexity
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Adder Cell with Multiplexer
• Below is a typical cell of the adder where the accumulator flip-flop can either be loaded directly from yi … or… from the sum output (si)
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Adder Cell with Multiplexer
• Ld = 1 … multiplexer selects yi … and … – yi is loaded into the accumulator flip-flop (xi) on the rising clock
edge • Ad = 1 … and … Ld = 0 … the adder output (si) is loaded into xi
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Adder Cell with Multiplexer
• The Ad and Ld signals are Ored together to … – Enable the clock when either addition or loading occurs
• When Ad = Ld = 0 … the clock is disabled and the accumulator outputs do not change
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Shift Registers
Shift Registers
• A shift register is … – A register in which binary data can be stored … and …
– This data can be shifted to the … left … or … right … when a
shift signal is applied
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Right Shift Registers
• A 4-bit right-shift register with serial input and output constructed from D flip-flops
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Right Shift Registers
• When Shift = 1 … the clock is enabled and shifting occurs on the rising clock edge
• When Shift = 0 … no shifting occurs and the data in the register is unchanged
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Right Shift Registers
• The serial input (SI) is … loaded into the first flip-flop (Q3) by the rising edge of the clock
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Right Shift Registers
• The serial input (SI) is … loaded into the first flip-flop (Q3) by the rising edge of the clock
• At the same time … – Output of first flip-flop is loaded into the second flip-flop
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Right Shift Registers
• The serial input (SI) is … loaded into the first flip-flop (Q3) by the rising edge of the clock
• At the same time … – Output of first flip-flop is loaded into the second flip-flop – Output of second flip-flop is loaded into the third flip-flop
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Right Shift Registers
• The serial input (SI) is … loaded into the first flip-flop (Q3) by the rising edge of the clock
• At the same time … – Output of first flip-flop is loaded into the second flip-flop – Output of second flip-flop is loaded into the third flip-flop – Output of third flip-flop is loaded into the last flip-flop
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Right Shift Registers
• Because of the propagation delay of the flip-flops … the output value loaded into each flip-flop is the value before the rising clock edge
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Right Shift Registers
• If the serial output is connected to the serial input … – The resulting cyclic shift register performs an end-around shift
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Serial-in … Serial-out Shift Register
Serial-in … Serial-out Shift Register
• Serial in … – Data is shifted into the first flip-flop one bit at a time … and …
the flip-flops cannot be loaded in parallel
• Serial out … – Data can only be read out of the last flip-flop … and … the
outputs from the other flip-flops are not connected to terminals of the integrated circuit
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Serial-in … Serial-out Shift Register
• An 8-bit serial-in … serial-out shift register
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Serial-in … Serial-out Shift Register
• Inputs to the first flip-flop are S = SI … and … R = SI‘ • When clocked …
– If … SI = 1 … a 1 is shifted into the register – If … SI = 0 … a 0 is shifted in
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Serial-in … Serial-out Shift Register
• Typical Timing Diagram for Serial Shift Register – The 8th rising edge occurs at the end of the 7th clock period
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Parallel-in … Parallel-Out … Right Shift Register
Parallel-in … Parallel-Out … Right Shift Register
• Parallel-in … – All bits can be loaded at the same time
• Parallel-out …
– All bits can be read out at the same time
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Parallel-in … Parallel-Out … Right Shift Register
• 4-bit parallel-in … parallel-out … shift register
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Parallel-in … Parallel-Out … Right Shift Register
• Two control inputs … shift enable … Sh … and … load enable …L
• Serial In … SI
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Parallel-in … Parallel-Out … Right Shift Register
• If Sh = 1 … and L = 1 … or … L = 0 … clocking causes … – SI to be shifted into the first flip-flop … while … – The data in flip-flops Q3, Q2, and Q1 are shifted right
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Parallel-in … Parallel-Out … Right Shift Register
• If Sh = 0 … and L = 1 … clocking will cause … – The four data inputs … D3, D2 , D1, D0 … to be loaded in
parallel into the flip-flops
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Parallel-in … Parallel-Out … Right Shift Register
• If Sh = L = 0 … clocking causes no change of state
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Parallel-in … Parallel-Out … Right Shift Register
• Summary of the operation for the shift register • All state changes occur immediately following the falling edge of the
clock
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Inputs Next State Action Sh (Shift) Ld (Load) Q3
+ Q2+ Q1
+ Q0+
0 0 Q3 Q2 Q1 Q0 no change 0 1 D3 D2 D1 D0 load 1 X SI Q3 Q2 Q1 right shift
Parallel-in … Parallel-Out … Right Shift Register
• The shift register can be implemented using MUXes and D flip-flops
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Parallel-in … Parallel-Out … Right Shift Register
• Using the table … The next-state equations for the flip-flops are …
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Inputs Next State Action Sh (Shift) Ld (Load) Q3
+ Q2+ Q1
+ Q0+
0 0 Q3 Q2 Q1 Q0 no change 0 1 D3 D2 D1 D0 load 1 X SI Q3 Q2 Q1 right shift
Parallel-in … Parallel-Out … Right Shift Register
• A typical application of this register is … – The conversion of parallel data to serial data
• The output from the last flip-flop … Q0 … serves as a serial
output as well as one of the parallel outputs
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Parallel-in … Parallel-Out … Right Shift Register
• Typical timing diagram …
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Parallel-in … Parallel-Out … Right Shift Register
• The first clock pulse loads data into the shift register in parallel …
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Parallel-in … Parallel-Out … Right Shift Register
• During the next four clock pulses … data is available at the serial output
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Shift Register with Inverted Feedback
Shift Register with Inverted Feedback
• 3-bit shift register with the Q1’ output from the last flip-flop fed back into the D input of the first flip-flop
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Shift Register with Inverted Feedback
• If initial state of the register is 000 … – Initial value of D3 is 1 … so
• After the first clock pulse … the register state is … 100 • Successive states are shown on the state graph • Note that states 010 and 101 are not in the loop
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Shift Register with Inverted Feedback
• If initial state of the register is 010 … – Initial value of D3 is 1 … so
• After the first clock pulse … the register state is … 101 • Successive states are shown on the state graph • We have a secondary loop on the state graph
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Shift Register with Inverted Feedback
• State Graphs for our 3-bit shift register …
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Shift Register
• Counter … – A circuit that cycles through a fixed sequence of states
• Johnson counter …
– A shift register with inverted feed back
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Lab
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LABS
• Lab #1 is available on the class web page
• Lab report criteria is available on the class web page
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Next Week …
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Next Week Topics
• Chapter 13 … Analysis of Clocked Sequential Circuits
• Pages 388 – 426
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Home Work
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Homework
1. Send me your UMS# (will be on your Access Card) so I can get access to BL-420 and EB-321 (computer labs), if you currently do not have access and require it
2. Read … – Chapter 13 … Analysis of Clocked Sequential Circuits
– Pages 388 – 426