logic gate inverter oscillators 1

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Special Feature C MOS inverters can be usefully con- figured as oscillators. For sinewave generation it is usual to specify unbuffered inverters, whilst for other waveforms it may be more convenient to use the buffered kind. Many CMOS NAND and NOR gates can be connected so as to also behave as inverters, and thus as oscillators. The aim of this article is to explain how inverter oscillators work and to give some simple design pointers. CMOS INVERTER The essentials of a typical single-stage CMOS inverter are shown in Fig.1. The heart of the circuit is formed around the two series-connected enhancement mode MOSFETs, TR1 and TR2, p-channel and n-channel respectively. The source (s) of TR1 is connected to the positive supply line (V CC ). TR2’s source is connected to the earthy (0V) side of the supply. The two drains (d) are con- nected together, as are the two gates (g). The whole configuration forms a comple- mentary push-pull amplifier. When used with digital signals, a suffi- ciently large positive input voltage turns TR2 on and TR1 off. The output is then low. An input voltage close to 0V takes the output high. It is unsafe to take the input more negative than about –0·5V as this can lead to damage of the chip. At the input of this circuit is a protec- tive resistance, R P (typically about 200 ohms), and (usually) two gate protection diodes, D1 and D2. An excessive input voltage turns on one of the diodes and R P then limits the current. There may also be two more protection diodes (D3 and D4) at the output. This stage, when used on its own, is known as an unbuffered inverter. BUFFERING In a buffered inverter, two more stages like this are added. The three-fold inver- sion gives the effect of a single inverter of much higher gain. The slope of the central portion of the input/output curve (Fig.2) is much steeper than a single inversion stage would produce. A digital input signal of high level makes the working point switch from P1 to P3, with a transition from P3 to P1 for a low level signal. There is a price to pay for this steeper operation. If a slowly changing input is applied, a point may be reached where all three inversion stages are biased to work- ing points such as that at P2. The overall gain is then very high and stray feedback can make the circuit jitter or oscillate. Also, random voltage variations (noise) mixed up with the input can make the cir- cuit turn on and off rapidly, giving an out- put like that at waveform B instead of the wanted one at waveform A. This is why single-stage (unbuffered) inverters are preferred for sine wave oscil- lators, where the input is not a repetitive series of high/low pulses, but a smoothly changing waveform and where, in order to set up the inverter, it is biased to a working point in the region of P2. DIODE CONDUCTION Diodes D1 and D2 are not meant to con- duct during normal operation. However, they may do so in oscillator circuits, with undesirable effects on the frequency. Fig.3 shows a common square wave oscillator circuit configuration known by various names, such as astable, relaxation oscilla- tor and multivibrator. LOGIC GATE INVERTER OSCILLATORS A compendium of practical oscillator circuits for the creative experimenter, all based on inverting logic gates. GEORGE HYLTON 684 Everyday Practical Electronics, June 2002 Fig.1. The essentials of a typical CMOS inverter, internal circuitry. Fig.2. Input/output voltage curve for the circuit in Fig.1. For oscillators, P2 represents a typical working point. Ideally, output pulses should be as shown in waveform A, but when buffered inverters are used they can have jitter, as illustrated in waveform B. Fig.3. A two-inverter oscillator, show- ing the effect of V CC on f o , with and without swamping resistance R P . Note that the frequency with Rp present is lower than the 50Hz obtained from the formula (see text). Part One

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Learn Logic Gate Inverter Oscillators

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  • CMOS inverters can be usefully con-figured as oscillators. For sinewavegeneration it is usual to specifyunbuffered inverters, whilst for otherwaveforms it may be more convenient touse the buffered kind. Many CMOSNAND and NOR gates can be connectedso as to also behave as inverters, and thusas oscillators.

    The aim of this article is to explain howinverter oscillators work and to give somesimple design pointers.

    The essentials of a typical single-stage

    CMOS inverter are shown in Fig.1. Theheart of the circuit is formed around thetwo series-connected enhancement modeMOSFETs, TR1 and TR2, p-channel andn-channel respectively.

    The source (s) of TR1 is connected tothe positive supply line (VCC). TR2ssource is connected to the earthy (0V) sideof the supply. The two drains (d) are con-nected together, as are the two gates (g).The whole configuration forms a comple-mentary push-pull amplifier.

    When used with digital signals, a suffi-ciently large positive input voltage turnsTR2 on and TR1 off. The output is thenlow. An input voltage close to 0V takes the

    output high. It is unsafe to take the inputmore negative than about 05V as this canlead to damage of the chip.

    At the input of this circuit is a protec-tive resistance, RP (typically about 200ohms), and (usually) two gate protectiondiodes, D1 and D2. An excessive inputvoltage turns on one of the diodes and RPthen limits the current. There may alsobe two more protection diodes (D3 andD4) at the output. This stage, when usedon its own, is known as an unbufferedinverter.

    In a buffered inverter, two more stages

    like this are added. The three-fold inver-sion gives the effect of a single inverter ofmuch higher gain. The slope of the centralportion of the input/output curve (Fig.2) ismuch steeper than a single inversion stagewould produce. A digital input signal ofhigh level makes the working point switchfrom P1 to P3, with a transition from P3 toP1 for a low level signal.

    There is a price to pay for this steeperoperation. If a slowly changing input is

    applied, a point may be reached where allthree inversion stages are biased to work-ing points such as that at P2. The overallgain is then very high and stray feedbackcan make the circuit jitter or oscillate.

    Also, random voltage variations (noise)mixed up with the input can make the cir-cuit turn on and off rapidly, giving an out-put like that at waveform B instead of thewanted one at waveform A.

    This is why single-stage (unbuffered)inverters are preferred for sine wave oscil-lators, where the input is not a repetitiveseries of high/low pulses, but a smoothlychanging waveform and where, in order toset up the inverter, it is biased to a workingpoint in the region of P2.

    Diodes D1 and D2 are not meant to con-

    duct during normal operation. However,they may do so in oscillator circuits, withundesirable effects on the frequency. Fig.3shows a common square wave oscillatorcircuit configuration known by variousnames, such as astable, relaxation oscilla-tor and multivibrator.

    684 Everyday Practical Electronics, June 2002

    Fig.1. The essentials of a typicalCMOS inverter, internal circuitry.

    Fig.2. Input/output voltage curve forthe circuit in Fig.1. For oscillators, P2represents a typical working point.Ideally, output pulses should be asshown in waveform A, but whenbuffered inverters are used they canhave jitter, as illustrated in waveform B.

    Fig.3. A two-inverter oscillator, show-ing the effect of VCC on fo, with andwithout swamping resistance RP. Notethat the frequency with Rp present islower than the 50Hz obtained from theformula (see text).

    Part One

  • Graph curve A shows the effect on fre-quency of changing the supply voltageVCC. Part of the change in frequency is theresult of protection diode conduction. Theeffect can be reduced by connecting a largeextra protection resistance RP in serieswith the input at A1. Curve B shows thechange produced by increasing RP to 10megohms.

    The extent to which a swamping resis-tance like RP improves stability, or fre-quency accuracy, depends on how muchbigger it is than the normal timing resis-tance, RT. Note, however, that diodeconduction is not the only influence onfrequency stability. The output resis-tances of Al and A2, which are effective-ly in series with RT and CT respectivelyalso affect timing, and they change withVCC.

    It is also necessary to be aware thatincreasing the value of Rp will reduce theoscillation frequency. This is due to the CRconstant of this resistor in conjunctionwith the inverters input capacitanceaffecting the circuits principal time con-stant, determined by RT and CT.

    Frequency can be adjusted by changingCT or RT. This resistance also sets up thed.c. conditions; with CT disconnected (nooscillation) negative feedback from A1output to input via RT sets the workingpoint to about that at P2 in Fig.2.

    A capacitor C charging from a d.c. volt-

    age source through a resistance R acquiresa charge voltage which builds up, at firstrapidly, and then ever more slowly as thecharge accumulates. Theoretically, C takesfor ever to charge right up to the sourcevoltage.

    However, the charge reaches 63 per centof the source voltage after a time of C Rseconds, known as the time constant CR,where C is in farads and R is in ohms.More conveniently, C can be in micro-farads and R in megohms. Thus a capaci-tor of 1F charged through 1M becomescharged to 63 per cent of the applied volt-age after one second.

    In relaxation oscillators, such as thatshown in Fig.3, the circuit changes stateabruptly when the charge on C reaches theA1 inverters critical threshold level, atabout point P2 in Fig.2. At this point, theinverter whose output has been highswitches to give a low output, and viceversa.

    Capacitor C then discharges and whenits voltage has decreased below the criticallevel, the circuit resets to its original state,and so on. If the charging and dischargingthreshold voltages are equal and the resis-tance is constant, the circuit generates rec-tangular waves with half cycles of equalduration, i.e. square waves.

    In Fig.3, the time constant CR is 001second (01M 01F). Consequently,the charge and discharge periods each take001 seconds, therefore one complete cycletakes 002 seconds. Using the period tofrequency conversion formula fo = 1/2CR,the frequency is thus 1/(2 001) = 50Hz.

    It should be noted, though, that CR mayalso be affected by other stray R and C val-ues within the circuit. As stated earlier, itcan also be affected by differences in sup-ply voltage, and by the value of RP.

    up to 15V (18V for some manufacturers).Modern high speed equivalents, suchas the 74HC04, are restricted to a maxi-mum VCC of 6V. They may also drawmore current when biased for oscillatoruse.

    As illustrated in Fig.2, jitter can occur

    when a normal inverters input voltage isat around the P2 level. To inhibit the jitterpossible with slowly-changing inputs,CMOS inverters having a snap action,and known as Schmitt trigger inverters,can be used.

    With these a slowly rising input voltagehas no effect until an upper critical (thresh-old) value is reached. Then the high outputflips abruptly to the low condition. If theinput is then reduced slightly the outputremains low.

    Not until the input is lowered by a fair-ly substantial amount, to below the lowerthreshold level, does the output flip back tothe high state. This backlash (hysteresis)prevents the output from jittering whenthere is noise mixed up with the inputsignal.

    Schmitt trigger inverters can cope withsignals arriving via long cables whosecapacitance slows the rate of rise or fall of

    Everyday Practical Electronics, September 2002 685

    However, as an approximation the formulacan be used to determine the likely frequencyto be produced. It can also be re-arranged sothat for a given frequency, the required valuesfor C and R can be calculated.

    Thus if R is known, to find the value ofC required for frequency fo, the formula isrearranged to become:

    C = 1/(2 fo R)To find R when C is known, it becomes:R = 1/(2 fo C)If the product RC is megohms times

    microfarads the frequency is in Hertz. Youcan increase the units of R to 10M and cor-respondingly reduce those of C to 01uF(100nF) and still get fo in Hz. In other words,if the units of R increase then those of Cdecrease by the same factor to get the sameunits of fo. You can get fo in kilohertz by hav-ing R in kilohms and C in microfarads orwith R in megohms and C in nanofards.

    You should also be aware that the actualvalues for the components used as C and Rare subject to manufacturing tolerances. Toadjust the oscillator frequency to that actu-ally required, a variable resistor (i.e. poten-tiometer) can be inserted as in Fig.4.

    We have assumed in the foregoing dis-

    cussion that the oscillator output is asquare wave whose peak-to-peak voltageis close to VCC. Because of differencesbetween the MOSFETs manufactured intothe CMOS inverter, the positive-goinghalf-cycles may have slightly differentdurations to those of the negative-goinghalf-cycles. They are said to have a differ-ent mark-space ratio.

    If necessary, the mark-space ratio can beequalised with the aid of an adjustment cir-cuit, such as that in Fig.5. In this case CR iscalculated as C (R1 + (VR1/2)), althoughthe presence of D1 and D2 will modify theratio, typically reducing the frequency dueto the charge/discharge voltage having beenreduced by about 07V.

    A reasonable rule of thumb formula isshown in Fig.5.

    To provide a wide spread for the mark-space ratio, the value of R1 should be keptsmall in relation to the value of VR1.

    Standard CMOS inverters, such as the

    4069 hex inverter, can be used with VCC

    Fig.4. Frequency adjustment is provid-ed by VR1. The ratio of maximum tominimum frequency can exceed 10 inlow-frequency oscillators where C andVR1 are large. Frequency adjustmenthas little effect on the mark-spaceratio.

    Fig.5. Mark-space adjustment is pro-vided by VR1. When D1 conducts theeffective resistance is R1 plus sectiona of VR1. When D2 conducts it is R1plus VR1 section b. Thus the chargeand discharge of C can be adjusteddifferentially. If a wide range of controlis needed R1 can approach zeroohms.

    Fig.6. A Schmitt trigger inverter squarewave oscillator which uses the mini-mum of components.

    c

  • a pulse and which may pick up noise orinterference.

    Buffered Schmitt devices such as the74HC14 hex inverter make good oscilla-tors whose output waveform is very closeto a square wave (Fig.6). The slight differ-ence in the mark-space ratio which may beobtained is dependent upon the Schmitttriggers precise upper and lower thresholdlevels.

    The only external components neededare a resistor and a capacitor. These act asa kind of integrator which turns the squarewave at the output into a triangular wave atthe input. This has a lower amplitude (typ-ically about 1V peak-to-peak for a 5V sup-ply) than the square wave and is too smallto turn on the protection diodes, conse-quently no swamping resistance is needed.

    In a typical Schmitt inverter with VCC =5V the circuit changes state when the inputvoltage rises to about +3V or falls to about+2V. Since the d.c. average voltage on C is25V (VCC/2) changes in input voltage of05V are all that is needed to flip the circuitfrom one state to the other.

    The difference between the two criticalthreshold voltages is called the hysteresisvoltage. For the 74HC14 inverter this istypically quoted on data sheets as 05V forVCC = 2V, 08V for VCC = 45V and 095Vfor VCC = 6V.

    Oscillation frequency is determined byhow long it takes for these changes of inputvoltage to occur after a switch of outputfrom high to low, or low to high. Since therequired changes are only around one fifthof VCC the time to produce them is rela-tively smaller than with the oscillators dis-cussed so far.

    The result is that the frequency is muchhigher than might be expected from thebasic RC time constant. It is roughly 2/RC,but this is only an approximation since it isalso affected by the supply voltage and theresulting hysteresis thresholds.

    The triangle waveform at the junction ofC and R can be tapped by using an op.ampbuffer, as shown in the dotted box of Fig.6.

    It is also possible to vary the mark-spaceratio of the oscillator by using the diodeand potentiometer configuration shown inFig.5. This also has the effect of changingthe triangle waveform to a rising or fallingramp (sawtooth).

    Another method of yielding sawtooth

    and pulse waveforms is shown in Fig.7, inwhich C is discharged via transistor TR1 assoon as the output of A2 goes high. The

    discharge of C causes the output of A2 togo low again, turning off TR1, whereuponC starts to charge up again and the processis repeated.

    The discharge of C is very rapid and,almost immediate, but during the dischargeof C there is a very short negative-goingpulse at A1 output and a correspondingpositive-going pulse at A2 output. Thewaveform at C is effectively a rising ramp.

    The sawtooth amplitude is about VCC/2

    and the rising of its slope is not linear.Linearity can be improved by substituting aconstant current source for R. This can bemade easier by taking advantage of the factthat the circuit still works if the top end ofR is connected to +VCC instead of A1 out-put, as shown in Fig.8.

    There is, however, another problem. Thefrequency of the sawtooth is only abouthalf that of the original triangular wave.The frequency can be increased by pre-venting C from discharging completelythrough TR1. With less recharging to bedone the cycle speeds up.

    In Fig.8 the speeding up is done by con-necting two diodes in the emitter (e) ofTR1. These make TR1 turn off before C isfully discharged. The inclusion of resistorRx (of 1k, say) prevents damaging cur-rent flow from A2 output through the base-emitter path of TR1.

    With VCC at +5V the sawtooth frequen-cy will typically be about the same as theoriginal triangle wave frequency and thetwo amplitudes will also be similar.Linearity is improved, too.

    Oscillators can usually be considered as

    amplifiers with positive feedback. Thefeedback increases gain and if there isenough of it, the gain becomes infinite.Then any noise at the input is amplified byas much as the circuit will allow. In prac-tice this means that the amplitude builds upuntil the system overloads. This reducesgain and stops any further increase.

    In a sine wave oscillator, the positivefeedback is channeled from output toinput through some sort of filter whichpermits the greatest feedback at one par-ticular frequency. This is the oscillationfrequency.

    Since, in an inverter, a positive input

    voltage results in a negative output volt-age an inverter should not oscillate iffeedback is taken directly from output toinput. Such feedback is negative andreduces gain.

    Most CMOS sine wave oscillators doincorporate feedback from output to input,but only at d.c. The feedbacks job is to setthe working point on the linear part of theinput/output curve and so establish theright starting conditions.

    To permit a.c. oscillation, some arrange-ment must be incorporated to create asecond phase reversal at the oscillation fre-quency. The two successive inversions(positive to negative, negative to positive)make feedback positive at the oscillationfrequency.

    One way of providing a second phaseinversion is to pass signals through a sec-ond inverter (but note that this will notwork with Schmitt inverters). This entails arisk, though: if feedback occurs at d.c. theworking point may be de-stabilised. Theresult (latchup) leaves all the inverterseither hard on or hard off (high or low),preventing a.c. oscillation. Also, if theoverall feedback is over a wide band of fre-quencies, the circuit may oscillate at anunintended frequency.

    Ways of avoiding these dangers will becovered later. For the present, lets look atother methods of obtaining a second phaseinversion.

    One method is to use a transformer. Ifthe inverter output is applied to a primarywinding, the secondary winding yields acopy, scaled up or down in voltage accord-ing to the turns ratio. The secondarywinding is electrically isolated from theprimary.

    To make an oscillator, we choose the endof the transformer secondary windingwhich provides a voltage having theopposite polarity to the inverters outputvoltage. This gives the required secondinversion.

    A practical version, shown in Fig.9,

    incorporates a feedback adjuster, VR1,which can be set to control the strength ofoscillation. In general, a setting which isjust sufficient to ensure reliable oscillationgives the best waveform.

    Fig.7. Sawtooth oscillator created byrapidly discharging C via TR1.

    Fig.8. Linearising a sawtooth waveform.

    Fig.9 Using a transformer to producephase inversion.

    686 Everyday Practical Electronics, September 2002

  • The frequency is determined by capaci-tor C1 and winding Ls. Capacitor C2merely provides a bypass (decoupling)capacitance, and its presence ensures thatthere is d.c. negative feedback to stabilizethe operating conditions.

    A pure sine wave appears across Ls/C1.A distorted (peaks flattened) waveformappears at the inverter output but it can bemade almost sinusoidal by careful settingof VR1.

    The turns ratio depends on both thetransconductance (g) of the inverter andthe dynamic resistance (Rd) of the LCcombination. The effect of the trans-former is to reduce the impedance seenlooking into the coupling winding fromthe inverter output to Rd/N2, where N isthe ratio of the turns on Ls to the turns onthe coupling winding.

    To design an oscillator, first assumeVR1 = 0 then calculate the turns ratiowhich will just allow oscillation. For thisN = (g Rd). In this type of oscillator,the working point will be on the linearpart of the characteristic, i.e. P2. Bothf.e.t.s are on and g is the sum of theirtransconductances.

    To take an example, if g = 3ms and Rd =100k, N is 3/1000 100,000 = 300. Toallow for adjustment and device spreads alower turns ratio is chosen. The best valueof VR1 is best found by experiment but isusually a few times the output resistance ofthe inverter; try a 100k preset.

    The correct setting of VR1 should givereliable oscillation in the face of any likelysupply-voltage variations. When set upcorrectly the level of signal at the input islow enough to ensure that the protectiondiodes never conduct. Hence Rp is notneeded. This is important when frequencystability must be maximised because bothRp and input capacitance are temperature-dependent.

    In any oscillator the amplitude in-

    creases until something stops it. In CMOS

    oscillators the limiting mechanism is peakflattening as the signals become largeenough to be affected by the nonlinearityof the transfer characteristic. If VR1 is lowenough to allow strong oscillation the out-put approaches a square wave.

    If VR1 is set for just oscillating theoutput is a sine wave except for slight peakcrushing. The waveform across the LCitself can still be a good sinewave evenwhen the output is crushed because theharmonics produced by crushing are atten-uated by the LC circuit. With symmetricalcrushing the main harmonic is the third andthis is well away from the peak of the LCresonance curve.

    When VR1 is set for strong oscillationthe peak-to-peak output approaches VCC.The level across the LC is normally muchlower. The signal across the couplingwinding is a good sine wave but only oneNth of the amplitude at the LC. To extractthe full LC signal without upsetting circuitoperation calls for a buffer, such as thef.e.t. follower in Fig.9.

    Transformers are often inconvenient.

    Designers may prefer to use a simpleinductor without a secondary winding or

    tappings. In this case the required secondinversion can be performed by the tuningcomponents themselves.

    In the usual arrangement shown inFig.10, the two capacitances C1 and C2,together with inductance L, form a pi-net-work. This inverts the voltage at one spe-cific frequency, that at which the reactanceof L is the same as the reactance of C1 andC2 in series.

    Oscillation may well be violent and thewaveform poorly shaped. Adding a feed-back-control resistance, VR1, provides athrottle control to adjust the oscillationlevel. Then the waveform at the inverteroutput is peak-clipped but good sine wavesare obtainable across the capacitors.Because of the network phase inversion,waveform voltages V1 and V2 are inantiphase. If C1 = C2 (the usual case), theamplitudes of V1 and V2 are equal, butopposite.

    This oscillator is a version of a classicalone, the Colpitts oscillator. It is easy to getit oscillating. The requirement is that theinverter should produce a gain of over onewhen driving the impedance looking intothe pi-network.

    With C1 = C2, this impedance is a quar-ter of the dynamic resistance of the tuningcircuit at the oscillation frequency. In mostpractical cases, this impedance is morethan high enough and VR1 is needed tolimit amplitude and ensure good wave-forms. The value of VR1 is not critical.Even if the resistance is considerably lessthan the maximum possible, the wave-forms can still be good.

    At radio frequencies, the Colpitts circuitcan be tuned by a two-gang variable capac-itor in place of C1 and C2, with the rotorearthed. A tuning range (ratio of maximumto minimum frequency) in excess of threeis usually obtainable. The range is limitedby the practical tuning capacitors available,where fmax/fmin = Cmax/Cmin = about 10in a circuit with typical stray capacitance.

    To be concluded next month.

    Fig.10 Colpitts oscillator. Phase inver-sion at the oscillating frequency iscreated by the pi-network C1, L, C2.

    Everyday Practical Electronics, September 2002 687

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