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TRANSCRIPT
LOGIC GATES
Ho Kyung Kim, Ph.D.
School of Mechanical Engineering
Pusan National University
Basic Experiment and Design of Electronics
Outline
• Boolean algebra
• Logic gates
• Karnaugh maps
2
• Analog signal
– An electric signal whose value varies in analogy with a physical quantity (e.g., temp., force, or acceleration)
– Sensitive to noise
• Digital signal
– Immune to noise
Analog and digital signals
3
Binary signal
• Characterized by transitions between two states (𝑓1/𝑓0, on/off, 5 V/0 V …)
• Knowledge of the transition between one state to another is equivalent to knowledge of the state Digital logic circuits can operate by detecting transitions (edges) between voltage levels
4
Binary number system
MSB
LSB
LSB
MSB
• bits = binary digits
– LSB (least significant bit), MSB (most significant bit)
– 8 bits = 1 byte
– 16 bits = 2 bytes = 1 word
• 3.2510 = 3 × 100 + 2 × 10−1 + 5 × 10−2
• 10.0112 = 1 × 21 + 0 × 20 + 0 × 2−1 + 1 × 2−2 + 1 × 2−3 = 2 + 0 + 0 +1
4+
1
8= 2.37510
• 3.2510 =?2• 28.37510 =?2
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Addition Subtraction
Multiplication Division
6
• Negative binary numbers
– +5 0101, -5 1101
– − 2𝑛−1 − 1 ≤ 𝑁 ≤ +(2𝑛−1 − 1) for 𝑛-bit signed integer words
– 𝑋 + −𝑌 instead of 𝑋 − 𝑌 in digital computers
• Complements
– Ones complement
• 𝑎 = 0101 ones complement of 𝑎 = 24 − 1 − 𝑎 = 1010
– Twos complement (= ones complement + 1)
• 𝑎 = 0101 ones complement of 𝑎 =24 − 𝑎 = 1011 (= 1010 + 1)
• Hexadecimal system
– 0, 1, 2, … , 9, A (= 10), B (= 11), C (= 12), D (= 13), E (= 14), F (= 15)
– B5F16 = 11 × 162 + 5 × 161 + 15 × 160 = 261110
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• Ex) Perform the following subtractions using the twos complement arithmetic
1. 𝑋 − 𝑌 = 1011100 − 1110010
2. 𝑋 − 𝑌 = 10101111 − 01110011
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Sol.)
1. 𝑋 − 𝑌 = 𝑋 + −𝑌 = 1011100 + 27 − 1110010 = 1011100 + 0001110 = 1101010Since 𝑋 − 𝑌 < 0, 𝑋 − 𝑌 = 𝟏1101010
2. 𝑋 − 𝑌 = 𝑋 + −𝑌 = 10101111 + 28 − 01110011 = 10101111 + 10001101 = 00111100Since 𝑋 − 𝑌 > 0, 𝑋 − 𝑌 = 𝟎00111100
• Binary codes
– BCD (binary-coded decimal)
• 13910 → 0001 0011 1001
• e.g., hand calculator
– Gray codes
• Any consecutive numbers differ only by 1 bit
• Effective in encoding mechanical angular position
BCD code Gray code
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Encoders
10
• Mathematics associated with the binary number system (and with the more general field of logic)
• Logical algebra
• Positive logic
– Logic 1 = true, logic 0 = false
• Negative logic
– Logic 1 = false, logic 0 = true
• Analysis of logic functions, that is, functions of logical (Boolean) variables, can be carried out in terms of truth tables
• Logic gates
– Physical devices that can be used to implement logic functions
Boolean algebra
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Logic gates: OR, AND, NOT
Logical addition Logical multiplication Logical complement
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VCC
VCERB
RC
VBB
A
B
F
+VCC
Input
OutputA
B
FInput
Output
13
• Ex) Realize the following statement with the logic gates:
– The output 𝑍 shall be logic 1 only when the condition (𝑋 = 1 AND 𝑌 = 1) OR (𝑊 = 1) occurs, and shall be logic 0 otherwise
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• Ex) Realize the following statement with the logic gates:
– The output 𝑍 shall be logic 1 only when the condition (𝑋 = 0 AND 𝑌 = 1) OR (𝑊 = 1) occurs, and shall be logic 0 otherwise
The output 𝑍 shall be logic 1 only when the condition ( 𝑋 = 1 AND 𝑌 = 1) OR (𝑊 = 1) occurs, and shall be logic 0 otherwise
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Rules of Boolean algebra
Proof of rule 16 by perfect induction (truth table)
0 ∙ 1 = 0 ⟺ 1+ 0 = 1 (duality)
From 2: 𝐴 + 𝐵 ∙ 𝐶 + 1 = 1 From 17: 𝐴 + 𝐵 ∙ 𝐴 + 𝐶 ∙ 𝐷 = 𝐴 + 𝐵 ∙ 𝐶 ∙ 𝐷
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• De Morgan’s theorems
– (𝑋 + 𝑌) = 𝑋 ∙ 𝑌
– (𝑋 ∙ 𝑌) = 𝑋 + 𝑌
– Any logic gates can be implemented by using only OR and NOT gates, or only AND and NOT gates
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NOR NAND
• Ex) Simplify the following functions
– 𝑓 𝐴, 𝐵, 𝐶, 𝐷 = 𝐴 ∙ 𝐵 ∙ 𝐷 + 𝐴 ∙ 𝐵 ∙ 𝐷 + 𝐵 ∙ 𝐶 ∙ 𝐷 + 𝐴 ∙ 𝐶 ∙ 𝐷
Sol.)
𝑓 = 𝐴 ∙ 𝐷 ∙ ( 𝐵 + 𝐵) + 𝐵 ∙ 𝐶 ∙ 𝐷 + 𝐴 ∙ 𝐶 ∙ 𝐷𝑓 = 𝐴 ∙ 𝐷 + 𝐵 ∙ 𝐶 ∙ 𝐷 + 𝐴 ∙ 𝐶 ∙ 𝐷𝑓 = ( 𝐴 + 𝐴 ∙ 𝐶) ∙ 𝐷 + 𝐵 ∙ 𝐶 ∙ 𝐷𝑓 = ( 𝐴 + 𝐶) ∙ 𝐷 + 𝐵 ∙ 𝐶 ∙ 𝐷𝑓 = 𝐴 ∙ 𝐷 + 𝐶 ∙ 𝐷 + 𝐵 ∙ 𝐶 ∙ 𝐷𝑓 = 𝐴 ∙ 𝐷 + (1 + 𝐵) ∙ 𝐶 ∙ 𝐷𝑓 = 𝐴 ∙ 𝐷 + 𝐶 ∙ 𝐷𝑓 = ( 𝐴 + 𝐶) ∙ 𝐷
Rule 4
Rule 18
Rule 2
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• Ex) Realize the logic function described by the truth table below
00001111
00110011
01010101
01011111
Sol.)
𝑦 = 𝐴 ∙ 𝐵 ∙ 𝐶 + 𝐴 ∙ 𝐵 ∙ 𝐶 + 𝐴 ∙ 𝐵 ∙ 𝐶 + 𝐴 ∙ 𝐵 ∙ 𝐶 + 𝐴 ∙ 𝐵 ∙ 𝐶 + 𝐴 ∙ 𝐵 ∙ 𝐶𝑦 = 𝐴 ∙ 𝐶 ∙ 𝐵 + 𝐵 + 𝐴 ∙ 𝐵 ∙ 𝐶 + 𝐶 + 𝐴 ∙ 𝐵 ∙ ( 𝐶 + 𝐶)𝑦 = 𝐴 ∙ 𝐶 + 𝐴 ∙ 𝐵 + 𝐴 ∙ 𝐵𝑦 = 𝐴 ∙ 𝐶 + 𝐴 ∙ ( 𝐵 + 𝐵)𝑦 = 𝐴 ∙ 𝐶 + 𝐴𝑦 = 𝐴 + 𝐶
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• NAND = NOT AND
• NOR = NOT OR
Logic gates: NAND, NOR, XOR
Just regard this “bubble” as the “NOT” gate
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• AND function with NAND gates
0011
0101
1110
0001
21
• Realization of various logic gates with only NAND gates
Inverter
AND
OR
NOR
22
• AND function with NOR gates
– 𝑓 = 𝑓 = 𝐴 ∙ 𝐵 = 𝐴 + 𝐵
23
• Realization of various logic gates with only NOR gates
Inverter
AND
OR
NOR
24
• XOR (exclusive OR) gate
– When its inputs are all logic 1’s, the output is exclusively a logic 0; otherwise, identical to the OR gate
– 𝑍 = 𝑋⨁𝑌 = (𝑋 + 𝑌) ∙ (𝑋 ∙ 𝑌)
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Summary
게이트 이름 회로기호 논리식 진리표
AND
x y
0 0
0 1
1 0
1 1
F
0
0
0
1
F = xy
F = x+y
x y
0 0
0 1
1 0
1 1
F
0
1
1
1
x
0
1
F
1
0
F = x'
x
yF
x
yF
x
y
x
y
x
y
x
y
F
F
F
F
F
F
x
x
XNOR(exclusive-NOR)
또는equivalence
OR
NOT또는
inverter
buffer
NAND
NOR
XOR(exclusive-OR)
x
0
1
F
0
1
F = x
x y
0 0
0 1
1 0
1 1
F
1
1
1
0
F = (xy)'
F = (x+y)'
x y
0 0
0 1
1 0
1 1
F
1
0
0
0
x y
0 0
0 1
1 0
1 1
F
0
1
1
0
x y
0 0
0 1
1 0
1 1
F
1
0
0
1
비고
입력이 모두 1일때 출력이 1
입력중 하나라도 1이면 출력이 1
입력이 반전되어 출력
입력이 그대로 출력
입력이 모두 1일때에만 출력이 0
입력이 모두 0일때에만 출력이 1
입력에 1이 홀수개일때 출력이 1
입력에 0이 짝수개일때 출력이 1
F = (x y)'F = x'y'+xy
F = x yF = x'y + xy'
게이트 이름 회로기호 논리식 진리표
AND
x y
0 0
0 1
1 0
1 1
F
0
0
0
1
F = xy
F = x+y
x y
0 0
0 1
1 0
1 1
F
0
1
1
1
x
0
1
F
1
0
F = x'
x
yF
x
yF
x
y
x
y
x
y
x
y
F
F
F
F
F
F
x
x
XNOR(exclusive-NOR)
또는equivalence
OR
NOT또는
inverter
buffer
NAND
NOR
XOR(exclusive-OR)
x
0
1
F
0
1
F = x
x y
0 0
0 1
1 0
1 1
F
1
1
1
0
F = (xy)'
F = (x+y)'
x y
0 0
0 1
1 0
1 1
F
1
0
0
0
x y
0 0
0 1
1 0
1 1
F
0
1
1
0
x y
0 0
0 1
1 0
1 1
F
1
0
0
1
비고
입력이 모두 1일때 출력이 1
입력중 하나라도 1이면 출력이 1
입력이 반전되어 출력
입력이 그대로 출력
입력이 모두 1일때에만 출력이 0
입력이 모두 0일때에만 출력이 1
입력에 1이 홀수개일때 출력이 1
입력에 0이 짝수개일때 출력이 1
F = (x y)'F = x'y'+xy
F = x yF = x'y + xy'
게이트 이름 회로기호 논리식 진리표
AND
x y
0 0
0 1
1 0
1 1
F
0
0
0
1
F = xy
F = x+y
x y
0 0
0 1
1 0
1 1
F
0
1
1
1
x
0
1
F
1
0
F = x'
x
yF
x
yF
x
y
x
y
x
y
x
y
F
F
F
F
F
F
x
x
XNOR(exclusive-NOR)
또는equivalence
OR
NOT또는
inverter
buffer
NAND
NOR
XOR(exclusive-OR)
x
0
1
F
0
1
F = x
x y
0 0
0 1
1 0
1 1
F
1
1
1
0
F = (xy)'
F = (x+y)'
x y
0 0
0 1
1 0
1 1
F
1
0
0
0
x y
0 0
0 1
1 0
1 1
F
0
1
1
0
x y
0 0
0 1
1 0
1 1
F
1
0
0
1
비고
입력이 모두 1일때 출력이 1
입력중 하나라도 1이면 출력이 1
입력이 반전되어 출력
입력이 그대로 출력
입력이 모두 1일때에만 출력이 0
입력이 모두 0일때에만 출력이 1
입력에 1이 홀수개일때 출력이 1
입력에 0이 짝수개일때 출력이 1
F = (x y)'F = x'y'+xy
F = x yF = x'y + xy'
26
• Sum-of-products expression
Standard forms
• Product-of-sums expression
• Any logical expression can be reduced to one of these two forms!
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• Sum-of-products
– OR of minterms
– 𝐹 = 𝑋 𝑌 𝑍 + 𝑋𝑌 𝑍 + 𝑋 𝑌𝑍 + 𝑋𝑌 𝑍
• Products-of-sums
– AND of maxterms
– 𝐹 = (𝑋 + 𝑌 + 𝑍)(𝑋 + 𝑌 + 𝑍)( 𝑋 + 𝑌 + 𝑍)( 𝑋 + 𝑌 + 𝑍)
𝑋 𝑌 𝑍 𝐹 Minterm Maxterm
00001111
00110011
01010101
10100110
𝑋 𝑌 𝑍
𝑋𝑌 𝑍
𝑋 𝑌𝑍𝑋𝑌 𝑍
𝑋 + 𝑌 + 𝑍
𝑋 + 𝑌 + 𝑍 𝑋 + 𝑌 + 𝑍
𝑋 + 𝑌 + 𝑍
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Karnaugh maps and logic designs
• Karnaugh map
– Describing all possible combinations of the 𝑁 variables present in the logic function of interest
– Arranging variables in a 1-bit change between adjacent terms
– 2𝑁 cells
– Minterm in each cell
• AND-combination of the 𝑁 variables in either uncomplemented or complemented form
• Product of the variables appearing at the corresponding vertical and horizontal coordinates
– Define a subcube with logical value
• 1 cell
• 2 cells = pair
• 4 cells = quad
• 8 cells = octet
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• 1 cell
– 𝑓 = 𝑊 ∙ 𝑋 ∙ 𝑌 ∙ 𝑍 + 𝑊 ∙ 𝑋 ∙ 𝑌 ∙ 𝑍 + 𝑊 ∙ 𝑋 ∙ 𝑌 ∙ 𝑍 +𝑊 ∙ 𝑋 ∙ 𝑌 ∙ 𝑍 +𝑊 ∙ 𝑋 ∙ 𝑌 ∙ 𝑍 + 𝑊 ∙ 𝑋 ∙ 𝑌 ∙ 𝑍+𝑊 ∙ 𝑋 ∙ 𝑌 ∙ 𝑍
• 2 cells
– 𝑓 = 𝑊 ∙ 𝑋 ∙ 𝑌 + 𝑊 ∙ 𝑌 ∙ 𝑍 + 𝑋 ∙ 𝑌 ∙ 𝑍 +𝑊 ∙ 𝑋 ∙ 𝑌 ∙ 𝑍 + 𝑊 ∙ 𝑋 ∙ 𝑌 ∙ 𝑍+𝑊 ∙ 𝑋 ∙ 𝑌 ∙ 𝑍
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• 4 cells
– 𝑓 = 𝑊 ∙ 𝑋 +𝑊 ∙ 𝑍 + 𝑋 ∙ 𝑍
• 8 cells
– 𝑓 = 𝑍
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• Ex) Simplify the following logic circuit
X
Y
Z
F
Y
FX
Z
00 01 11 10
0 1 0 0 1
1 1 1 1 1
YZX
𝑓 = 𝑋 + 𝑌 𝑍 + 𝑌 𝑍 = 𝑋 + 𝑌 + 𝑌 𝑍 = 𝑋+ 𝑍
32
• Ex) Design a logic circuit that implements the following truth table
– 𝑦 = 𝐴 ∙ 𝐵 ∙ 𝐷 + 𝐵 ∙ 𝐶 + 𝐶 ∙ 𝐷 + 𝐴 ∙ 𝐷
Sum-of-products realizations
33
• Ex) Derive the truth table and minimum sum-of-products expression for the following circuit
– 𝑓 = 𝑥 ∙ 𝑦 + 𝑦 ∙ 𝑧
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1. Solve for the 0’s exactly as for the 1’s in sum-of-products expressions
2. Complement the resulting expression
Product-of-sums realization
• Product-of-sums
– 𝑓 = 𝑥 ∙ 𝑦 ∙ 𝑧 + 𝑥 ∙ 𝑦 = 𝑥 ∙ 𝑦 ∙ 𝑧 ∙ 𝑥 ∙ 𝑦
– 𝑓 = (𝑥 + 𝑦 + 𝑧) ∙ ( 𝑥 + 𝑦)
• Sum-of-products
– 𝑓 = 𝑥 ∙ 𝑦 + 𝑦 ∙ 𝑧 + 𝑥 ∙ 𝑦
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𝑥 ∙ 𝑧
• Use the don’t care entry with 𝒙 whenever it does not matter whether a position in the K-map is filled by a 1 or a 0
• Then, 𝒙 can be used as either a 1 or a 0, depending on which results in a greater simplification (i.e., helps in forming the smallest number of maximal subcubes)
Don’t care conditions
• If 𝒙 =1 in the right truth table;
– 𝑓 = 𝐵 ∙ 𝐷 + 𝐵 ∙ 𝐶 + 𝐴 ∙ 𝐶 ∙ 𝐷
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