logika kombinasi
TRANSCRIPT
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EE207: Digital Systems I, EE207: Digital Systems I, Semester I 2003/2004Semester I 2003/2004
CHAPTER 3 CHAPTER 3 --ii:ii:Combinational Logic Design Combinational Logic Design ––
Design Procedure, Encoders/DecodersDesign Procedure, Encoders/Decoders(Sections 3.4 (Sections 3.4 –– 3.6)3.6)
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30-Apr-09 2Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
OverviewOverviewnn Design ProcedureDesign Procedurenn Code ConvertersCode Convertersnn Binary DecodersBinary Decoders
nn ExpansionExpansionnn Circuit implementationCircuit implementation
nn Binary EncodersBinary Encodersnn Priority EncodersPriority Encoders
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30-Apr-09 3Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Combinational Circuit DesignCombinational Circuit Design
nn DesignDesign of a combinational circuit is the of a combinational circuit is the development of a circuit from a development of a circuit from a description of its function.description of its function.
nn Starts with a problem specification and Starts with a problem specification and produces a logic diagram or set of produces a logic diagram or set of boolean equations that represent the boolean equations that represent the circuit.circuit.
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30-Apr-09 4Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Design ProcedureDesign Procedure1.1. Determine the required number of inputs Determine the required number of inputs
and outputs and assign variables to them.and outputs and assign variables to them.2.2. Derive the truth table that defines the Derive the truth table that defines the
required relationship between inputs and required relationship between inputs and outputs.outputs.
3.3. Obtain and Obtain and simplifysimplify the Boolean function (Kthe Boolean function (K--maps, algebraic manipulation, CAD tools, maps, algebraic manipulation, CAD tools, ……). ). Consider any design constraints (area, delay, Consider any design constraints (area, delay, power, available libraries, etc).power, available libraries, etc).
4.4. Draw the logic diagram.Draw the logic diagram.5.5. VerifyVerify the correctness of the design.the correctness of the design.
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30-Apr-09 5Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Design ExampleDesign Example
nn Design a combinational circuit with 4 Design a combinational circuit with 4 inputs that generates a 1 when the # of inputs that generates a 1 when the # of 1s equals the # of 0s. Use only 21s equals the # of 0s. Use only 2--input input NOR gatesNOR gates
……
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30-Apr-09 6Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
More Examples More Examples -- Code ConvertersCode Converters
nn Code Converters transform/convert Code Converters transform/convert information from one code to another:information from one code to another:nn BCDBCD--toto--ExcessExcess--3 Code Converter3 Code Converter
nn Useful in some cases for digital arithmeticUseful in some cases for digital arithmeticnn BCDBCD--toto--SevenSeven--Segment ConverterSegment Converter
nn Used to display numeric info on 7 segment Used to display numeric info on 7 segment displaysdisplays
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30-Apr-09 7Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
BCDBCD--toto--ExcessExcess--3 Code Converter3 Code Converter
nn Design a circuit that converts a binaryDesign a circuit that converts a binary--codedcoded--decimal (BCD) codeword to its decimal (BCD) codeword to its corresponding excesscorresponding excess--3 codeword.3 codeword.
nn ExcessExcess--3 code: Given a decimal digit 3 code: Given a decimal digit nn, its , its corresponding excesscorresponding excess--3 codeword 3 codeword (n+3)(n+3)22Example: Example:
n=5 n=5 àà n+3=8 n+3=8 àà 10001000excessexcess--33n=0 n=0 àà n+3=3 n+3=3 àà 00110011excessexcess--33nn We need 4 input variables (A,B,C,D) and 4 We need 4 input variables (A,B,C,D) and 4
output functions W(A,B,C,D), X(A,B,C,D), output functions W(A,B,C,D), X(A,B,C,D), Y(A,B,C,D), and Z(A,B,C,D).Y(A,B,C,D), and Z(A,B,C,D).
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30-Apr-09 8Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
BCDBCD--toto--ExcessExcess--3 Converter (cont.)3 Converter (cont.)nn The truth table relating the input and output variables is shownThe truth table relating the input and output variables is shown below.below.nn Note that the outputs for inputs 1010 through 1111 are Note that the outputs for inputs 1010 through 1111 are don't caredon't cares (not s (not
shown here).shown here).
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30-Apr-09 9Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Maps for BCD-to-Excess-3 Code Converter
The KThe K--maps for are constructed using the don't care termsmaps for are constructed using the don't care terms
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30-Apr-09 10Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
BCDBCD--toto--ExcessExcess--3 Converter (cont.)3 Converter (cont.)
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30-Apr-09 11Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Another Code Converter Example:Another Code Converter Example:BCDBCD--toto--SevenSeven--Segment ConverterSegment Converter
nn SevenSeven--segment display:segment display:nn 7 LEDs (light emitting diodes), each one 7 LEDs (light emitting diodes), each one
controlled by an inputcontrolled by an inputnn 1 means “on”, 0 means “off”1 means “on”, 0 means “off”nn Display digit “3”?Display digit “3”?
nn Set a, b, c, d, g to 1Set a, b, c, d, g to 1nn Set e, f to 0Set e, f to 0
d
a
b
c e
f g
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30-Apr-09 12Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
BCDBCD--toto--SevenSeven--Segment ConverterSegment Converter
nn Input is a 4Input is a 4--bit BCD code bit BCD code àà 4 inputs (w, 4 inputs (w, x, y, z).x, y, z).
nn Output is a 7Output is a 7--bit code (a,b,c,d,e,f,g) that bit code (a,b,c,d,e,f,g) that allows for the decimal equivalent to be allows for the decimal equivalent to be displayed.displayed.
nn Example: Example: nn Input: 0000Input: 0000BCDBCDnn Output: 1111110 Output: 1111110
(a=b=c=d=e=f=1, g=0)(a=b=c=d=e=f=1, g=0)d
a
b
c e
f g
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30-Apr-09 13Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
BCDBCD--toto--SevenSeven--Segment (cont.)Segment (cont.)Truth TableTruth Table
11100X011100X00111011177X011111X0111110110011066101101110110110101010155011001101100110100010044111100111110010011001133110110111011010010001022011000001100000001000111111111011111100000000000abcdefgabcdefgwxyzwxyzDigitDigit abcdefgabcdefgwxyzwxyzDigitDigit
XXXXXXXXXXXXXX11111111XXXXXXXXXXXXXX11101110XXXXXXXXXXXXXX11011101XXXXXXXXXXXXXX11001100XXXXXXXXXXXXXX10111011XXXXXXXXXXXXXX10101010
111X011111X0111001100199111111111111111000100088
??
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30-Apr-09 14Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
DecodersDecoders
nn A combinational circuit that converts A combinational circuit that converts binary information from binary information from nn coded inputs coded inputs to a maximum 2to a maximum 2n n decoded outputs decoded outputs àà nn--toto-- 22nn decoderdecoder
nn nn--toto--mm decoder, decoder, m m == 22nn
nn Examples: BCDExamples: BCD--toto--77--segment decoder, segment decoder, where where n=4n=4 and and m=7m=7
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30-Apr-09 15Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Decoders (cont.)
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30-Apr-09 16Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
2-to-4 Decoder
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30-Apr-09 17Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
2-to-4 Active Low Decoder
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30-Apr-09 18Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
33--toto--8 Decoder8 Decoder
addressaddress
datadata
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30-Apr-09 19Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
33--toto--8 Decoder (cont.)8 Decoder (cont.)nn Three inputs, AThree inputs, A00, A, A11, A, A22, are decoded into , are decoded into
eight outputs, Deight outputs, D0 0 through Dthrough D77
nn Each output DEach output Dii represents one of the represents one of the minterms of the 3 input variables.minterms of the 3 input variables.
nn DDii = 1 when the binary number A= 1 when the binary number A22AA11AA00 = = iinn Shorthand: DShorthand: Dii = m= mii
nn The output variables are The output variables are mutually exclusivemutually exclusive; ; exactly one output has the value 1 at any time, exactly one output has the value 1 at any time, and the other seven are 0.and the other seven are 0.
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30-Apr-09 20Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
nn AnyAny combinational circuit can be constructed combinational circuit can be constructed using decoders and OR gates! Why?using decoders and OR gates! Why?
nn Here is an example:Here is an example:Implement a full adder circuit with a decoder Implement a full adder circuit with a decoder and two OR gates.and two OR gates.
nn Recall full adder equations, and let X, Y, and Z Recall full adder equations, and let X, Y, and Z be the inputs:be the inputs:nn S(X,Y,Z) = X+Y+Z = S(X,Y,Z) = X+Y+Z = ΣΣm(1,2,4,7) m(1,2,4,7) nn CC (X,Y,Z) = (X,Y,Z) = ΣΣm(3, 5, 6, 7).m(3, 5, 6, 7).
nn Since there are 3 inputs and a total of 8 Since there are 3 inputs and a total of 8 minterms, we need a 3minterms, we need a 3--toto--8 decoder.8 decoder.
Implementing Boolean functionsImplementing Boolean functionsusing decodersusing decoders
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30-Apr-09 21Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Implementing a Binary Adder Using a Decoder
S(X,Y,Z) = Sm(1,2,4,7)
C(X,Y,Z) = Sm(3,5,6,7)
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30-Apr-09 22Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Decoder ExpansionsDecoder ExpansionsLarger decoders can be constructed using a number of smaller ones.
-> HIERARCHICAL design!Example:A 6-to-64 decoder can be designed using four 4-to-16 and one 2-to-4 decoders. How? (Hint: Use the 2-to-4 decoder to generate the enable signals to the four 4-to-16 decoders).
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30-Apr-09 23Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
33--toto--8 decoder using two 28 decoder using two 2--toto--4 decoders4 decoders
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30-Apr-09 24Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
44--input tree decoderinput tree decoder
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30-Apr-09 25Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
EncodersEncoders
nn An encoder is a digital circuit that An encoder is a digital circuit that performs the inverse operation of a performs the inverse operation of a decoder. An encoder has 2decoder. An encoder has 2nn input lines input lines and and nn output lines. output lines.
nn The output lines generate the binary The output lines generate the binary equivalent of the input line whose value equivalent of the input line whose value is 1.is 1.
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30-Apr-09 26Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Encoders (cont.)Encoders (cont.)
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30-Apr-09 27Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Encoder ExampleEncoder Examplenn Example: 8Example: 8--toto--3 binary encoder (octal3 binary encoder (octal--toto--binary)binary)
A0 = D1 + D3 + D5 + D7A1 = D2 + D3 + D6 + D7A2 = D4 + D5 + D6 + D7
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30-Apr-09 28Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Encoder Example (cont.)Encoder Example (cont.)
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30-Apr-09 29Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Simple Encoder Design IssuesSimple Encoder Design Issuesnn There are two ambiguities associated with There are two ambiguities associated with
the design of a simple encoder:the design of a simple encoder:1.1. Only one input can be active at any given time. If Only one input can be active at any given time. If
two inputs are active simultaneously, the output two inputs are active simultaneously, the output produces an undefined combination (for example, produces an undefined combination (for example, if Dif D33 and Dand D66 are 1 simultaneously, the output of are 1 simultaneously, the output of the encoder will be 111.the encoder will be 111.
2.2. An output with all 0's can be generated when all An output with all 0's can be generated when all the inputs are 0's,or when Dthe inputs are 0's,or when D00 is equal to 1.is equal to 1.
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30-Apr-09 30Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Priority EncodersPriority Encoders
nn Solves the ambiguities mentioned above.Solves the ambiguities mentioned above.nn Multiple asserted inputs are allowed; Multiple asserted inputs are allowed;
one has priority over all others.one has priority over all others.nn Separate indication of no asserted Separate indication of no asserted
inputs.inputs.
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30-Apr-09 31Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Example: 4Example: 4--toto--2 Priority Encoder2 Priority EncoderTruth TableTruth Table
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30-Apr-09 32Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
44--toto--2 Priority Encoder (cont.)2 Priority Encoder (cont.)nn The operation of the priority encoder is The operation of the priority encoder is
such that:such that:nn If two or more inputs are equal to 1 at If two or more inputs are equal to 1 at
the same time, the input in the highestthe same time, the input in the highest--numbered position will take precedence.numbered position will take precedence.
nn A A valid output indicatorvalid output indicator, designated by , designated by V, is set to 1 only when one or more V, is set to 1 only when one or more inputs are equal to 1. V = Dinputs are equal to 1. V = D33 + D+ D22 + D+ D11 + + DD00 by inspection.by inspection.
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30-Apr-09 33Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Example: 4Example: 4--toto--2 Priority Encoder2 Priority EncoderKK--MapsMaps
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30-Apr-09 34Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Example: 4Example: 4--toto--2 Priority Encoder2 Priority EncoderLogic DiagramLogic Diagram
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30-Apr-09 35Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
88--toto--3 Priority Encoder3 Priority Encoder
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30-Apr-09 36Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
A Matrix of switches = KeypadA Matrix of switches = KeypadC0 C1 C2 C3
R0
R1
R2
R3
1 2 3 F
4 5 6 E
7 8 9 D
0 A B C
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30-Apr-09 37Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Keypad Decoder IC Keypad Decoder IC -- EncoderEncoder
1 2 3 F
4 5 6 E
7 8 9 D
0 A B C
COL.4-bit
ROW4-bit
4-bitBinary
(encoded)
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30-Apr-09 38Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Priority Interrupt Encoder Priority Interrupt Encoder SchematicSchematic
Device A
Device B
Device C
Device D
MicroprocessorInterruptEncoder
Req(1:0)
IntRq
InterruptingDevices
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30-Apr-09 39Chapter 3-ii: Combinational Logic Design (3.4 - 3.6)
Priority Encoding Priority Encoding -- Interrupt Interrupt RequestsRequests
Interrupting DeviceInterrupting Device
111 01 000001100110 10 111110000110 10 100110000110 00 011000000000 00 000000000
IntRqIntRqReqReq (1:0)(1:0)DDCCBBAA
Exercise: Complete this table?