low energy flip-flop design (dejan)

8/3/2019 Low Energy Flip-Flop Design (Dejan)

1/9

Low Energy Flip-Flop Design

Dejan Markovic

Prof. Borivoje NikolicProf. Robert W. Brodersen

Department of EECS

University of California, Berkeley

BWRC Retreat, January 2000


2/9

Motivation

Clock power dissipation (about 30% of the total system

power) is divided between three major contributors:

Clock wires

Clock buffers

Flip-Flops

Power consumed in Flip-Flops can be significantly

reduced in some applications (DCT) by Flip-Flop selection

[Hamada et al., ISSCC 99]

Clock buffer design is tightly related to the design ofFlip-Flops


3/9

Conventional Flip-Flop Design

Master Slave Latches

Small clock-output delay, but positive setup time

Clock generated locally, clock load is high

Feedback added for static operation

Pulse Triggered Latches First stage is pulse generator

generates a pulse (glitch) on a rising edge of the clock

Second stage is a latch

captures the pulse generated in the first stage

Pulse generation results in a negative setup time

Frequently exhibit a soft edge property (negative setup time)

Power is always consumed in the pulse generator!


4/9

Low Energy Flip-Flop Design

E = Ey C y VDD y Vswing

Energy reduction mechanisms:

Reduce node switching probability

Reduce switched capacitance

Scale down supply voltage

Low swing circuit techniques

Low Energy Flip-Flop Techniques:

Reduced Clock Swing

Data Transition Lookahead (Clock-On-Demand) Activate internal clock only when the input data is to change the output

Dual Edge Triggered

DL-DFF circuit[from Nogawa et al., JSSC 05/98]


5/9

Performance Metrics

Setup/Hold time = f (CLK slope, VDD)

Energy per transition

Useful transitions are 01 and 10

Explore 00 and 11 transitions too to see how much

energy can be saved by deactivating internal clock

TCLK-Q = f (CLK slope, Setup/Hold times, VDD)

D Q

Clk

D Q

Clk

Logic

N

TLogicTClk-Q TSetup

Sum of setup time and CLK-Q

delay is the only true measure of theperformance with respect to the

system speed

T= TCLK-Q + TLogic + Tsetup+ Tskew


6/9

Test Example: Master Slave Latch

Vdd Vdd

Clk

QClk Clkb

Clkb

D

PowerPC 603 (Gerosa, JSSC 12/94)


7/9

Delay vs. Setup/Hold Times

Setup time increases

with increase in

supply voltage

Hold time decreases

with increase in

supply voltage

Sampling window

widens as supply

voltage increases

PowerPC603

1.00E-10

3.00E-10

5.00E-10

7.00E-10

9.00E-10

1.10E-09

1.30E-09

-1.39E-09 -1.11E-09 -8.58E-10 -6.36E-10 -4.04E-10 -4.72E-10 -2.12E-10 3.55E-12 2.44E-10 4.59E-10 6.41E-10

Data-CLK

tpLH

Vdd = 1V

Vdd = 1.8V Vdd = 2.5V


8/9

Energy vs. Setup/Hold Times

PowerPC603

0.00E+00

5.00E-13

1.00E-12

1.50E-12

2.00E-12

2.50E-12

-2.14E-10 -6.16E-12 2.80E-11 6.30E-11 9.70E-11 1.28E-10 1.61E-10 1.94E-10 2.26E-10

Data - CLK

Energy

(1-0

transition)

Vdd = 2.5V

Vdd = 1.8V

Scales down ~ 3 .3 times

(2.5/1.8)2 = 1.93

because 4/8 internal nodes

don't swing rail-to-rail

setup time

violation

hold time

violation

hold timeviolation

setup time

violation

For this

topology,

decrease in

energy vs. VDDis better than

quadratic,

because some

internal nodes

dont swingrail-to-rail


9/9

Future Work

Measure what is a minimum energy needed for a Flip-Flop

to record one transition at its output, for a given input data

throughput

Find the minimum energy solution of the entire timing

sub-system containing clock distribution network and

timing elements

Multiple voltage domains

Flip-Flop selection for Power-Delay tradeoff

Clock generation and clock distribution to multiple clock domains

low energy flip-flop design (dejan)

Documents