low frequency noise in advanced mos transistors...2010 ‐11‐19 low frequency noise in advanced...

UC Berkeley EE298‐12 Solid State Technology and Device Seminar

2010‐11‐19

Low Frequency Noise in Advanced MOS Transistors

Chia‐Yu ChenDepartment of Electrical Engineering

Stanford University

• CMOS scaling

Motivation

2

ItIt’s ok.It’s noisy.

IEDM 2008 short course11/19/2010 C.‐Y. Chen UCB EE298‐12 Seminar

Low Frequency Noise becomes important!

• Low Frequency (LF) noise

Motivation

3

Fabrication

Device Material s

IC designer Physicist

Mathematician

LF noise

11/19/2010 C.‐Y. Chen UCB EE298‐12 Seminar

• Introduction• Methodology• SiGe

channel

• Size effect• Conclusions

Outline


• Introduction

• Methodology• SiGe

channel


Outline

5

Why LF noise is important?

The origin of LF noise

CMOS scaling



6

– White

noise:

thermal

noise

and shot noise.

– 1/f

noise:

certain

trap

distribution

or

fluctuation

in mobility.

– G‐R

noise:

trap/de‐trap

mechanism;

one

special

case is RTN.

Low frequency (LF) noise106105104103102

Sid

(A2 /H

z)

Frequency (Hz)

• Noise in a MOSFET


• Analog domain


7

f0

VCO: phase noise

– LF noise is up‐converted and causes phase noise.

– Phase noise limits channel capacity.

1 10 1001E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

S id

(uA

2 /H

z)

Frequency (Hz)

1/f

Good oxide Up‐convert

1 10 1001E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

S id

(uA

2 /H

z)

Frequency (Hz)

1/f

Good oxide

Worse oxide

Adjacent channel



8

– LF noise increases with scaling.

– Noise margin becomes small.

• Digital domain


N. Tega, VLSI symp. 2009, p. 50‐51.

SRAM: noise

margin

• Introduction

• Methodology• SiGe

channel


Outline

9



CMOS scaling



10

– Conductivity fluctuation.

– Two

schools:

number

fluctuations

(ΔN)

and

mobility

fluctuations (Δμ).

σ=μeff

N

• Two schools


• ΔN model: one trap


11

A. McWhorter, Semi.Surf. Phys., 1957.

N+ N+

G

Surface effect

s D

Random telegraph noise

Lorentzian

one trap/de‐trap


• ΔN model: a lot of traps


12

A. McWhorter, Semi.Surf. Phys., 1957. Correlated Δμ

is also induced.

0 5 10 15

2.06E-006

2.07E-006

I d (A

)

Time (s)

N+ N+

G

s D



13

• ΔN model: a lot of traps

– Sum of Lorentzians: 1/f noise

Depth in oxide (um)1e‐3

Gate (um)

F=1Hz

Channel

F=1e4Hz

Channel

Depth in oxide (um)1e‐3

Sid(A2 /Hz)

Frequency (Hz)

1/f

SISPAD 2006, Y. LiuGate (um)


• ΔN model: Id

and Vg

dependence


14

– Id

: Sid

/Id2

α

(gm

/Id

)2.

– Vg

: flat in weak inversion.

)(2)( RGrSnt

S id/I d2 (1/Hz)

Drain current (A) 0.0 0.5 1.0 1.5

1E-11

1E-10

1E-9

1E-8

S id/

I d2

(1/H

z)Gate Voltage (V)

S id/I d2 (1/Hz)

1e‐11

1e‐10

1e‐9

1e‐8

Gate voltage (V)


Fix Vd and increase Vg (g m/Id)2 (1/Hz)

• Δμ

model


15

– Bulk phonon scattering

– Empirical equation

N-type Si substrate

P+ P+

Source

Gate

Drain

2Id H

d i

S qI WLQ f

T‐ED 1994, F. N. Hooge

1E-5

1E-4

1E-3

100

S id

(uA

2 /H

z)

Frequency (Hz)

1/f

1 10

Phonon Si bulk

Bulk effect

Hooge mobility fluc.11/19/2010 C.‐Y. Chen UCB EE298‐12 Seminar

-0.5 0.0 0.5 1.0 1.5 2.0

1E-11

1E-10

1E-9

1E-8

1E-7

S id/

I d2

(1/H

z)Gate Voltage (V)


16

• Δμ

model: Id

and Vg

dependence

)(2)( RGrSnt

S id/I d2 (1/Hz)

Drain current (A) S id/I d2 (1/Hz)

1e‐11

1e‐10

1e‐9

1e‐8

– Id

: Sid

/Id2

α

1/Id

.

– Vg

: Sid

/Id2

increases when Vg

decreases.

Gate voltage (V)

2Id H

d i

S qI WLQ f


• ΔN or Δμ?


17

– Different trend in Id

and Vg

dependence.

Fix Vd and increase Vg

S id/I d2 (A

2 /Hz)

Drain current (A)

G. Ghibaudo, Noise in

Devices and Circuits, 2003.

0.0 0.5 1.0 1.5 2.0

1E-11

1E-10

1E-9

1E-8

1E-7

S id/

I d2

(1/H

z)Gate Voltage (V)

S id/I d2 (A

2 /Hz)

Gate voltage (V)

Δμ

ΔN


• Introduction

• Methodology• SiGe channel• Size effect• Conclusions

Outline

18



CMOS Scaling


CMOS scaling

19

– CMOS scaling: provide new opportunity to optimize LF noise.


Size:Larger variability

• Introduction• Methodology

• SiGe channel• Size effect• Conclusions

Outline

20

Overview

TCAD simulations

Noise characterization


Overview

21


TCAD simulations

Explain low frequency noise mechanism


• Introduction• Methodology


Outline

22

Overview

TCAD simulation



TCAD simulation

23

– Total noise is the sum of ΔN and Δμ.– No correlation.

Sid_total

=Sid_ ΔN

+Sid_ Δμ


TCAD simulation

24

• Impedance field method (IMF)

Vd

Vg

Vs

W. Shockley, QuantumTheory of Atoms,

Molecules and Solid State,

1966, pp. 537–563.

Injection

current

Voltage

fluct. at

drain


TCAD simulation

25

• Impedance field method (IFM)

oxide

Pinch‐off

DrainSource

Tride Saturation

Gate

IFM: linear No effect


TCAD simulation

26

• ΔN model

– Noise source is inside oxide.– A rate equation to correlate oxide traps and channel

carriers and then apply IMF to calculate Sid

.

G‐Roxide

channel drain


TCAD simulation

27

– Extract parameters from TCAD simulations such as Qi.

202 )/1( cDn

202 )/1( cDn

202 )/1( cDn

• Δμ

model

Extract from TCAD

~1e-5 for Si material

2Id H

d i

S qI WLQ f

IEEE T‐ED 2008, C.‐Y. Chen


• Introduction• The origin of LF noise• Methodology


Outline

28

Overview

TCAD simulations




• Basic schematic

29

– Offset current removes the DC component at the input.– SR570 is used to drive high impedance loads and input impedance

of signal analyzer should be high.

Offset current

Signal analyzer

SR 570

HP 4156

A. Blaum, Agilent document, 2000.

DUT



• Measurement bench

30

SR 570

Wafer (DUT)

Drain

Gate

Source

Bulk

Cascade probe station HP4156

SR760 FFT spectrum analyzer


• Introduction• Methodology• SiGe channel


Outline

31

Device schematic

Gate bias

Body bias


• Si/SiGe/Si p‐HFET

Device schematic

32

– Two

channels:

SiGe

buried

channel

and

parasitic

surface

channel.

L/W=1um/10um oxide thickness=6nm

Si/SiGe/Si p-MOSFET

Source Drain

Gate

Bulk

SiGe buried channel

Parasitic surface channel

SiO2

Body

Lg=1um

Devices from PanasonicSi

SiGe

Si


• Advantage

Device schematic

33

– Improve LF noise: (1) longer tunneling distance and (2) smaller Coulomb interaction.

1 10 100 1000 100001E-22

1E-21

1E-20

1E-19

1E-18

S id

(A2 /

Hz)

Frequency (Hz)

Si: TCAD Si: meas. Si/SiGe/Si: TCAD Si/SiGe/Si: meas.

W/L=10um/1umVd=-0.5V|Vg|-|Vth|=0.3V




Outline

34

Device schematic

Gate bias

Body bias


• Dual‐channel behavior

1 10 100 10001E-20

1E-19

1E-18

1E-17

Sid

(A2 /

Hz)

Frequency (Hz)


W/L=10um/1umVd=-0.5VVov=2V

Gate bias

35

– When buried channel dominant LF noise is reduced.

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.50.000

0.002

0.004

0.006 Si/SiGe/Si p-HMOS

Surf. charge Buried charge

Gate voltage (V)

Cha

rge

Den

sity

(C/m

2 )Vd=-0.1V

1 10 100 1000 100001E-22

1E-21

1E-20

1E-19

1E-18

S id

(A2 /

Hz)

Frequency (Hz)


W/L=10um/1umVd=-0.5V|Vg|-|Vth|=0.3V


• Vg

dependence

Gate bias

36

-2.5 -2.0 -1.5 -1.0 -0.5 0.0 0.51E-12

1E-11

1E-10

1E-9

1E-8

1E-7

Vd=-0.1V

Number fluc. Mobility fluc. Total noise Measurements

S id/

I d2

(1/H

z)

Gate Voltage (V)

SiGe p-HMOS

ΔN

Δμ

ΔN


– Weak inversion: Δμ– Medium/strong inversion: ΔN

1E-9 1E-8 1E-7 1E-6 1E-5 1E-410-1610-1510-1410-1310-1210-1110-1010-910-810-7

Drain Currrent (A)

Sid

/I d2

(1/H

z)

SiGe p-HMOSVd=-0.1V

• Id

dependence

Gate bias

37

ΔN

Δμ

– Weak inversion: Δμ– Medium/strong inversion: ΔN

(gm

/Id)2

(V-2

)

10-210-1100101102103104105106107




Outline

38

Device schematic

Gate bias

Body bias


• SiGe p‐HFET

Body bias

39

10 100 1000

1E-23

1E-22

1E-21

1E-20

TCAD Vb=-0.4V Vb=-0.2V Vb=0V Vb=0.2V

SiGe p-HMOS

Vd=-0.5VVov=-0.3V

S id(

A2 /

Hz)

Frequency (Hz)

Vb=-0.4V Vb=-0.2V Vb=0V Vb=0.2V

Mea.

– LF noise in SiGe p‐HFET has strong body bias dependence.

SISPAD 2007, C.‐Y. Chen

forward

reverse


Body bias

40

• SiGe p‐HFET

– Body bias changes carrier distribution in dual channels

reverseforward-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2

1E13

1E14

1E15

Vd=-0.5V

Si cap layer SiGe channel

Vov=-0.3V

Hol

e de

nsity

(cm

-2)

Body bias (V)

Si/SiGe/Si p-HMOSTCAD simulation

Surf.Buried

Surf.Buried

T‐ED 2008, C.‐Y. Chen11/19/2010 C.‐Y. Chen UCB EE298‐12 Seminar

Body bias

41

• SiGe p‐HFET

T‐ED 2008, C.‐Y. Chen

– FL noise is mainly from surface channel.

-0.4 -0.3 -0.2 -0.1 0.0 0.1 0.21E-22

1E-21

1E-20

Vov=-0.3V

Si cap layer hole density Simulated Sid Measured Sid

Body bias (V)

Vd=-0.5V

1E14

1E15

1E16S i

d (A

2 /H

z)Si/SiGe/Si p-HMOS

Surf

ace

carr

ier d

ensi

ty (c

m-2

)

reverseforward

more noisyless noisy


Body bias

42

• Si p‐FET

– Si p‐MOS does not show body bias dependence.

SISPAD 2007, C.‐Y. Chen

10 100 1000

1E-21

1E-20

1E-19

TCAD Vb=-0.4V Vb=-0.2V Vb=0V Vb=0.2V

Vd=-0.5VVov=-0.3V

Vb=-0.4V Vb=-0.2V Vb=0V Vb=0.2V

S id

(A2 /

Hz)

Frequency (Hz)

Si pMOS

Mea.

reverse

forward


• Introduction• Methodology• SiGe channel• Size effect

• Conclusions

Outline

43

Device schematic

Mechanism

Gate bias


Device schematic

44

– Only a few traps are involved.

– ΔN predicts RTN; Δμ

shows 1/f noise.

α

Cross view Top view

L/W=40nm/70nm oxide thickness~2.5nm

Devices from G‐foundries


• Scaled MOSFETs (small gate area)


• Conclusions

Outline

45

Device schematic

Mechanism

Gate bias


• Ig‐

/ Id‐RTN

Mechanism

N+ N+

G

s D

A few trap/de‐trap

Id

Time

Ig

Time

– Two types: Ig‐RTN

and Id‐RTN.


Mechanism

• Where are traps?

47

– Traps should be inside high‐κ

oxide.

0.4 0.8 1.2 1.6 2.0 2.4

120

160

200

240

280

320

Elec

tron

mob

ility

(cm

2 /Vs)

Interfacial layer thickness (nm)

High-k metal gate nMOSFET(HfO2/TiN)

SiON

gatechannel

xxx

HfO2


Et Ef

Mechanism

• Trap/de‐trap

48

7.00E-012

7.20E-012

7.40E-012

0 10 20 30

1.56E-006

1.58E-006

1.60E-006

trapped state

de-trapped state

charge de-trap(emission)

charge trap(capture)

I g

(A)

I d (A

)

Time (s)

– Capture: Vth

and TAT increase Id

and Ig

– Emission:

Vth

and TAT decrease Id

and Ig

Track each other


Mechanism

• PBTI and RTN

49

– Consistent with RTN results.

-0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.01E-13

1E-11

1E-9

1E-7

1E-5

IgI d (A

) or

Ig

(A)

Vg (V)

Before stress Positive stress Negative stress

Id



• Conclusions

Outline

50

Device schematic

Mechanism

Gate bias


• Ig

‐RTN

Gate bias

– Vg

increases: Time in high‐Ig

state increases.

EtEf

51

5 .2 x 1 0 - 1 15 .6 x 1 0 - 1 16 .0 x 1 0 - 1 16 .4 x 1 0 - 1 1

3 .2 x 1 0 - 1 1

3 .6 x 1 0 - 1 1

0 5 1 0 1 5 2 0 2 51 .6 x 1 0 - 1 1

1 .8 x 1 0 - 1 1

2 .0 x 1 0 - 1 1

Ig (A

)

Time (s)

Vg=1V

Vg=0.9V

Vg=0.8V


Gate bias

52

• Id

‐RTN: Low Vg

– Measurement still shows 1/f noise; Δμ

model is dominant.

0.01 0.1 1 101E-24

1E-23

1E-22

1E-21

1E-20

1E-19

S id

(A2 /

Hz)

Frequency (Hz)

Vg=0.2VVd=20mVScaled nMOSFETL=50nmW=70nm

1/f

150 155 160 165 170

2.05E-009

2.10E-009

2.15E-009

2.20E-009

2.25E-009

2.30E-009

Id (A

)

Time (s)

Vd=10mV Vg=0.2V


Gate bias

53

• Id

‐RTN: High gm bias condition

0.1 1 101E-20

1E-19

1E-18

1E-17

1E-16

1E-15

S id

(A2 /

Hz)

Frequency (Hz)

Vd=10mVVg=570mVScaled nMOSFETL=50nmW=70nm

1/f2

20 25 30 354.60E-007

4.65E-007

4.70E-007

4.75E-007

4.80E-007

I d (A

)

Time (s)

Vd=10mV Vg=570mV

– RTN and Lorentzian shape are observed

in high gm region.


Gate bias

54

• Id

‐RTN: High Vg

– 1/f noise is shown in a very scaled MOSFET: Δμ

is dominant.

0.1 1 10

1E-20

1E-19

1E-18

1E-17

1E-16

S id

(A2 /

Hz)

Frequency (Hz)

Vd=10mVVg=750mVScaled nMOSFETL=50nmW=70nm

1/f

0 10 20 30 40

8.26E-007

8.28E-007

8.30E-007

8.32E-007

8.34E-007

8.36E-007

8.38E-007

8.40E-007

8.42E-007

Vd=10mV Vg=750mV

Id(A

)

Time (s)


55

– RTN should be considered especially in high gm region. 1/f

-0.4 0.0 0.4 0.8 1.20.0

4.0x10-7

8.0x10-7

1.2x10-6

1.6x10-6

2.0x10-6

gm

(1/o

hm)

Vg (V)

Vd=10mVScaled nMOSL/W=50nm/70nm

1/f

Δμ

Gate bias

RTN

Δμ

ΔN


• Id

‐RTN: summary

56

– RTN should be considered especially in high gm region.

-0.4 0.0 0.4 0.8 1.20.0

4.0x10-7

8.0x10-7

1.2x10-6

1.6x10-6

2.0x10-6

gm

(1/o

hm)

Vg (V)

Vd=10mVScaled nMOSL/W=50nm/70nm

Δμ

Gate bias

Δμ

ΔN

Sid/Id2

Freq

1/f

Freq

1/f

Lorentzian

Freq

1/f

Sid/Id2

Sid/Id2


• Id

‐RTN: summary

• Introduction• The origin of LF noise• Methodology• SiGe channel• Size effect• Conclusions

Outline

57

Summary

Contributions

Future work


Summary

58

Bias SiGe H‐MOS (Lg~1um) Scaled MOS (Lg~40nm)

Weak inversion Δμ

model is dominant. Δμ

model is dominant.

High gm region (~ Vdd

/2) ΔN model is important; LF noise is mostly surface

effect.

ΔN model becomes

important; RTN should be

considered.

High Vg

conditionΔN is dominant in our

device, but in general it

can be technology

dependence.

Δμ

model is dominant


Summary

59

The origin of LF noise: (1)

ΔN model and (2)

Δμ

model.

Methodology:

TCAD simulations and noise measurements

SiGe

channel:

Dual‐channel

is

important

to

explain

the

low

frequency noise performance.

Size effect: Ig

‐RTN is directly related to physical trapping or de‐

trapping

and

the

Id

‐RTN

reflects

sensitivity

to

charge

trapping

as determined by gm

.

CMOS scaling: provides a new opportunity for LF noise study.


Contributions

60

Detailed LF noise mechanisms in SiGe p‐HFET are proposed.

LF noise mechanisms in scaled MOSFETs are

measured

and

analyzed.

Other parts: (1) LF noise mechanisms in high‐κ

MOSFET, (2)

A

LF

noise

compact

model

in

SiGe

p‐HFET,

(3)

linearity

of

asymmetric channel doping for LDMOS, (4) linearity in GaN HEMTs, and (5) asymmetric FET scaling.


Future work


Rethink “device noise” “distortion” and “reliability”

Publications

11/19/2010 62

[1] C.‐Y. Chen, Q. Ran, H.‐J. Cho, A. Kerber, Y. Liu, M.‐R. Lin, and R. W. Dutton, IRPS, 2011.[2] C.‐Y. Chen, C.‐C. Wang, Y. Ye, Y. Liu, Y. Cao, and R. W. Dutton, SASIMI, 2010.[3] C.‐Y. Chen, O. Tornblad, R. W. Dutton, IEEE Trans. on Microwave Theory and

Techniques, Dec. 2009.

[4] C.‐Y. Chen

and R. W. Dutton, IEEE Design & Test of Computers, 2009.[5] C.‐Y. Chen, Y. Liu, J. Kim, R. W. Dutton, SISPAD 2009, Sept. 2009.[6] C.‐Y. Chen, O. Tornblad, R. W. Dutton, IEEE MTT‐S International Microwave

Symposium Dig. (IMS), pp. 601‐604, 2009.

[7] C.‐Y. Chen, Y. Liu, R. W. Dutton, J. Sato‐Iwanaga, A. Inoue, H. Sorada, SASIMI

2009, Sapporo, Japan, pp. 405‐409, March 2009.

[8] C.‐Y. Chen, Y. Liu, R. W. Dutton, J. Sato‐Iwanaga, A. Inoue, H. Sorada, IEEE Trans. Electron Devices, July, 2008.

[9] J.

Kim, C.‐Y.

Chen

and R.

W.

Dutton, Journal of Computational Electronics, Jan. 2008.[10] C.‐Y. Chen, Y. Liu, R. W. Dutton, J. Sato‐Iwanaga, A. Inoue, H. Sorada, SASIMI, Sapporo,

Japan, pp. 238‐241, Oct. 2007.[11] C.‐Y. Chen, Y. Liu, R. W. Dutton, J. Sato‐Iwanaga, A. Inoue, H. Sorada,

Workshop on Compact Modeling (WCM) 2007, San Jose, USA, March 2007.

[12] J. Kim, C.‐Y. Chen, R. W. Dutton,

SISPAD, Nov. 2007.[13] J. Kim, C.‐Y. Chen, R. W. Dutton, Proc. of 12th International Workshop on

Computational Electronics (IWCE), Oct. 2007.C.‐Y. Chen UCB EE298‐12 Seminar

UC Berkeley EE298‐12 Solid State Technology and Device Seminar

2010‐11‐19

Backup: Linearity analysis of lateral channel doping in RF power MOSFETs

Chia‐Yu ChenDepartment of Electrical Engineering

Stanford University

• Introduction

• Quasi‐1D structure

• Realistic LDMOS structure

• Conclusions

Backup: Outline

ω ω

Linearity:

Low distortion is one of the most important concerns for wireless communication systems.

Analysis of the distortion generated by the device itself has been fairly limited.

Backup: Introduction (1 of 2)

Harmonic balance device simulations:

A unique harmonic balance (HB) device simulator with the capability of including external circuitry is used.

In the HB simulations, variations in device parameters are directly reflected in the final large signal RF performance.

Backup: Introduction (2 of 2)

0.0 0.1 0.2 0.3 0.4 0.51E16

1E17

1E18

Cha

nnel

dop

ing

(cm

-3)

Lateral location (um)

uniform 8e16 cm-3

uniform 2e17 cm-3

char. length 0.2um char. length 0.3um

Source DrainGraded channel doping

Gate

0.5um gate length, 30nm oxide thickness.

Avoid 2D-effects.

Very high source and drain dopings to avoid compensation effects at source and drain junctions.

4 cases: 2 uniform doping and 2 laterally graded.

Test circuit consisting of bias feeds and blocking capacitors on input and output.

Device schematic:

Backup: Quasi‐1D structure (1 of 3)

1.5 2.0 2.5 3.0 3.5

0

Gm

3/G

m

Gate voltage (V)

uniform 8e16cm-3

uniform 2e17cm-3 char. length 0.3um char. length 0.2um

Different gm3/gm magnitudes for different cases. Devices were biased at gm3/gm minima, close to overall best linearity.

gm3/gm:

-1.5 -1.0 -0.5 0.0

-65

-60

-55

-50

-45

-40

-35

-30

-25

IM3d

Bc

Log10(Vin)

uniform 8e16cm-3

uniform 2e17cm-3


Freq.=10MHz

First data point correlates to magnitude of gm3/gm minima.Shorter char. length / lower uniform doping: higher IM3 at low input power lower IM3 at high input power.

IM3:


0.0 0.1 0.2 0.3 0.4 0.5

0

1x105

2x105

3x105

4x105

Late

ral e

lect

rical

fiel

d (V

/cm

)

Lateral channel position (um)

unifrom 8e16cm-3

uniform 2e17cm-3


Vg at gm3/gm min.Vd: 2.0V

Field distribution:

Graded cases more uniform field.

Smaller uniform doping more uniform field.

Uniform lateral field better linearity at higher power.


0.4 0.6 0.8

1E14

1E15

1E16

1E17

1E18

1E19

1E20

Late

ral c

hann

el d

opin

g (c

m-3

)

Lateral channel location (um)

char. length 0.0525um char. length 0.0625um char. length 0.0725um char. length 0.0925um

Device schematic (based on Infineon 7th generation design):

Two different lightly doped drain regions: optimize on-resistance and breakdown voltage.

Source doping and lightly doped drain kept the same for all cases.

Four different lateral grading cases in channel, defined through analytical expressions.

Backup: Realistic LDMOS (1 of 4)

6.0 6.3 6.6 6.9 7.2 7.5-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

1.5

Gm

3/G

m1

Gate voltage (V)


gm3/gm:

Circuitry with internal and external matching and bias.Infineon product PTF210451.

Bias-point at gm3/gm minima.

Test circuitry:


0.0 0.5-60

-50

-40

-30

IM3d

Bc

Log10(Vin)


Freq. = 2.14GHz

20 25 30 35 40-60

-50

-40

-30

IM3d

Bc

IM1


Freq. = 2.14GHz

IM3 at 2.14GHz:

Effect of graded doping is significant the nonlinearities in capacitances will not swamp the studied effects at high frequency.

More graded channel profile shows better linearity in the intermediate power regime.


20 25 30 35-60

-50

-40

-30

IM3d

Bc

IM1

char. 0.0525um; shift 50mv char. 0.0925um; shift -30mv char. 0.0525um; shift 0mv char. 0.0925um; shift -100mv

Freq. = 2.14GHz

Vgs shifts from gm3/gm minima

IM3 change is quite sensitive.

Different device designs give different IM3 that cannot be compensated for by simply changing Vgs bias (Idq setting).

Vgs shifts from gm3/gm:


• A graded channel has better linearity for intermediate to high powers. By contrast, for increased back‐off, the

situation is reversed.

• Nonlinearities in intrinsic capacitances will not swamp the effect of graded channel doping at high frequency.

• The effect of graded channel doping cannot be fully compensated for by adjusting the Idq bias point.

• The analysis lays ground‐work for RF device optimization for improved linearity.

Backup: Conclusions

0 1 2 3 41E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

1E-4

unifrom 8e16cm-3

unifrom 2e17cm-3


Gate voltage (V)

Dra

in c

urre

nt, l

og s

cale

(A/u

m)

0.0

2.0x10-54.0x10-56.0x10-58.0x10-51.0x10-41.2x10-41.4x10-41.6x10-41.8x10-42.0x10-4

Dra

in c

urre

nt, l

inea

r sca

le (A

/um

)

Vd=2.0V

1.5 2.0 2.5 3.0 3.5

0

Gm

3/G

m

Gate voltage (V)

uniform 8e16cm-3

uniform 2e17cm-3 char. length 0.3um char. length 0.2um

Clearly different gm3/gm magnitudes for different cases. Shorter characteristic length and lower doping give larger gm3/gm magnitudes.Devices were biased at gm3/gm minima, close to overall best linearity for many applications.

Quasi-1D structure: IdVgs

Backup: Additional information (1 of 4)

Quasi-1D structure: velocity saturation:

2.6 2.8 3.0 3.2 3.4 3.6-2.0

-1.5

-1.0

-0.5

0.0

Gm

3/G

m

Gate voltage (V)

w/ Vsat model w/o Vsat model

Uniform doping 2e17cm-3

-25 -20 -15 -10 -5 0 5 10-80

-70

-60

-50

-40

-30

IM3d

Bc

IM1

w/ Vsat model w/o Vsat model

Uniform doping 2e17cm-3

When Vsat model is not included: 1. gm3/gm shifts to a smaller magnitude. 2. IM3 is much lower, both initially and for high powers.


1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0

-65

-60

-55

-50

-45

-40

-35

-30

IM3d

Bc

Log10(Vin)


Freq.=10MHz

Realistic LDMOS: IM3 at 10MHz

-10 -5 0 5 10 15 20

-65

-60

-55

-50

-45

-40

-35

-30Freq.=10MHz

IM3d

Bc

IM1


First, separate nonlinearities in static IV from capacitive effects

low freq. 10MHz.More graded channel profile shows better linearity in intermediate power regime.


At high power, the compressing non-linearity along the load-line will dominate; the curves merge. Lower Vgs two sweet-spots appear.

Realistic LDMOS: two sweet spots

-10 -5 0 5 10 15 20-90

-80

-70

-60

-50

-40

-30

-20

IM3d

Bc

IM1

Shift -50mV from gm3/gm min. gm3/gm min.

Ids (A)

Vds (V)


11/23/2010 GaN HEMT project 79

Lg=0.5um

GaN HEMT structureBackup: GaN HEMT structure

-7 -6 -5 -4 -3 -2 -1 0 10.0000

0.0002

0.0004

0.0006

0.0008

0.0010

0.0012

Id (A

/um

)

Vg (V)

w/o Hydrodynamics w/ Hydrodynamics

11/23/2010 80GaN HEMT project

Backup: Id‐Vgs, GaN HEMT

TCAD simulation results

-5 -4 -3 -2 -1 0 11E-7

1E-6

1E-5

1E-4

1E-3

Id (A

/um

)

Vg (V)


11/23/2010 81GaN HEMT project

-5 -4 -3 -2

-20

0

20

40

G

m3/

Gm

1

Vg (V)


Gm3/Gm1 min.:Vg=-4.9047V

Backup: Gm3/Gm1, GaN HEMT

11/23/2010 GaN HEMT project 82

0.01 0.11E-16

1E-14

1E-12

1E-10

1E-8

Id(A

)

Vg(V)

Id1 at f1 Id3 at 2f1-f2

GaN HEMTVd=28VVg=-4.91V (Gm3/Gm1 min.)

Backup: Linearity, GaN HEMT

• ΔN model

Backup: The origin of LF noise

8383

ΔN

one trap RTN

a lot of traps 1/f noise

time:

freq.:

time:

freq.:

Sid/Id2

Freq

Id

Time

Sid/Id2

Freq

Id

Time


Backup: Statistics

• Statistical results

84

About

12%

MOSFETs

show

RTN:

9%

Ig‐RTN,

2%

Id

‐RTN,

and 1%

Ig

‐/Id

‐RTN.

The

statistical

results

are

from

1000

devices

with

the

same

technology and structures.


• Ig

‐RTN

Backup: Gate bias

– Vg

increases: Time in high‐Ig

state increases.85

0.6 0.7 0.8 0.9 1.0 1.1 1.20.01

0.1

1

10

Vg (V)

Device 1 Device 2 Device 3 Device 4

5 .2 x 1 0 - 1 15 .6 x 1 0 - 1 16 .0 x 1 0 - 1 16 .4 x 1 0 - 1 1

3 .2 x 1 0 - 1 1

3 .6 x 1 0 - 1 1

0 5 1 0 1 5 2 0 2 51 .6 x 1 0 - 1 1

1 .8 x 1 0 - 1 1

2 .0 x 1 0 - 1 1

Ig (A

)

Time (s)

Vg=1V

Vg=0.9V

Vg=0.8V


Backup: TCAD

86

• Id

‐RTN: High gm bias condition

– TCAD simulations confirm the origin of RTN can be from one‐ trap/de‐trap.

Trap/de-trap


Backup: Motivation

11/09/2010 87C.‐Y. Chen UCB seminar

Device Noise

Bio‐implant systemIntegrated sensors

Portable electronics

Ultra‐low power circuits

Transistor reliability

Bio/silicon interfaces

SRAM yield

Noise:

key

issue

for

the

future

electronic

system development.

R. Jayaraman et al. IEEE T-ED, vol.36, no. 9, pp. 1773-1782, Sept., 1989.

Ener

gy (e

V)

Space (um)

H. Wong et al. IEEE T-ED, vol.37 no. 7, pp. 1743-1749, July, 1990.

L/H H/L

U-shape

– Space: from gate to Si can be low-high or high-low.

– Energy: distribution is a U-shape in log-scale.


Backup: Trap distribution (1 of 2)

– Vg dependence shows flat region in weak inversion regime.

– In the U-shape distribution Vg dependence is less sensitive compared with uniform distribution.

Y. Liu et al. SISPAD 2006, pp. 99-102, 2006.K. K. Hung et al. IEEE T-ED, vol.37, no. 5, pp. 1323-1333, May, 1990.

∝

1/Vov2flat


Backup: Trap distribution (2 of 2)• Vg

dependence

– Physical model

– Impedance field method (IMF)

devicetheinratcurrentInjected

electrodekthatnfluctuatioCurrentrAk

dvrSrAS sin )(2

[5] A. McWhorter, Semiconductor Surface Physics, PA, Univ. Pennsylvania Press,1957, pp. 207-208.[6] W. Shockley et al., Quantum Theory of Atoms, Molecules and Solid State, NY: Academic, 1966, pp. 537-563.


Backup: Numerical method (1 of 2)

• Hooge mobility fluctuation (Δμ

model)– Bulk phonon scattering

– Empirical equation

– Numerical approach: Post process

Hooge model is empirical the post process with simulated parameters/reasonable αH is used.

[7] F. N. Hooge, IEEE T-ED, vol.41, no. 11, pp. 1926-1935, Nov., 1994.9111/19/2010 C.‐Y. Chen UCB EE298‐12 Seminar

Backup: Numerical method (2 of 2)

The fluctuating oxide charge density △Qox is equivalent to a variation in the flat-band voltage

The fluctuation in the drain current yields

The first term in the parentheses is due to fluctuating number of inversion carriers and the second term to correlated mobility fluctuations.

Fluctuation of Num. Fluctuation of correlated mobility


Backup: Unified model (1 of 4)

The power spectral density of the flat-band voltage fluctuations is calculated by summing the contributions from all traps in the gate oxide.

Fermi‐Dirac distribution

x

z

y

Semiconductor



The product f(E)(1-f(E)) is sharply peaked around the quasi- Fermi level

If the Fermi-level is far above or below the trap level, the trap will be filled or empty.

All empty

All filled

Fluctuations

f(E) 1-f(E)



Lorentzian spectrum

The trapping time constant (quantum tunneling)

Tunneling attenuation length



• Numerical approach

j

SiHigh-κ

Different affinities and tunneling are considered

SiON

f=1Hz

f=1e4Hz

1/γ

SiO2 : 1×10-8 cm

HfO2 : 2.1×10-8 cm[9] Y. Liu et al. SISPAD 2006, pp. 99-102, 2006.


Backup: High‐κ

• Scaling trend: general trend

– SiO2 trap density is much smaller than that of HfO2 .

– 1/f noise increases much faster than the thermal noise when size scales down.


Backup: Noise scaling (1 of 2)

• Scaling trend: traps at gate edge

– High trap density in the gate edge region.

– In the scaled devices traps in the gate edge becomes important so Sid /Id2 increases significantly.

[14] Y. Yasuda et al., IEEE T-ED, vol.55, no. 1, pp. 417-422, Jan., 2008.9811/19/2010 C.‐Y. Chen UCB EE298‐12 Seminar

Backup: Noise scaling (2 of 2)

– Halo doping profiles suppress the short channel effect.

– The same amount of electrons greater Δ

Id in halo.

– Reduced inversion carrier density in the halo regions.

[8] Y. Liu et al. SISPAD 2006, pp. 99-102, 2006.9911/19/2010 C.‐Y. Chen UCB EE298‐12 Seminar

Backup: Halo doping

– The lowering of the 1/f noise: observed in the strong inversion regime.

– Traps and charges at the gate dielectric interface: better screened by a metal gatealleviate remote phonon scattering.

-

+

+

-

[15] E. Simoen et al., IEEE T-ED, vol.40, pp. 2054-2059, 1993.

Poly SiGeHigh-κ

(TiN)


Backup: Metal gate

• Dual channel behavior

[16] C.-Y. Chen et al., IEEE T-ED, vol.55, no.7, pp. 1741-1748, 2008.

-2.0 -1.5 -1.0 -0.5 0.0

1E-23

1E-22

1E-21

1E-20

S id

(A2 /

Hz)

Gate Voltage (V)

w/o layer dependence This work Measurements

Vd= -0.1VSiGe p-HMOS

n3-D

– Surface and buried channels have different Coulomb interactions.

– Both channels also have different material quality.


Backup: SiGe FET (1 of 2)

• Compact model

– Physics based compact model can simulate dual-channel behavior for SiGe FETs.

Vg

Vth_buried

Vth_surf

SiSiGe

SiSiGe

Thin body MOS

SiSi

SiGe

Si

SiGe

Surface channel Buried channelCase 1: low Vg

Case 2: Medium Vg

Case 3: High VgVth_surf

-2.0 -1.5 -1.0 -0.5 0.0 0.51E-12

1E-11

1E-10

1E-9

1E-8

1E-7

1E-6

1E-5

S id/

I d2

(1/H

z)

Vg(V)

TCAD Proposed model Measurements

SiGe p-HMOSVd=-0.1V

107 108 109

1E-8

1E-7

1E-6

1E-5

1E-4

1E-3

Sid

(A2 /

Hz)

F requency (Hz)

SiG e p-HM O S Si p-M O S


Backup: SiGe FET (2 of 2)

• Exponential tail in RTN

– The slope of Vth instability shows an exponential tail.

– The slope increases with technology scaling.[18] A. Ghetti et al., IEEE T-ED, vol.56, no.8, pp. 1746-1752, 2009.


Backup: Random Telegraph Noise (1 of 2)

• Body bias dependence: explain

– RTN: channel/gate dielectrics system in dynamic equilibrium.

– NBTI relaxation: perturbed system returning to the equilibrium.


Backup: Random Telegraph Noise (2 of 2)

• Switched MOS

– Large switch in gate can reduce 1/f noise.[19] A. P. Wel et al., IEEE JSSC, vol.42, no.3, pp. 540-550, 2007.


Backup: Switched bias

• RTNBackup: Temperature effect

1/f noise

[20] M. J. Deen et al. AIR conf. vol. 282, pp. 165-188, 1992.10611/19/2010 C.‐Y. Chen UCB EE298‐12 Seminar

Noise floor ~ 10-10Amps/rootHz Bandwidth ~ 1MHz

– The sensitivity is 2uA/V– High bandwidth mode is used.

SR 570 settings


Backup: 1/f noise characterization (1 of 4)

SR 760 settings

– Impedance ~ 1MΩ, 15pF– Bandwidth: DC to 100kHz

– The bandwidth of noise measurement is limited by SR760.

– Good for very low frequency measurements.



– Impedance ~ 1MΩ.– Bandwidth: 5Hz to 500MHz

– Convert high impedance to 50 Ω.

HP4396A

Active probe HP41800A

– Impedance ~ 50Ω.– Bandwidth: 2Hz to 1.8GHz

– Easy interface and high resolution.



On‐package measurements



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low frequency noise in advanced mos transistors...2010 ‐11‐19 low frequency noise in advanced...

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