low latency ethernet 10g mac intel® stratix® 10 fpga ip ... · 1. quick start guide. the low...

Low Latency Ethernet 10G MACIntel® Stratix® 10 FPGA IP DesignExample User Guide

Updated for Intel® Quartus® Prime Design Suite: 19.3

IP Version: 19.3.0

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Contents

1. Quick Start Guide............................................................................................................51.1. Directory Structure................................................................................................ 61.2. Generating the Design............................................................................................7

1.2.1. Procedure.................................................................................................71.2.2. Design Example Parameters........................................................................8

1.3. Compiling and Simulating the Design....................................................................... 91.3.1. Procedure.................................................................................................91.3.2. Testbench............................................................................................... 10

1.4. Changing Target Device in Hardware Design Example............................................... 111.4.1. Procedure............................................................................................... 11

1.5. Compiling and Testing the Design in Hardware.........................................................131.5.1. Procedure............................................................................................... 131.5.2. Hardware Setup.......................................................................................14

2. 10GBASE-R Ethernet Design Example........................................................................... 152.1. Features............................................................................................................. 152.2. Hardware and Software Requirements.................................................................... 152.3. Functional Description.......................................................................................... 16

2.3.1. Design Components................................................................................. 162.3.2. Clocking and Reset Scheme.......................................................................17

2.4. Simulation.......................................................................................................... 172.5. Hardware Testing.................................................................................................17

2.5.1. Test Cases.............................................................................................. 182.6. Interface Signals..................................................................................................202.7. Configuration Registers.........................................................................................20

3. 10M/100M/1G/2.5G/10G Ethernet Design Example.....................................................223.1. Features............................................................................................................. 223.2. Hardware and Software Requirements.................................................................... 223.3. Functional Description.......................................................................................... 22

3.3.1. Design Components................................................................................. 233.3.2. Clocking Scheme..................................................................................... 243.3.3. Reset Scheme......................................................................................... 243.3.4. Timing Constraints................................................................................... 25

3.4. Simulation.......................................................................................................... 263.5. Hardware Testing.................................................................................................26

3.5.1. Test Procedure.........................................................................................263.6. Interface Signals..................................................................................................293.7. Configuration Registers.........................................................................................29

4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature...................................... 314.1. Features............................................................................................................. 314.2. Hardware and Software Requirements.................................................................... 314.3. Functional Description.......................................................................................... 32


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4.4. Simulation.......................................................................................................... 364.4.1. Test Case—Design Example with the IEEE 1588v2 Feature.............................36

4.5. Hardware Testing.................................................................................................374.5.1. Test Procedure.........................................................................................38

4.6. Interface Signals..................................................................................................414.7. Configuration Registers.........................................................................................41

5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature.............................. 435.1. Features............................................................................................................. 435.2. Hardware and Software Requirements.................................................................... 435.3. Functional Description.......................................................................................... 43


5.4. Simulation.......................................................................................................... 485.4.1. Test Case—Design Example with the IEEE 1588v2 Feature.............................48

5.5. Hardware Testing.................................................................................................495.5.1. Changing to SFP+ Setting......................................................................... 505.5.2. Test Procedure.........................................................................................50


6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example............................ 556.1. Features............................................................................................................. 556.2. Hardware and Software Requirements.................................................................... 556.3. Functional Description.......................................................................................... 55

6.3.1. Design Components................................................................................. 576.3.2. Clocking Scheme..................................................................................... 596.3.3. Reset Scheme......................................................................................... 59

6.4. Simulation.......................................................................................................... 616.4.1. Test Case—Design Example with the IEEE 1588v2 Feature.............................616.4.2. Test Case—Design Example without the IEEE 1588v2 Feature........................ 62

6.5. Hardware Testing.................................................................................................636.5.1. Test Procedure.........................................................................................64


7. Interface Signals Description........................................................................................697.1. Clock and Reset Interface Signals.......................................................................... 697.2. Avalon-MM Interface Signals................................................................................. 707.3. Avalon-ST Interface Signals...................................................................................717.4. PHY Interface Signals........................................................................................... 737.5. Status Interface...................................................................................................747.6. IEEE 1588v2 Timestamp Interface Signals...............................................................747.7. Packet Classifier Interface Signals.......................................................................... 757.8. ToD Interface Signals........................................................................................... 77

8. Configuration Registers Description..............................................................................788.1. Register Access Definition..................................................................................... 788.2. Low Latency Ethernet 10G MAC............................................................................. 788.3. PHY................................................................................................................... 82

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8.3.1. 1G/2.5G/5G/10G Multi-rate PHY................................................................ 828.4. Transceiver Reconfiguration...................................................................................888.5. TOD...................................................................................................................88

9. Low Latency Ethernet 10G MAC Intel Stratix 10 FPGA IP Design Example UserGuide Archives.........................................................................................................90

10. Document Revision History for the Low Latency Ethernet 10G MAC Intel Stratix10 FPGA IP Design Example User Guide...................................................................91

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1. Quick Start GuideThe Low Latency 10G Ethernet (LL 10GbE) MAC Intel® FPGA IP core for Intel Stratix®

10 devices provides the capability of generating design examples for selectedconfigurations.

Figure 1. Development Stages for the Design Example

DesignExample

Generation

Compilation(Simulator)

FunctionalSimulation

Compilation(Quartus Prime)

HardwareTesting

Related Information

• 10GBASE-R Ethernet Design Example on page 15Provides details for the 10GBASE-R Ethernet design example.

• 10M/100M/1G/2.5G/10G Ethernet Design Example on page 22Provides details for the 10M/100M/1G/2.5G/10G Ethernet design example.

• 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature on page 31Provides details for the 1G/2.5G Ethernet design example.

• 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature on page 43Provides details for the 1G/2.5G/10G Ethernet design example with IEEE1588v2 feature.

• 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example on page 55Provides details for the 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernetdesign example.

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1.1. Directory Structure

Figure 2. Directory Structure for the Design Example

<Design Example>

rtl

altera_eth_multi_channel.sv

altera_eth_channel.sv

<Design Component>

<Design Component>

altera_eth_top.svaltera_eth_top.sdcaltera_eth_top.sof

altera_eth_top.qpfaltera_eth_top.qsfsimulation

models

hwtesting

system_console

output_files

ed_sim

cadence

mentor

synopsys

vcs

xcelium

Table 1. Directory and File Description

Directory/File Description

altera_eth_top.qpf Intel Quartus® Prime Pro Edition project file.

altera_eth_top.qsf Intel Quartus Prime Pro Edition settings file.

altera_eth_top.sv Design example top-level HDL.

altera_eth_top.sdc Synopsys Design Constraints (SDC) file.

rtl The folder that contains the design example synthesizable components.

rtl/altera_eth_10g_mac_base_r.sv

rtl/altera_10g_mac_base_r_wrap.v

Design example DUT top-level files for 10GBASE-R Ethernet design example.

rtl/altera_mge_rd.sv

rtl/altera_mge_channel.v

Design example DUT top-level files for the following Ethernet design examples:• 1G/2.5G with 1588v2 feature• 1G/2.5G/10G with IEEE 1588v2 feature• 10M/100M/1G/2.5G/10G

rtl/altera_mge_multi_channel.sv

rtl/altera_mge_channel.v

Design example DUT top-level files for 10M/100M/1G/2.5G/5G/10G (USXGMII)Ethernet design example.

rtl/<Design Component> The folder for each synthesizable component including Platform Designergenerated IPs, such as LL 10GbE MAC, PHY, and FIFO.

simulation/ed_sim/models The folder that contains the testbench files.

simulation/ed_sim/cadence

simulation/ed_sim/mentor

simulation/ed_sim/synopsys/vcs

simulation/ed_sim/xcelium

The folder that contains the simulation script. It also serves as a working area forthe simulator.

hwtesting/system_console The folder that contains system console scripts for hardware testing.

output_files The folder that contains Intel Quartus Prime Pro Edition output files includingIntel Quartus Prime Pro Edition compilation reports and design programing file(.sof file).

1. Quick Start Guide

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1.2. Generating the Design

1.2.1. Procedure

You can generate the design example from the IP Parameter Editor.

Start ParameterEditor

Specify IP Variationand Select Device

SelectDesign Parameters

InitiateDesign Generation

Specify Example Design

Figure 3. Example Design Tab

1. Select Tools ➤ IP Catalog to open the IP Catalog and select Low LatencyEthernet 10G MAC Intel FPGA IP.The IP parameter editor appears.

2. Specify a top-level name and the folder for your custom IP variation, and thetarget device. Click OK.

3. To generate a design example, select a design example preset from the Presetslibrary and click Apply. When you select a design, the system automaticallypopulates the IP parameters for the design.

The Parameter Editor automatically sets the parameters required to generate thedesign example. Do not change the preset parameters in the IP tab.

4. Specify the parameters in the Example Design tab.

5. Click the Generate Example Design button.

The software generates all design files in sub-directories. You require these files to runsimulation, compilation, and hardware testing.


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Related Information

Directory Structure on page 6Provides more information about the generated design example directories andfiles.

1.2.2. Design Example Parameters

Table 2. Parameters in the Example Design Tab

Parameter Description

Select Design Available example designs for the IP parameter settings. When youselect an example design from the Preset library, this field shows theselected design.

Example Design Files The files to generate for the different development phase.• Simulation—generates the necessary files for simulating the example

design.• Synthesis—generates the synthesis files. Use these files to compile

the design in the Intel Quartus Prime Pro Edition software forhardware testing and perform static timing analysis.

Generate File Format The format of the RTL files for simulation—Verilog or VHDL.

Select Board Supported hardware for design implementation. When you select anIntel FPGA development board, the Target Device is the one thatmatches the device on the Development Kit.If this menu is not available, there is no supported board for the optionsthat you select.Stratix 10 GX Signal Integrity H-Tile (Prod) Development Kit: Thisoption allows you to test the design example on the selected Intel FPGAIP development kit. This option automatically selects the Target Deviceto match the device on the Intel FPGA IP development kit. If your boardrevision has a different device grade, you can change the target device.Custom Development Kit: This option allows you to test the designexample on a third party development kit with Intel FPGA IP device, acustom designed board with Intel FPGA IP device, or a standard IntelFPGA IP development kit not available for selection. You can also select acustom device for the custom development kit.No Development Kit: This option excludes the hardware aspects forthe design example.

Change Target Device Select this parameter to display and select all devices for the Intel FPGAIP development kit.

Specify Number of Channels The number of Ethernet channels.For Intel Stratix 10 devices, the default number of channels is 2 and thisparameter is not selectable.

Analog Voltage VCCR_GXB and VCCT_GXB supply voltage for the Transceiver.Note: This option is only available from Intel Quartus Prime Pro Edition

version 17.0 onwards

Enable Native PHY Debug Master Endpoint(NPDME)

Turn on this option to enable the Transceiver Native PHY Debug MasterEndpoint (NPDME) feature.Note: This option is only available from Intel Quartus Prime Pro Edition

version 17.0 onwards


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1.3. Compiling and Simulating the Design

1.3.1. Procedure

You can compile and simulate the design by running a simulation script from thecommand prompt.

Change to Testbench Directory

Run<Simulation Script>

AnalyzeResults

1. At the command prompt, change the working directory to <Example Design>\simulation\ed_sim\<Simulator>.

2. If you change the target device in the hardware design example and regeneratethe IP component (refer to the Changing Target Device in Hardware DesignExample section), perform the steps in Updating PHY IP Design File Names onpage 9. Otherwise, skip this step.

3. Run the simulation script for the simulator of your choice.

Simulator Working Directory Command

ModelSim* <Example Design>/simulation/ed_sim/mentor vsim -c -do tb_run.tcl

VCS* <Example Design>/simulation/ed_sim/synopsys/vcs

sh tb_run.sh

NCSim <Example Design>/simulation/ed_sim/cadence sh tb_run.sh

Xcelium* <Example Design>/simulation/ed_sim/xcelium sh tb_run.sh

A successful simulation ends with the following message:

Simulation passed.

After successful completion, you can analyze the results.

Related Information

Changing Target Device in Hardware Design Example on page 11

1.3.1.1. Updating PHY IP Design File Names

If you change the target device in the hardware design example and regenerate the IPcomponent, the random string suffixes of the PHY IP component design file namesmay change.

To ensure proper simulation elaboration, follow these steps:

1. Open the simulation script for the simulator of your choice.


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Simulator Simulator Script

Modelsim <Example Design>/simulation/ed_sim/setup_scripts/common/modelsim_files.tcl

VCS <Example Design>/simulation/ed_sim/setup_scripts/common/vcs_files.tcl

<Example Design>/simulation/ed_sim/setup_scripts/common/vcsmx_files.tcl

NCSim <Example Design>/simulation/ed_sim/setup_scripts/common/ncsim_files.tcl

Xcelium <Example Design>/simulation/ed_sim/setup_scripts/common/xcelium_files.tcl

2. Edit the PHY IP design files names in the simulation script to match with theregenerated PHY IP component design file names.

Examples of the PHY IP design files names with random string suffix that need tobe updated:

• alt_mgbaset_phy_altera_xcvr_native_s10_htile_1921_dsmw74y.sv

• alt_xcvr_native_rcfg_opt_logic_dsmw74y.sv

• alt_mgbaset_phy_alt_mge_phy_1930_3oqbkgq.v

1921 and 1930 are IP versions. dsmw74y and 3oqbkgq are the random stringsthat specific to the Quartus version and transceiver tile type.

3. Save the file.

1.3.2. Testbench

Figure 4. Block Diagram of the Testbench

Avalon-MMControlRegister

Avalon-STTransmit

FrameGenerator

Avalon-STReceiveFrame

Monitor

EthernetPacket

Monitor

avalon_bfm_wrapper.sv

Avalon Driver

Channel 0

Channel 1

Ordinary Clock

EthernetPacket

Monitor

Loopbackon Serial

DUT

TX data

RX data

Testbench

Avalon-MM

Channel n-1

Channel n

.

.

.


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Table 3. Testbench Components

Component Description

Device under test (DUT) The design example.

Avalon driver Consists of Avalon-ST master bus functional models (BFMs). This driverforms the TX and RX paths. The driver also provides access to theAvalon-MM interface of the DUT.

Ethernet packet monitors Monitor TX and RX datapaths, and display the frames in the simulatorconsole.

1.4. Changing Target Device in Hardware Design Example

If you have selected Intel Stratix 10 GX Signal Integrity H-Tile (Production)Development Kit as your target device, the Low Latency Ethernet 10G MAC IntelFPGA IP core for Intel Stratix 10 devices generates a hardware example design fortarget device 1SX280HU1F50E2VG. This device may differ from the device on yourdevelopment kit.

1.4.1. Procedure

To change the target device in your hardware design example, follow these steps:

1. Launch the Intel Quartus Prime Pro Edition software and open the hardware testproject file /hardware_test_design/altera_eth_top.qpf.

2. On the Assignments menu, click Device. The Device dialog box appears.

3. In the Device dialog box, select 1SG280HU1F50E2VG (H-tile) or1SG280LU2F50E2VG (L-tile) in the target device table that matches the devicepart number on your development kit. Refer to the Stratix 10 GX Signal IntegrityDevelopment Kit link on the Intel website for more information.

4. A prompt appears when you select a device, as shown in the figure below. SelectNo to preserve the generated pin assignments and I/O assignments.

Figure 5. Intel Quartus Prime Prompt for Device Selection

5. If you select 1SG280LU2F50E2VG (L-Tile GX) as your target device, clickUpgrade IP Components in Project menu, select L-Tile/H-Tile TransceiverNative PHY Intel Stratix 10 FPGA IP from the list of IP components, and clickUpgrade in Editor. Regenerate this IP component.

Note: If you select 1SG280HU1F50E2VG (H-Tile GX) as your target device, skipthis step if you are using the same Quartus and IP version.

6. Perform full compilation of your design.


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You can now test the design on your hardware.

Note: No other pin assignment modifications are required for the design example. When yougenerate the design example targeting other Intel Stratix 10 development kits, referto the respective development kit user guides for pin assignment.


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1.5. Compiling and Testing the Design in Hardware

1.5.1. Procedure

You can compile and test the design in the supported Intel FPGA development kit.

Compile Designin Quartus Prime

Software

Set up Hardware Program Device Test Designin Hardware

1. Launch the Intel Quartus Prime Pro Edition software and open the design exampleproject file. Select Processing ➤ Start Compilation to compile the designexample.

The timing constraints for the design example and the design components areautomatically loaded during compilation.

2. Connect the development board to the host computer.

3. Launch the Clock Controller application, which is part of the development kit, andset new frequencies for the design example.

Note: For the frequencies to set, refer to the Hardware Testing section in therespective design example chapter.

4. In the Intel Quartus Prime Pro Edition software, select Tools ➤ Programmer toconfigure the FPGA on the development board using the generated .sof file.

5. Reset the system by pressing the PB0 push button.

6. In the Intel Quartus Prime software, select Tools ➤ System Debugging Tools ➤System Console to launch the system console.

7. Change the working directory to <Example Design>\hwtesting\system_console.

8. Initialize the design command list by running this command: source main.tcl.

Note: For a design example that does not provide the main.tcl file, refer to theHardware Testing section in the respective design example chapter.

You can now run any of the predefined hardware tests from the System Console.

Observe the test results displayed.

Related Information

Intel Stratix 10 GX Signal Integrity Development Kit Webpage


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https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-s10-transceiver-si.html


1.5.2. Hardware Setup

Figure 6. Block Diagram of the Hardware Setup

Stratix 10 GX Signal Integrity Development Board

JTAG TAPController

SystemController

Ethernet Frame Generation& Monitoring (Master) Ethernet Channel 0

Ethernet Frame Generation& Monitoring (Slave)

Ethernet Channel 1

Ethernet Frame Generation& Monitoring Ethernet Channel n - 1

Ethernet Frame Generation& Monitoring

Ethernet Channel n

Intel Stratix 10 FPGA

Intel SystemConsole

Software

PC

(1)

(2)

(1)(2)

Use this type of loopback to test IEEE 1588v2 features.Use this type of loopback to test features other than IEEE 1588v2. This loopback is different than the loopback usedfor simulating multiple channels.


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2. 10GBASE-R Ethernet Design ExampleThe 10GBASE-R Ethernet design example demonstrates an Ethernet solution for IntelStratix 10 devices using the LL 10GbE MAC Intel FPGA IP core, the native PHY IP core,and a small form factor pluggable (SFP+) module.

Generate the design example from the Example Design tab of the LL 10GbE IntelFPGA IP parameter editor.

2.1. Features

• Supports dual Ethernet channel operating at 10G using Intel Stratix 10 Native PHY.

• On the transmit and receive paths:

— Provides packet monitoring system.

— Reports Ethernet MAC statistics counter.

• Supports testing using different types of Ethernet packet transfer protocol.

2.2. Hardware and Software Requirements

Intel uses the following hardware and software to test the design example in a Linuxsystem:

• Intel Quartus Prime Pro Edition software

• ModelSim-AE, ModelSim-SE, NCSim (Verilog only), VCS, and Xcelium simulators

• For hardware testing:

— Stratix 10 GX Signal Integrity H-Tile (Production) Development Kit(1SX280HU1F50E2VG)

— Cables—SFP+ and fiber optic cable

Related Information

Analyzing and Debugging Designs with System Console

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2.3. Functional Description

Figure 7. Block Diagram—10GBASE-R Ethernet Design Example

Input Clock Reset

Avalon-STFIFOLL 10GbE MAC

PHY

Transceiver ResetController

TX/RXSerialData

Core fPLL ResetSynchronizer

Design Example

Adapter

Adapter

(altera_eth_multi_channel)

ATX PLL

address_decoder_channel

altera_eth_10g_mac_base_r_wrap

Generated with Platform DesignerGenerated with IP Catalog

S

S

Avalon-MMMasterS M

Avalon-MM Avalon-MMMasterS M

address_decoder_multi_channel

2.3.1. Design Components

Table 4. Design Components


LL 10GbE MAC The Low Latency Ethernet 10G MAC Intel FPGA IP core with the following configuration:• Speed: 10G• Datapath options: TX & RX• Enable ECC on memory blocks: Not selected• Enable 10GBASE-R register mode: Not selected• Enable supplementary address: Selected• Enable statistics collection: Selected• Statistics counters: Memory-based• TX and RX datapath Reset/Default To Enable: Selected• Use legacy XGMII Interface: Selected.• Use legacy Avalon Memory-Mapped Interface: Not Selected• Use legacy Avalon Streaming Interface: Not selected

PHY • The L-Tile/H-Tile Transceiver Native PHY Intel Stratix 10 FPGA IP configured for the 10GBASE-R protocol.

• The preset sets the PHY's TX FIFO MODE to Phase Compensation and RX FIFO MODE to10GBASE-R.


The Transceiver PHY Reset Controller Intel Stratix 10 FPGA IP core. Resets the transceiver.

Address decoder Decodes the addresses of the components.

Reset synchronizer Synchronizes the reset of all design components.

ATX PLL Generates a TX serial clock for the Intel Stratix 10 10G transceiver.

FIFO • Avalon® Streaming (Avalon-ST) single-clock and dual-clock FIFO.• Buffers the RX and TX data between the MAC IP core and the client.

continued...

2. 10GBASE-R Ethernet Design Example

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By default, the maximum packet length is supported up to 8000 bytes. You can configure theFIFO depth to increase the packet length.

Core fPLL Generates 312.5 MHz and 156.25 MHz clocks to the MAC IP core, reset synchronizer, Ethernettraffic controller, address decoder and FIFO.

Related Information

• Low Latency Ethernet 10G MAC User GuideProvides more information about the MAC parameters.

• 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with KR FEC VariantsProvides more information about the PHY parameters.

2.3.2. Clocking and Reset Scheme

Figure 8. Clocking and Reset Scheme for 10GBASE-R Design Example

Generator andChecker

reset_n clk

FIFO

rx_sc_fifo_clk_reset_reset tx_sc_fifo_clk_reset_reset

rx_sc_fifo_clk_clk tx_sc_fifo_clk_clk

Avalon-ST Adapteravalon_st_rx_clk_312avalon_st_rx_312_reset_n

avalon_st_tx_clk_312avalon_st_tx_312_reset_n

avalon_st_rx_clk_156avalon_st_rx_156_reset_n

avalon_st_tx_clk_156avalon_st_tx_156_reset_n

LL 10GbE MAC

csr_clkcsr_rst_n

rx_312_5_clkrx_156_25_clk

rx_rst_n

tx_312_5_clktx_156_25_clk

tx_rst_n PHY

reconfig_clkrx_cdr_refclk0reconfig_reset

tx_xcvr_half_clktx_serial_clk

tx_clkoutrx_clkout

Address Decodertx_xcvr_half_clk_clksync_tx_half_rst_reset_n

clk_csr_clkcsr_reset_n

rx_xcvr_clk_clksync_rx_rst_reset_n

tx_xcvr_clk_clksync_tx_rst_reset_n

ResetController

reset clock

ResetSynchronizer

ATX PLL

125 MHz csr_clk

ref_clk_clk322.265625 MHz

master_reset_n

fPLLoutclk_0

outclk_1

Avalon-MM Adaptersl_clocksl_reset

ms_clockms_reset

Transceiver

2.4. Simulation

At the end of the simulation, the simulator generates the statistics of TX and RXpackets in the Transcript window.

Related Information

Compiling and Simulating the Design on page 9Provides information on the procedure and testbench.

2.5. Hardware Testing

Follow the procedure at the provided link to test the design example in the selectedhardware.


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https://www.intel.com/content/www/us/en/programmable/documentation/bhc1395127830032.html#bhc1395127588036

https://www.intel.com/content/www/us/en/programmable/documentation/joc1445446725697.html#joc1446490105251


In the Clock Controller application, which is part of the development kit, set thefollowing frequencies:

• Y1—322.265625 MHz

• U5, OUT 8—125 MHz

Related Information

• Compiling and Testing the Design in Hardware on page 13More information on the procedure and hardware setup.

• Clock ControllerMore information on using the Clock Controller application.

2.5.1. Test Cases

You can run any of the following tests from the System Console.

Table 5. Hardware Test Cases

Test Case Command Description

SFP+ loopback source gen_conf.tcl The generator generates and sends about 100 000 packets. Wait30 seconds for it to complete its tasks.

source monitor_conf.tcl The monitor checks the number of good and bad packetsreceived.

source show_stats.tcl This script displays the values of the statistics counters.

Avalon-ST loopback source loopback_conf.tcl This command enables the Avalon-ST loopback. This test is usedwith an external tester such as Spirent tester.

After the test is completed, observe the output displayed in the System Console.

Figure 9. Sample Test Output—Ethernet Packet Monitor


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Figure 10. Sample Test Output—Statistics Counters


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2.6. Interface Signals

Figure 11. Interface Signals of the 10GBASE-R Ethernet Design Example

10BASE-R Ethernet Design Example

PHY Interface

tx_ready_export[n]rx_ready_export[n]block_lock[n]atx_pll_locked tx_serial_data[n]

rx_serial_data[n]

Clock andReset

csr_clk

rx_rst_n

tx_rst_n

csr_rst_n

ref_clk_clktx_clk_312 tx_clk_156

avalon_st_rxstatus_valid[n]avalon_st_rxstatus_data[n][40]avalon_st_rxstatus_error[n][7]

Avalon-ST ReceiveStatus Interface

avalon_st_rx_endofpacket[n]avalon_st_rx_startofpacket[n]

avalon_st_rx_valid[n]avalon_st_rx_ready[n]avalon_st_rx_error[n][6]avalon_st_rx_data[n][32]avalon_st_rx_empty[n][2]

Avalon-ST ReceiveData Interface

Avalon-ST TransmitStatus Interface

avalon_st_txstatus_valid[n]avalon_st_txstatus_data[n][40]avalon_st_txstatus_error[n][7]

Avalon-ST TransmitFlow Control Interface

avalon_st_pause_data[n][2]

Avalon-ST TransmitData Interface

avalon_st_tx_startofpacket[n]avalon_st_tx_endofpacket[n]avalon_st_tx_valid[n]avalon_st_tx_ready[n]avalon_st_tx_error[n]avalon_st_tx_data[n][32]avalon_st_tx_empty[n][2]

link_fault_status_xgmii_rx_data[2]

rx_clk_312 rx_clk_156

Avalon-MMInterface

mac_csr_read[n]mac_csr_readdata[n][32]

mac_csr_write[n]mac_csr_writedata[n][32]

mac_csr_address[n][10]mac_csr_waitrequest[n]

phy_csr_read[n]phy_csr_readdata[n][32]

phy_csr_write[n]phy_csr_writedata[n][32]

phy_csr_address[n][11]phy_csr_waitrequest[n]

Status Interface

n : Number of channels

Related Information

Interface Signals Description on page 69For more information on each interface signal.

2.7. Configuration Registers

You can access the 32-bit configuration registers of the design components throughthe Avalon-MM interface.

Table 6. Register Map

Byte Offset Block

0x0000_0000 – 0x0001_CFFF Reserved

0x0001_D000 – 0xFFFF_FFFF Client Logic

Channel 0

0x0000_0000 MAC

0x0000_8000 PHY

0x0000_d400 RX SC FIFO

0x0000_d600 TX SC FIFO

0x0000_c000 Packet Generator and Checker

continued...


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Byte Offset Block

Channel 1

0x0001_0000 MAC

0x0001_8000 PHY

0x0001_d400 RX SC FIFO

0x0001_d600 TX SC FIFO

0x0001_c000 Packet Generator and Checker

Related Information

Configuration Registers Description on page 78For more information on each configuration register.


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3. 10M/100M/1G/2.5G/10G Ethernet Design ExampleThe 10M/100M/1G/2.5G/10G Ethernet design example demonstrates an Ethernetsolution for Intel Stratix 10 using the LL 10GbE MAC Intel FPGA IP core operating at10M, 100M, 1G, 2.5G, and 10G.


3.1. Features

• Supports dual Ethernet channel operating at 10M, 100M, 1G, 2.5G, and 10G usingIntel Stratix 10 Multi-rate PHY.











— Cables— SFP+ and fiber optic cable

Related Information



The design example consists of various components. The following block diagramshows the design components and the top-level signals of the design example.

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Figure 12. Block Diagram—10M/100M/1G/2.5G/10G Ethernet Design Example

1G Input ClockReset

AddressDecoder

S

M

Avalon-MM

LL 10GbE MACS

TX/RXSerialData

Ethernet channel 0..(n-1)

Transceiver Reconfig

Avalon-ST

Design Example

(alt_mge_channel)

(alt_mge_rd)

Avalon-MM MuxTransceiver

ReconfigS

TransceiverReset

Controller

PHYS

M

M

.

.

.

ATX PLL(10G)

ATX PLL(2.5G)

10G Input Clock

fPLL(1G)





LL 10GbE MAC The Low Latency Ethernet 10G MAC Intel FPGA IP core with the following configuration:• Speed: 10M/100M/1G/2.5G/10G• Datapath options: TX & RX• Enable ECC on memory blocks: Not selected• Enable supplementary address: Selected• Enable statistics collection: Selected• Statistics counters: Memory-based• TX and RX datapath Reset/Default To Enable: Selected• All Legacy Ethernet 10G MAC Interfaces options: Selected

PHY The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP with the followingconfiguration:• Speed: 1G/2.5G/10G• SGMII bridge: Selected• Connect to MGBASE-T PHY: Selected• Connect to NBASE-T PHY: Not selected• PHY ID (32 bit): 0x00000000• VCCR_GXB and VCC_GXB supply voltage for the Transceiver: 1_0V• Reference clock frequency for 10GbE (MHz): 644.53125• Selected TX PMA local clock division factor for 1 GbE: 1• Selected TX PMA local clock division factor for 2.5 GbE: 1• Enable Native PHY Debug Master Endpoint: Not selected• Enable capability registers: Not selected• Enable control and status registers: Not selected• Enable PRBS soft accumulators: Not selected

continued...

3. 10M/100M/1G/2.5G/10G Ethernet Design Example

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Transceiver Reset Controller The Transceiver PHY Reset Controller Intel FPGA IP core. Resets the transceiver.

Address Decoder Decodes the addresses of the components.

Avalon-MM Mux TransceiverReconfig

Provides the transceiver reconfig block and system console access to the Avalon-MMinterface of the PHY.

Transceiver Reconfig Reconfigures the transceiver channel speed from 1G to 2.5G, or to 10G, and vice versa.

ATX PLL Generates a TX serial clock for the Intel Stratix 10 2.5G and 10G transceiver.

fPLL Generates a TX serial clock for the Intel Stratix 10 1G transceiver.

Related Information

Low Latency Ethernet 10G MAC User GuideProvides more information about the MAC parameters.

3.3.2. Clocking Scheme

Figure 13. Clocking Scheme for 10M/100M/1G/2.5G/10G Ethernet Design Example

MAC PHY


1G/2.5G/10GReconfiguration

Block

Channel 0

MAC PHY

Channel 1

2.5G PLL

1G PLL

Design Example

125 MHzReference

Clock

User Logic

User Logic

CSR Clock2.5G TXSerial Clock

1G TXSerial Clock

10G TXSerial Clock

PLL

125 MHz Reference Clock

2.5G TX Serial Clock (1562.5 Mbps)

1G TX Serial Clock (625 Mbps)HSSI TX Clock Out 62.5 MHz at 1G, 156.25 MHz at 2.5G125 MHz CSR Clock

156.25 MHz MAC Clock

MAC Clock CDR Reference Clocks

CDR Reference Clock

10G PLL

644.53125 MHzReference

Clock

10G TX Serial Clock (5156.25 Mbps)644.53125 MHz Reference Clock

3.3.3. Reset Scheme

The global reset signal of the design example is asynchronous and active-high.Asserting this signal resets all channels and their components. Upon power-up, resetthe design example.


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Figure 14. Reset Scheme for 10M/100M/1G/2.5G/10G Ethernet Design Example

MAC PHY



Block

Channel 0

MAC PHY

Channel 1

Design Example

User Logic

Global ResetAnalog Reset

Digital Reset

Global Reset

Reconfiguration Done (triggers reset)

User Logic

3.3.4. Timing Constraints

When you configure the PHY in 1G/2.5G/10G (MGBASE-T) configuration, Intelrecommends that you refer to the Timing Constraints section of 1G/2.5G/5G/10GMulti-rate Ethernet PHY Intel Stratix 10 FPGA IP User Guide for details on the timingconstraint examples.

In addition, you can set false path from native PHY 10G clock to Low Latency (LL)Ethernet 10G (10GbE) MAC logic and vice versa. Since the LL 10GbE MAC logic is notrunning 10G clock, you do not need to ensure timing closure for LL 10GbE MACdatapath at 10G clock. For example:

set_false_path -from [get_clocks \$profile2_clk] \\ -to [get_registers *|alt_em10g32:*|*]set_false_path -from [get_registers *|alt_em10g32:*|*] \\ -to [get_clocks \$profile2_clk]

where the path indicated by profile2 is associated to the native PHY 10G clockwhereas the alt_em10g32 path indicates the LL 10GbE MAC logic.

Related Information

1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel Stratix 10 FPGA IP User Guide


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https://www.intel.com/content/www/us/en/programmable/documentation/dto1486572140811.html#yoq1490121069787


3.4. Simulation

The simulation test case performs the following steps:

1. Starts up the example design with an operating speed of 10 Gbps.

2. Configures the MAC, PHY, and FIFO buffer for both channels.

3. Waits until the design example asserts the channel_tx_ready andchannel_rx_ready signals for both channels.

4. Sends the following packets:

• 64-byte packet

• 1518-byte packet

• 100-byte packet

5. Repeats steps 2 to 4 for 2.5G, 1G, 100M, and 10M.

When simulation ends, the values of the MAC statistics counters are displayed in thetranscript window. The transcript window also displays PASSED if the RX Avalon-STinterface of channel 0 received all packets successfully, all statistics error counters arezero, and the RX MAC statistics counters are equal to the TX MAC statistics counters.

Related Information





• Y1— 644.53125 MHz

• U5, OUT 1—125 MHz

• U5, OUT 8—125 MHz

Related Information



3.5.1. Test Procedure

Follow these steps to test the design examples in hardware:

1. Run the following command in the system console to start the test.

TEST_EXT_LB <channel> <speed> <burst_size>

Example: TEST_EXT_LB 0 10G 80000000


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Table 8. Command Parameters

Parameter Valid Values Description

channel 0, 1 The channel number to test.

speed 1G, 2.5G, 10G The PHY speed.

burst_size An integer value The number of packets to generate for the test.

2. When the test is completed, observe the output displayed. The following diagramsshow excerpts of the output, which shows that the Ethernet packet monitor blockreceives the same number of packets generated without error, and the TX and RXstatistics counters.



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Figure 17. Interface Signals of the Design Example

MAC RX

10M/100M/1G/2.5G/10G Ethernet Design Example

avalon_st_rx_status_valid[n]avalon_st_rx_status_data[n][40]avalon_st_rx_status_error[n][7]






avalon_st_tx_status_valid[avalon_st_tx_status_data[n][40]avalon_st_tx_status_error[n][7]

n]





Avalon-MM Interface

Clock andReset

csr_clk

refclk_10g

mac_clk

reset

tx_digitalreset[n]rx_digitalreset[n]

rx_pma_clkout

mac64b_clk

refclk_1g2p5g

n: Number of channels

PHY Interface rx_serial_data[n]tx_serial_data[n]

led_link[n]

led_char_err[n]led_disp_err[n]led_an[n]

channel_tx_ready[n]channel_rx_ready[n]

rx_block_lock[n]

csr_mac_read[n]csr_mac_readdata[n][32]

csr_mac_write[n]csr_mac_writedata[32]

csr_mac_address[n][10]csr_mac_waitrequest[n]

csr_phy_read[n]csr_phy_readdata[n][32]

csr_phy_write[n]csr_phy_writedata[32]csr_phy_address[n][11]

csr_phy_waitrequest[n]

csr_rcfg_readcsr_rcfg_readdata[32]

csr_rcfg_writecsr_rcfg_writedata[32]

csr_rcfg_address[2]

(LL 10GbE MAC)

Avalon-MM Interface(1G/2.5G/10G Multi-rate Ethernet PHY)

Avalon-MM Interface(Reconfiguration)

Status Interface

led_panel_link[n]

Related Information





Byte Offset Block

0x00_0000 Transceiver Reconfiguration

0x00_4000 Reserved

Channel 0

0x01_0000 MAC

0x01_8000 PHY

0x01_A000 Native PHY Reconfiguration

Channel 1

0x02_0000 MAC

0x02_8000 PHY

continued...


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Byte Offset Block


Traffic Controller

0x10_0000 Traffic Controller

Related Information



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4. 1G/2.5G Ethernet Design Example with IEEE 1588v2Feature

The 1G/2.5G Ethernet design example with the IEEE 1588v2 feature demonstrates anEthernet solution for Intel Stratix 10 devices using the LL 10GbE MAC Intel FPGA IPcore operating at 1G and 2.5G.


4.1. Features

• Supports dual Ethernet channel operating at 1G and 2.5G using Intel Stratix 10Multi-rate PHY.












Related Information


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Figure 18. Block Diagram—1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature

Avalon-MM

S

alt_mge_channel

PTP PacketClassifier

LL 10GbEMAC

S

PHYS

LocalTOD

STODSync

Pulse perSecond

alt_mge_channel

TransceiverReset

ControllerS

I/O PLL

MasterTOD

S

Pulse perSecond

Avalon-MMMultiplexerTransceiver

Reconfiguration

S

TransceiverReconfiguration

S

Reset Input Clock

Master PulsePer Second

TX/RX SerialData

1G/2.5G PulsePer Second

Avalon-ST

alt_mge_rd_addrdec_mch

Avalon-MMMaster

S M

altera_eth_top


alt_mge_rd

CSR Clock

ATX PLL fPLL

CorefPLL




LL 10GbE MAC The Low Latency Ethernet 10G MAC Intel FPGA IP core with the following configuration:• Speed: 1G/2.5G• Datapath options: TX & RX• Enable ECC on memory blocks: Not selected• Enable supplementary address: Selected• Enable statistics collection: Selected• Statistics counters: Memory-based• TX and RX datapath Reset/Default To Enable: Selected• All Legacy Ethernet 10G MAC Interfaces options: SelectedFor the design example with the IEEE 1588v2 feature, the following additional parametersare configured:• Enable time stamping: Selected• Enable PTP one-step clock support: Selected• Timestamp fingerprint width: 4• Time Of Day format: Enable both 96b and 64b Time of Day Format

PHY The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP with the followingconfiguration:

continued...

4. 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature

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• Speed: 1G/2.5G• Enable SGMII bridge: Not selected• Enabled IEEE 1588 Precision Time Protocol: Selected• PHY ID (32 bit): 0x00000000• VCCR_GXB and VCC_GXB supply voltage for the Transceiver: 1_0V• Selected TX PMA local clock division factor for 1 GbE: 1• Selected TX PMA local clock division factor for 2.5 GbE: 1• Enable Native PHY Debug Master Endpoint: Not selected• Enable capability registers: Not selected• Enable control and status registers: Not selected• Enable PRBS soft accumulators: Not selected

Transceiver Reset Controller The Transceiver PHY Reset Controller Intel Stratix 10 FPGA IP core. Resets the transceiver.


Provides the transceiver reconfig block and system console access to the PHY's Avalon-MMinterface.

Transceiver Reconfig Reconfigures the transceiver channel speed from 1 Gbps to 2.5 Gbps, and vice versa.

ATX PLL Generates a TX serial clock for the Intel Stratix 10 2.5G transceiver.


Core fPLL Generates 156.25 MHz clocks to MAC IP core, reset synchronizer, Ethernet traffic controller,PTP packet classifier, and address decoder.

Design Components for the IEEE 1588v2 Feature

IO PLL Generates the clocks for the 1588 design components.

Master Time-of-Day (TOD) The master TOD for all channels.

TOD Synch Synchronizes the master TOD to all local TODs.

Local TOD The TOD for each channel.

Master Pulse Per Second(PPS)

The master PPS. Returns pulse per second (pps) for all channels.

PPS The slave PPS. Returns pulse per second (pps) for each channel.

PTP Packet Classifier Decodes the packet type of incoming PTP packets and returns the decoded information tothe LL 10GbE MAC Intel FPGA IP core.

Related Information

Low Latency Ethernet 10G MAC User GuideProvides more information about the MAC parameters.


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Figure 19. Clocking Scheme for 1G/2.5G Ethernet Design Example with IEEE 1588v2Feature

MACClock

125 MHzCSR Clock


MAC

PHY

TOD 2.5G SyncTOD 2.5G PPS 2.5G

TOD 1G SyncTOD 1G PPS 1G

UserLogic

Channel N

AddressDecoder

TransceiverReset

Controller

1G/2.5GReconfiguration

Block1G fPLL

2.5GATX PLL

SamplingIOPLL

MasterToD

MasterPPS

Reference Design

125 MHzReference

Clock

Reference Clock (125 MHz)2.5G TX Serial Clock (1562.5 MHz)1G TX Serial Clock (625 MHz)HSSI TX Clock Out: 62.5 MHz at 1G, 156.25 MHz at 2.5G

CSR Clock (125 MHz)Sampling Clock (53.33 MHz)Sampling Clock (80 MHz)MAC Clock (156.25 MHz)

HSSI TX Clock In: 62.5 MHz at 1G, 156.25 MHz at 2.5G

CorePLL

4.3.3. Reset Scheme

The global reset signal of the design example is asynchronous and active-low.Asserting this signal resets all channels and their components. Upon power-up, resetthe design example.


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Figure 20. Reset Scheme for 1G/2.5G Ethernet Design Example with IEEE 1588v2Feature


MAC

PHY

TOD 2.5G SyncTOD 2.5G PPS 2.5G

TOD 1G SyncTOD 1G PPS 1G

UserLogic

Channel N

AddressDecoder

TransceiverReset

Controller

1G/2.5GReconfiguration

Block1G fPLL

2.5GATX PLL

SamplingIOPLL

TODMaster

PPSMaster

Design Example

Global Reset

Digital ResetDigital/Analog Reset Stat Analog Reset

Reconfiguration Done(to trigger reset after reconfiguration)

GlobalReset


When you configure the PHY in 1G/2.5G configuration, Intel recommends that yourefer to the Timing Constraints section of 1G/2.5G/5G/10G Multi-rate Ethernet PHYIntel Stratix 10 FPGA IP User Guide for details on the timing constraint examples.

When the IEEE 1588v2 feature is enabled for 1G/2.5G PHY configuration, add thefollowing constraints to the timing constraint file:

• Set false path from native PHY 1G clock to 2.5G 1588 logic and vice versa. Sincethe 2.5G 1588 logic is not running the native 1G clock, you do not need to ensuretiming closure for LL 10GbE MAC data path at 1G clock. For example:

set_false_path -from [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile0|*}] \ -to [get_registers {*|alt_mge_1588_tod_2p5g:*|* \ *|alt_mge_1588_tod_sync_*_2p5g:*|*}]set_false_path -from [get_registers {*|alt_mge_1588_tod_2p5g:*|* \ *|alt_mge_1588_tod_sync_*_2p5g:*|*}] \ -to [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile0|*}]

where the path indicated by profile0 is associated to the native PHY 1G clock,whereas the alt_mge_1588_tod_2p5g and alt_mge_1588_tod_sync_*_2p5gpaths indicate the 2.5G 1588 logic.

• Set false path from native PHY 2.5G clock to 1G 1588 logic and vice versa. Sincethe 1G 1588 logic is not running the native 2.5G clock, you do not need to ensuretiming closure for LL 10GbE MAC data path at 2.5G clock. For example:

set_false_path -from [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile1|*}] \ -to [get_registers {*|alt_mge_1588_tod_1g:*|* \ *|alt_mge_1588_tod_sync_*_1g:*|*}]set_false_path -from [get_registers {*|alt_mge_1588_tod_1g:*|* \


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*|alt_mge_1588_tod_sync_*_1g:*|*}] \ -to [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile1|*}]

where the path indicated by profile1 is associated to the native PHY 2.5G clock,whereas the alt_mge_1588_tod_1g and alt_mge_1588_tod_sync_*_1gpaths indicate the 1G 1588 logic.

Related Information


4.4. Simulation

Related Information


4.4.1. Test Case—Design Example with the IEEE 1588v2 Feature


1. Starts up the design example with an operating speed of 2.5G.


3. Waits until the design example asserts the channel_tx_ready andchannel_rx_ready signals for each channel.


• Non-PTP

• No VLAN, PTP over Ethernet, PTP Sync Message, 1-step PTP

• VLAN, PTP over UDP/IPv4, PTP Sync Message, 1-step PTP

• Stacked VLAN, PTP over UDP/IPv6, PTP Sync Message, 2-step PTP

• No VLAN, PTP over Ethernet, PTP Delay Request Message, 1-step PTP

• VLAN, PTPover UDP/IPv4, PTP Delay Request Message, 2-step PTP

• Stacked VLAN, PTP over UDP/IPv6, PTP Delay Request Message, 1-step PTP

5. Repeats steps 2 to 4 for 1G.



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Figure 21. Sample Simulation Output




• U5, OUT 0—125 MHz

• U5, OUT 8—125 MHz

Related Information




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Example: TEST_EXT_LB 0 2.5G 1000000000




speed 1G, 2.5G The PHY speed.




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Figure 24. Interface Signals of the 1G/2.5G Ethernet Design Examples with IEEE 1588v2Feature

MAC RX

1G/2.5G Ethernet Design Example with 1588v2 Feature

avalon_st_rxstatus_valid[n]avalon_st_rxstatus_data[n][40]avalon_st_rxstatus_error[n][7]






avalon_st_txstatus_valid[n]avalon_st_txstatus_data[n][40]avalon_st_txstatus_error[n][7]





Avalon-MM Interface

Clock andReset

csr_clk

refclkmac_clk

reset

tx_digital_reset[n]rx_digital_reset[n]

rx_pma_clkout

rx_digital_reset_stat[n]

IEEE 1588v2Time-Stamp

Interface

tx_egress_timestamp_96b_valid[n]tx_egress_timestamp_96b_data[n][96]tx_egress_timestamp_96b_fingerprint[n][f]tx_egress_timestamp_64b_valid[n]tx_egress_timestamp_64b_data[n][64]tx_egress_timestamp_64b_fingerprint[n][f]rx_ingress_timestamp_96b_valid[n]rx_ingress_timestamp_96b_data[n][96]rx_ingress_timestamp_64b_valid[n]rx_ingress_timestamp_64b_data[n][64]

n: Number of channelsf: Timestamp fingerprint width

master_pulse_per_secondstart_tod_sync[n]

pps[n]TOD Interface

Packet ClassifierInterface

tx_egress_timestamp_request_in_valid[n]tx_egress_timestamp_request_in_fingerprint[n][f]

clock_operation_mode_mode[n][2]pkt_with_crc_mode[n]

tx_ingress_timestamp_valid[n]tx_ingress_timestamp_96b_data[n][96]tx_ingress_timestamp_64b_data[n][64]

tx_ingress_timestamp_format[n]


led_char_err[n]led_disp_err[n]led_an[n]channel_tx_ready[n]

led_link[n]

channel_rx_ready[n]




csr_master_tod_waitrequest[n]

csr_master_tod_read[n]csr_master_tod_readdata[n][32]

csr_master_tod_write[n]csr_master_tod_writedata[n][32]

csr_master_tod_address[n][4]


csr_phy_write[n]csr_phy_writedata[32]

csr_phy_address[n][11]csr_phy_waitrequest[n]

csr_rcfg_read[n]csr_rcfg_readdata[32]

csr_rcfg_write[n]csr_rcfg_writedata[32]

csr_rcfg_address[2]csr_native_phy_rcfg_read

csr_native_phy_rcfg_readdata[32]csr_native_phy_rcfg_write

csr_native_phy_rcfg_writedata[32]

csr_native_phy_rcfg_waitrequestcsr_native_phy_rcfg_address[10]

(LL 10GbE MAC)

Avalon-MM Interface(1G/2.5G/10G Multi-rate Ethernet PHY)

Avalon-MM Interface(Reconfiguration)

Avalon-MM Interface(Native PHY Reconfiguration)

Avalon-MM Interface(Master ToD Clock)

Status Interface

Related Information





Byte Offset Block


0x00_4000 TOD Master

continued...


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Byte Offset Block

Channel 0

0x01_0000 MAC

0x01_8000 PHY


Channel 1

0x02_0000 MAC

0x02_8000 PHY


Traffic Controller


Related Information



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5. 1G/2.5G/10G Ethernet Design Example with IEEE1588v2 Feature

The 1G/2.5G/10G Ethernet design example with the IEEE 1588v2 featuredemonstrates an Ethernet solution for Intel Stratix 10 using the LL 10GbE MAC IntelFPGA IP core operating at 1G, 2.5G, and 10G.


5.1. Features

• Supports dual Ethernet channel operating at 1G, 2.5G, and 10G using Intel Stratix10 Multi-rate PHY.












Related Information




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Figure 25. Block Diagram—1G/2.5G/10G Ethernet Design Example with IEEE 1588v2Feature

Avalon-MM

S

alt_mge_channel


LL 10GbE MAC

S

PHYS

LocalTOD

S TODSync

Pulse perSecond

alt_mge_channel

TransceiverReset

ControllerS Master

TODS

Pulse perSecond

Avalon-MMMultiplexerTransceiver

Reconfiguration

S

TransceiverReconfiguration

S

Reset 1G/2.5G/10G Core Reference Clocks


TX/RX SerialData

1G/2.5G/10G Pulse Per Second

Avalon-ST

alt_mge_rd_addrdec_mch

Avalon-MMMaster

S M

altera_eth_top

Generated with IP CatalogGenerated with Platform Designer

alt_mge_rd

CSR Clock

ATXPLL

ATXPLL

fPLL fPLL fPLL

CorefPLL




LL 10GbE MAC The Low Latency Ethernet 10G MAC Intel FPGA IP core with the following configuration:• Speed: 1G/2.5G/10G• Datapath options: TX & RX• Enable ECC on memory blocks: Not selected• Enable supplementary address: Selected• Enable statistics collection: Selected• Statistics counters: Memory-based• TX and RX datapath Reset/Default To Enable: Selected• All Legacy Ethernet 10G MAC Interfaces options: SelectedFor the design example with the IEEE 1588v2 feature, the following additional parametersare configured:• Enable time stamping: Selected• Enable PTP one-step clock support: Selected• Timestamp fingerprint width: 4• Time Of Day format: Enable both 96b and 64b Time of Day Format

PHY The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP with the followingconfiguration:• Speed: 1G/2.5G/10G• Enable SGMII bridge: Not selected• Enabled IEEE 1588 Precision Time Protocol: Selected

continued...

5. 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2 Feature

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• Connect to MGBASE-T PHY: Selected• Connect to NBASE-T PHY: Not selected• PHY ID (32 bit): 0x00000000• VCCR_GXB and VCC_GXB supply voltage for the Transceiver: 1_0V• Reference clock frequency for 10GbE (MHz): 644.53125• Selected TX PMA local clock division factor for 1 GbE: 1• Selected TX PMA local clock division factor for 2.5 GbE: 1• Enable Native PHY Debug Master Endpoint: Not selected• Enable capability registers: Not selected• Enable control and status registers: Not selected• Enable PRBS soft accumulators: Not selected



Provides the transceiver reconfig block and system console access to the PHY's Avalon-MMinterface.

Transceiver Reconfig Reconfigures the transceiver channel speed from 1G to 2.5G, or to 10G, and vice versa.

ATX PLL Generates a TX serial clock for the Intel Stratix 10 2.5G and 10G transceiver.



ToD Sampling fPLL Generates the clocks for the 1588 design components.

Master ToD The master ToD for all channels.

ToD Synch Synchronizes the master ToD to all local ToDs.

Local ToD The ToD for each channel.

Master PPS The master PPS. Returns pulse per second (pps) for all channels.





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Figure 26. Clocking Scheme for 1G/2.5G/10G Ethernet Design Example with IEEE1588v2 Feature

mac64b_clk

125 MHzcsr_clk


MAC

PHY

ToD 2.5G PPS 2.5G

ToD 1G PPS 1G

UserLogic

Channel N

AddressDecoder

TransceiverReset

Controller


Block

10GATX PLL

2.5GATX PLL

ToDSampling

fPLL

MasterToD

MasterPPS

Design Example

644.53125 MHzrefclk_10g

refclk_10g (644.53125 MHz)refclk_1g2p5g (125 MHz)refclk_core (125 MHz)xcvr_pll_10g_serial_clk (5156.25 MHz)

xcvr_pll_1g_serial_clk (625 MHz)gmii16b_tx_clk (62.5 MHz [1G], 156.25 MHz [2.5G])gmii16b_rx_clk (62.5 MHz [1G], 156.25 MHz [2.5G])csr_clk (125 MHz)

xcvr_pll_2p5g_serial_clk (1562.5 MHz)

ToD 10GSync

ToD 10G PPS 10G

TransceiverSampling

fPLL

1GfPLL

125 MHzrefclk_core

TOD 10GSync

ToD 10GSync

125 MHzrefclk_1g2p5g

latency_sclk (153.846153 MHz)tod_sampling_clk (80 MHz)mac_clk (312.5 MHz)mac64b_clk (156.25 MHz)

CorePLL

5.3.3. Reset Scheme

The global reset signal of the design example is asynchronous and active-low.Asserting this signal resets all channels and their components. Upon power-up, resetthe design example.

Figure 27. Reset Scheme for 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2Feature


MAC

PHY

ToD 10G SyncToD 10G PPS 10G


UserLogic

Channel N

AddressDecoder

TransceiverReset

Controller


Block

Design Example

Global Reset

Digital ResetAnalog Reset

Reconfiguration Done(to trigger reset after reconfiguration)

GlobalReset


ToDSampling

fPLL

MasterToD

MasterPPS

TransceiverSampling

fPLL


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When you configure the PHY in 1G/2.5G/10G (MGBASE-T) configuration, Intelrecommends that you refer to the Timing Constraints section of 1G/2.5G/5G/10GMulti-rate Ethernet PHY Intel Stratix 10 FPGA IP User Guide for details on the timingconstraint examples.

When the IEEE 1588v2 feature is enabled for 1G/2.5G/5G (MGBASE-T) PHYconfiguration, add the following constraints to the timing constraint file:

• Set false path from native PHY 1G clock to 2.5G 1588 logic and vice versa. Sincethe 2.5G 1588 logic is not running the native 1G clock, you do not need to ensuretiming closure for LL 10GbE MAC data path at 1G clock. For example:

set_false_path -from [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile0|*}] \ -to [get_registers {*|alt_mge_1588_tod_2p5g:*|* \ *|alt_mge_1588_tod_sync_*_2p5g:*|*}]set_false_path -from [get_registers {*|alt_mge_1588_tod_2p5g:*|* \ *|alt_mge_1588_tod_sync_*_2p5g:*|*}] \ -to [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile0|*}]

where the path indicated by profile0 is associated to the native PHY 1G clock,whereas the alt_mge_1588_tod_2p5g and alt_mge_1588_tod_sync_*_2p5gpaths indicate the 2.5G 1588 logic.

• Set false path from native PHY 2.5G clock to 1G 1588 logic and vice versa. Sincethe 1G 1588 logic is not running the native 2.5G clock, you do not need to ensuretiming closure for LL 10GbE MAC data path at 2.5G clock. For example:

set_false_path -from [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile1|*}] \ -to [get_registers {*|alt_mge_1588_tod_1g:*|* \ *|alt_mge_1588_tod_sync_*_1g:*|*}]set_false_path -from [get_registers {*|alt_mge_1588_tod_1g:*|* \ *|alt_mge_1588_tod_sync_*_1g:*|*}] \ -to [get_clocks {DUT|CHANNEL_GEN[*].u_channel|phy|alt_mge_phy_0|profile1|*}]

where the path indicated by profile1 is associated to the native PHY 2.5G clock,whereas the alt_mge_1588_tod_1g and alt_mge_1588_tod_sync_*_1gpaths indicate the 1G 1588 logic.

• Set false path from native PHY 10G clock to 1G/2.5G 1588 logic and vice versa.Since the 1G/2.5G 1588 logic is not running the native 10G clock, you do not needto ensure timing closure for LL 10GbE MAC data path at 2.5G clock. For example:

set_false_path -from [get_clocks \$profile2_clk] \\ -to [get_registers *|alt_em10g32:*|*]set_false_path -from [get_registers *|alt_em10g32:*|*] \\ -to [get_clocks \$profile2_clk]

where the path indicated by profile2 is associated to the native PHY 10G clock,whereas the alt_em10g32 path indicates the Low Latency Ethernet 10G MAClogic.

Related Information



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5.4. Simulation

Related Information




1. Starts up the design example with an operating speed of 10G.




• Non-PTP







5. Repeats steps 2 to 4 for 1G and 2.5G.



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The design example is using board trace loopback by default. To use SFP+, followinstruction in Changing to SFP+ Setting on page 50.


For board trace loopback setting:

• U5, OUT 0—644.53125 MHz

• U5, OUT 4—125 MHz

• U5, OUT 8—125 MHz

For SFP+ setting:


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• Y1—644.53125 MHz

• U5, OUT 1—125 MHz

• U5, OUT 8—125 MHz

Related Information



5.5.1. Changing to SFP+ Setting

In order to use SFP+, modify altera_eth_top.qsf file with the following setting:







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speed 1G, 2.5G, 10G The PHY speed.





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Figure 31. Interface Signals of the 1G/2.5G/10G Ethernet Design Examples with IEEE1588v2 Feature

MAC RX

1G/2.5G/10G Ethernet Design Example with 1588v2 Feature







avalon_st_tx_status_valid[n]avalon_st_tx_status_data[n][40]avalon_st_tx_status_error[n][7]





Avalon-MM Interface

Clock andReset

csr_clk

refclk_10g

mac_clk

resettx_digitalreset[rx_digitalreset[

mac64b_clk

refclk_1g2p5grefclk_core

rx_digitalreset_stat[

n]n]n]

n: Number of channels


led_char_err[n]led_disp_err[n]led_an[n]channel_tx_ready[n]

led_link[n]

channel_rx_ready[n]





csr_phy_write[n]csr_phy_writedata[32]

csr_phy_address[n][11]csr_phy_waitrequest[n]

csr_rcfg_readcsr_rcfg_readdata[32]

csr_rcfg_writecsr_rcfg_writedata[32]

csr_rcfg_address[2]

csr_native_phy_rcfg_readcsr_native_phy_rcfg_readdata[32]

csr_native_phy_rcfg_writecsr_native_phy_rcfg_writedata[32]

csr_native_phy_rcfg_waitrequestcsr_native_phy_rcfg_address[11]

(LL 10GbE MAC)

Avalon-MM Interface(1G/2.5G/5G/10G Multi-rate Ethernet PHY)

Avalon-MM Interface(1G/2.5G/10G

Avalon-MM Interface(Direct Native PHY

Status Interface

Ethernet Reconfiguration)

Reconfiguration)

csr_master_tod_write[

csr_master_tod_read[

n]

csr_master_tod_address[n]csr_master_tod_waitrequest[n]

n]

csr_master_tod_writedata[n][32]

csr_master_tod_readdata[n][32]Avalon-MM Interface(Master ToD Clock)


Interface


master_pulse_per_secondstart_tod_sync[n]

pps[n]TOD Interface

Packet ClassifierInterface

tx_egress_timestamp_request_in_valid[n]tx_egress_timestamp_request_in_fingerprint[n][f]

clock_operation_mode_mode[n][2]pkt_with_crc_mode[n]

tx_ingress_timestamp_valid[n]tx_ingress_timestamp_96b_data[n][96]tx_ingress_timestamp_64b_data[n][64]

tx_ingress_timestamp_format[n]

f: Timestamp fingerprint width




Byte Offset Block


0x00_4000 TOD Master

continued...


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Byte Offset Block

Channel 0

0x01_0000 MAC

0x01_8000 PHY


Channel 1

0x02_0000 MAC

0x02_8000 PHY


Traffic Controller



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6. 10M/100M/1G/2.5G/5G/10G (USXGMII) EthernetDesign Example

The 10M/100M/1G/2.5G/5G/10G (USXGMII) design example demonstrates anEthernet solution for Intel Stratix 10 devices using the LL 10GbE MAC Intel FPGA IPcore operating at 10M, 100M, 1G, 2.5G, 5G, and 10G.

Generate the design example from the Example Design tab of the LL 10GbE IntelFPGA IP parameter editor. You can choose to generate the design with or without theIEEE 1588v2 feature.

6.1. Features

• Supports dual Ethernet channel operating at 10M, 100M, 1G, 2.5G, 5G, and 10G.




• Option to generate the design example with IEEE 1588v2 feature.









Related Information




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Figure 32. Block Diagram—10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet DesignExample Without IEEE 1588v2 Feature

Avalon-MM

alt_mge_channel

LL 10GbE MAC

S

PHYS

alt_mge_channel

TransceiverReset

ControllerS

SS

Reset10G

Core Reference Clocks

TX/RX SerialData

Avalon-ST

address_decoder_top

altera_eth_top


alt_mge_multi_channel

CSR Clock

ATXPLL Core

fPLL


fPLL

refclk_sampling125 MHz


6. 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet Design Example

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Figure 33. Block Diagram—10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet DesignExample With IEEE 1588v2 Feature

Avalon-MM

alt_mge_channel


LL 10GbE MAC

S

PHYS

LocalTOD

S TODSync

Pulse perSecond

alt_mge_channel

TransceiverReset

ControllerS

MasterTOD

S

Pulse perSecond

S

Reset10G

Core Reference Clocks


TX/RX SerialData

PulsePer Second

Avalon-ST

address_decoder_top

altera_eth_top


alt_mge_multi_channel

CSR Clock

Transceiversampling

fPLL

ATXPLL Core

fPLL


fPLL

refclk_sampling125 MHz





LL 10GbE MAC The Low Latency Ethernet 10G MAC Intel FPGA IP core with the following configuration:• Speed: 10M/100M/1G/2.5G/5G/10G (USXGMII)• Datapath options: TX & RX• Enable ECC on memory blocks: Not selected• Enable supplementary address: Selected• Enable statistics collection: Selected• Statistics counters: Memory-based• TX and RX datapath Reset/Default To Enable: Selected• Use legacy XGMII Interface: Not selected• Use legacy Avalon Memory-Mapped Interface: Not selected• Use legacy Avalon Streaming Interface: SelectedFor the design example with the IEEE 1588v2 feature, the following additional parametersare configured:

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• Enable time stamping: Selected• Enable PTP one-step clock support: Selected• Timestamp fingerprint width: 4• Time Of Day format: Enable both 96b and 64b Time of Day Format

PHY The 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel FPGA IP with the followingconfiguration:• Speed: 10M/100M/1G/2.5G/5G/10G• Enable SGMII bridge: Not selected• Enabled IEEE 1588 Precision Time Protocol: Selected• Connect to MGBASE-T PHY: Not selected• Connect to NBASE-T PHY: Selected• VCCR_GXB and VCC_GXB supply voltage for the Transceiver: 1_0V• Reference clock frequency for 10GbE (MHz): 644.53125• Enable Native PHY Debug Master Endpoint: Not selected• Enable capability registers: Not selected• Enable control and status registers: Not selected• Enable PRBS soft accumulators: Not selected

Channel address decoder Decodes the addresses of the components in each Ethernet channel, such as PHY and LL10GbE MAC.

Multi-channel addressdecoder

Decodes the addresses of the components used by all channels, such as the Master ToDmodule.

Top address decoder Decodes the addresses of the top-level components, such as the Traffic Controller.


ATX PLL Generates a TX serial clock for the Intel Stratix 10 transceiver.

Core fPLL Generates clocks for all design components.


ToD Sampling fPLL Generates the clocks for the 1588 design components.

Master ToD The master ToD for all channels.

ToD Synch Synchronizes the master ToD to all local ToDs.

Local ToD The ToD for each channel.

Master PPS The master PPS. Returns pulse per second (pps) for all channels.




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Figure 34. Clocking Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) EthernetDesign Example Without IEEE 1588v2 Feature

MAC PHY


Channel 0

MAC PHY

Channel 1

10G ATXPLL

Design Example

644.53125 MHzReference Clock

User Logic

User Logic

CSR Clock10G TXSerial Clock

Core fPLL

644.53125 MHz Reference Clock 10G TX Serial Clock (5156.25 MHz)

312.5 MHz MAC Clock

MAC ClockCDR Reference Clock

CDR Reference Clock

125 MHz CSR Clock

Figure 35. Clocking Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) EthernetDesign Example With IEEE 1588v2 Feature



PTP Packet Classifier

LL 10GbE MACS

Adapters

Adapters

Transceiver Reset Controller

alt_mge_channelalt_mge_channel

altera_eth_multi_channel_1588

csr_clk

tx/rx_312_5_clktx/rx_156_25_clk

PHYS

latency_sclkcsr_clk

tx_serial_clk

Legend

312.5 MHz125 MHz

156.25 MHz

125 MHz125 MHz

644.53125 MHz

125 MHz125 MHz

LocalTODS

TODSync 96b

clk_slave clk_master

period_clk

clk

PulsePer Second

MasterTODS

period_clk

clk


TransceiverSampling

fPLLATX PLL

clk_sampling

refclk_core

refclk_10grefclk_sampling_125M

TODSync 64b

clk_master clk_slave

clk_sampling

TODSampling

fPLLCorefPLL

xgmii_txrx_coreclkin

6.3.3. Reset Scheme

The global reset signal of the design example is asynchronous and active-high.Asserting this signal resets all channels and their components. Upon power-up, resetthe design example.


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Figure 36. Reset Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet DesignExample With IEEE 1588v2 Feature



PTP Packet Classifier

LL 10GbE MAC

Transceiver Reset Controller

alt_mge_channelalt_mge_channel

altera_eth_multi_channel_1588

Legend

Digital resetAnalog reset

Global reset

LocalTOD

TODSync 96b

PulsePer Second

MasterTOD


TransceiverSampling

fPLLATX PLL

TODSync 64b

TODSampling

fPLLCorefPLL

User Logic

Digital resetAnalog reset

Global reset

PHY

Figure 37. Reset Scheme for 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet DesignExample Without IEEE 1588v2 Feature

MAC PHY


Channel 0

MAC PHY

Channel 1

10G PLL

Design Example

XGMII withData Valid

XGMII withData Valid

User Logic

User Logic

Global Reset

Global Reset

Analog Reset

Digital Reset


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6.4. Simulation

Related Information




1. Starts up the design example with an operating speed of 10G.




• Non-PTP







5. Repeats steps 2 to 4 for 10M, 100M, 1G, 2.5G, and 5G.



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6.4.2. Test Case—Design Example without the IEEE 1588v2 Feature


1. Starts up the example design with an operating speed of 10G.


3. Waits until the design example asserts the channel_tx_ready andchannel_rx_readysignals for both channels.


• 64-byte packet

• 1518-byte packet

• 100-byte packet

5. Repeats steps 2 to 4 for 10M, 100M, 1G, 2.5G, and 5G.



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• Y1—644.53125 MHz

• U5, OUT 8—125 MHz

Related Information




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speed 10M, 100M, 1G, 2P5G, 5G,10G

The PHY speed.




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Figure 42. Interface Signals of the 10M/100M/1G/2.5G/5G/10G (USXGMII) EthernetDesign Example

10M/100M/1G/2.5G/5G/10G (USXGMII)Ethernet Design Example

Clock andReset

csr_clk

mac32b_clk

reset

refclk_10g

mac64_clkrx_pma_clkout[

tx_digitalreset[rx_digitalreset[







avalon_st_tx_status_valid[n]avalon_st_tx_status_data[n][40]avalon_st_tx_status_error[n][7]





channel_tx_readychannel_rx_ready

rx_block_lockled_an

tx_serial_data[rx_serial_data[

PHY Interface

Status Interface

n]n]

n]

n]n]

n : Number of channels

refclk_sampling_125M


Interface


Avalon-MMInterface

csr_mch_readcsr_mch_readdata[32]

csr_mch_writecsr_mch_writedata[32]

csr_mch_address[20]csr_mch_waitrequest




Byte Offset Block

0x00_0000 Reserved

Channel 0

0x02_0000 Reserved

0x02_4000 PHY

0x02_6000 Native PHY Reconfiguration

continued...


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Byte Offset Block

0x02_8000 MAC

Channel 1

0x03_0000 Reserved

0x03_4000 PHY

0x03_6000 Native PHY Reconfiguration

0x03_8000 MAC

Traffic Controller



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7. Interface Signals DescriptionUse the following tables to find the description of the signals in the design example.The pinout diagram for each design example specifies the width of the signals.

7.1. Clock and Reset Interface Signals

Table 19. Clock and Reset Interface Signals

Signal Direction Width Description

csr_clk In 1 125 MHz configuration clock for the Avalon-MMinterface and core logic. In Intel Stratix 10 devices,it also provides clock for core logics.

csr_rst_n In 1 Active-low reset signal for the Avalon-MM interface.

tx_rst_n In 1 Active-low reset signal for the TX datapath.

rx_rst_n In 1 Active-low reset signal for the RX datapath.

mac_clk In 1 156.25 MHz configuration clock for the Avalon-STinterface and 0 ppm frequency difference withrefclk.

refclk In 1 125 MHz reference clock for the TX PLLs.

ref_clk_clk In 1 644.53125 MHz clock for the TX PLL.

core_clk_312 Out 1 312.5 MHz clock for the fast domain.

core_clk_156 Out 1 156.25 MHz clock for the slow domain.

rx_pma_clkout Out 1 CDR recovered clock.

reset In 1 Assert this asynchronous and active-high signal toreset the whole design example.

tx_digitalreset In [NUM_CHANNELS] Asynchronous and active-high signal to reset PCSTX portion of the transceiver PHY.

rx_digitalreset In [NUM_CHANNELS] Asynchronous and active-high signal to reset PCSRX portion of the transceiver PHY.

tx_digitalreset_stat Out [NUM_CHANNELS] Status signal for tx_digitalreset from PHY.

rx_digitalreset_stat Out [NUM_CHANNELS] Status signal for rx_digitalreset from PHY.

tx_analogreset In [NUM_CHANNELS] Asynchronous and active-high signal to reset PMATX portion of the transceiver PHY

rx_analogreset In [NUM_CHANNELS] Asynchronous and active-high signal to reset PMARX portion of the transceiver PHY.

tx_analogreset_stat Out [NUM_CHANNELS] Status signal for tx_analogreset from PHY.

rx_analogreset_stat Out [NUM_CHANNELS] Status signal for rx_analogreset from PHY.

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7.2. Avalon-MM Interface Signals

Table 20. Avalon-MM Interface Signals

Signal Direction Description

write

csr_mac_write

csr_phy_write

csr_rcfg_write

csr_native_phy_rcfg_write

csr_master_tod_write

csr_mch_write

In Assert this signal to request a write.

read

csr_mac_read

csr_phy_read

csr_rcfg_read

csr_native_phy_rcfg_read

csr_master_tod_read

csr_mch_read

In Assert this signal to request a read.

address

csr_mac_address

csr_phy_address

csr_rcfg_address

csr_native_phy_rcfg_address

csr_master_tod_addresscsr_mch_address

In Use this bus to specify the register address you want to read from or write to.

writedata

csr_mac_writedata

csr_phy_writedata

csr_rcfg_writedata

csr_native_phy_rcfg_writedata

csr_master_tod_writedata

csr_mch_writedata

In Carries the data to be written to the specified register.

readdata

csr_mac_readdata

csr_phy_readdata

csr_rcfg_readdata

csr_native_phy_rcfg_readdata

csr_master_tod_readdata

csr_mch_readdata

Out Carries the data read from the specified register.

waitrequest

csr_mac_waitrequest

csr_phy_waitrequest

Out When asserted, this signal indicates that the IP core is busy and not ready toaccept any read or write requests.

continued...

7. Interface Signals Description

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csr_native_phy_rcfg_waitrequest

csr_master_tod_waitrequest

csr_mch_waitrequest

7.3. Avalon-ST Interface Signals

Table 21. Avalon-ST Interface Signals

Signal Direction width Description

avalon_st_tx_startofpacket[]

In [NUM_CHANNELS] Assert this signal to indicate the beginning of the TXdata.

avalon_st_tx_endofpacket[]

In [NUM_CHANNELS] Assert this signal to indicate the end of the TX data.

avalon_st_tx_valid[] In [NUM_CHANNELS] Assert this signal to indicate that theavalon_st_tx_data signal and other signals onthis interface are valid.

avalon_st_tx_ready[] Out [NUM_CHANNELS] When asserted, indicates that the MAC IP core isready to accept data. The reset value of this signalis nondeterministic.

avalon_st_tx_error[] In [NUM_CHANNELS] Assert this signal to indicate that the current TXpacket contains errors.

avalon_st_tx_data[][]

In [NUM_CHANNELS][m] TX data from the client.m is 64 when the Use legacy Avalon StreamingInterface parameter is selected. Otherwise, m is32.

avalon_st_tx_empty[][]

In [NUM_CHANNELS][m] Use this signal to specify the number of emptybytes in the cycle that contain the end of the TXdata.m is 3 when the Use legacy Avalon StreamingInterface parameter is selected. Otherwise, m is 2.• 0x0—All bytes are valid.• 0x1—The last byte is invalid.• 0x2—The last two bytes are invalid.• 0x3—The last three bytes are invalid.

avalon_st_rx_startofpacket[]

Out [NUM_CHANNELS] When asserted, indicates the beginning of the RXdata.

avalon_st_rx_endofpacket[]

Out [NUM_CHANNELS] When asserted, indicates the end of the RX data.

avalon_st_rx_valid[] Out [NUM_CHANNELS] When asserted, indicates that theavalon_st_rx_data signal and other signals onthis interface are valid.

avalon_st_rx_ready[] In [NUM_CHANNELS] Assert this signal when the client is ready to acceptdata.

avalon_st_rx_error[][]

Out [NUM_CHANNELS][6] When set to 1, the respective bits indicate an errortype:

continued...


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• Bit 0—PHY error.— — For 10 Gbps, the data on xgmii_rx_data

contains a control error character (FE).— For 10 Mbps,100 Mbps,1 Gbps,

gmii_rx_err or mii_rx_err is asserted.• Bit 1—CRC error. The computed CRC value does

not match the CRC received.• Bit 2—Undersized frame. The receive frame

length is less than 64 bytes.• Bit 3—Oversized frame. The receive frame

length is more than MAX_FRAME_SIZE.• Bit 4—Payload length error. The actual frame

payload length is different from the value in thelength/type field.

• Bit 5—Overflow error. The receive FIFO buffer isfull while it is still receiving data from the MACIP core.

avalon_st_rx_data[][]

Out [NUM_CHANNELS][m] RX data to the client.m is 64 when the Use legacy Avalon StreamingInterface parameter is selected. Otherwise, m is32.

avalon_st_rx_empty[][]

Out [NUM_CHANNELS][m] Contains the number of empty bytes during thecycle that contain the end of the RX data.m is 3 when the Use legacy Avalon StreamingInterface parameter is selected. Otherwise, m is 2.

avalon_st_tx_status_valid[]

Out [NUM_CHANNELS] When asserted, this signal qualifies theavalon_st_txstatus_data andavalon_st_txstatus_error signals.

avalon_st_tx_status_data[][]

Out [NUM_CHANNELS][40] Contains information about the TX frame.• Bits 0 to 15: Payload length.• Bits 16 to 31: Packet length.• Bit 32: When set to 1, indicates a stacked VLAN

frame.• Bit 33: When set to 1, indicates a VLAN frame.• Bit 34: When set to 1, indicates a control frame.• Bit 35: When set to 1, indicates a pause frame.• Bit 36: When set to 1, indicates a broadcast

frame.• Bit 37: When set to 1, indicates a multicast

frame.• Bit 38: When set to 1, indicates a unicast frame.• Bit 39: When set to 1, indicates a PFC frame.

avalon_st_tx_status_error[][]

Out [NUM_CHANNELS][7] When set to 1, the respective bit indicates thefollowing error type in the TX frame:• Bit 0: Undersized frame.• Bit 1: Oversized frame.• Bit 2: Payload length error.• Bit 3: Unused.• Bit 4: Underflow.• Bit 5: Client error.• Bit 6: Unused.The error status is invalid when an overflow occurs.

avalon_st_rx_status_valid[]

Out [NUM_CHANNELS] When asserted, this signal qualifies theavalon_st_rxstatus_data and avalon_st_rxstatus_error signals.

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The MAC IP core asserts this signal in the sameclock cycle the avalon_st_rx_ endofpacketsignal is asserted.

avalon_st_rx_status_data[][]

Out [NUM_CHANNELS][40] Contains information about the RX frame.• Bits 0 to 15: Payload length.• Bits 16 to 31: Packet length.• Bit 32: When set to 1, indicates a stacked VLAN

frame.• Bit 33: When set to 1, indicates a VLAN frame.• Bit 34: When set to 1, indicates a control frame.• Bit 35: When set to 1, indicates a pause frame.• Bit 36: When set to 1, indicates a broadcast

frame.• Bit 37: When set to 1, indicates a multicast

frame.• Bit 38: When set to 1, indicates a unicast frame.• Bit 39: When set to 1, indicates a PFC frame.

avalon_st_rx_status_error[][]

Out [NUM_CHANNELS][7] When set to 1, the respective bit indicates thefollowing error type in the RX frame.• Bit 0: Undersized frame.• Bit 1: Oversized frame.• Bit 2: Payload length error.• Bit 3: Unused.• Bit 4: Underflow.• Bit 5: Client error.• Bit 6: Unused.The error status is invalid when an overflow occurs.

avalon_st_pause_data[][]

In [NUM_CHANNELS][2] This signal takes effect when the register bits,tx_pauseframe_enable[2:1], are both set tothe default value 0. Set this signal to the followingvalues to trigger the corresponding actions.• 0x0—Stops pause frame generation.• 0x1—Generates an XON pause frame.• 0x2—Generates an XOFF pause frame. The MAC

IP core sets the pause quanta field in the pauseframe to the value in thetx_pauseframe_quanta register.

• 0x3—Reserved.

Related Information

Avalon-ST Data Interface Clocks, Intel FPGA Low Latency Ethernet 10G MAC UserGuide

7.4. PHY Interface Signals

Table 22. PHY Interface Signals


rx_serial_data In 2 RX serial input data

tx_serial_data Out 2 TX serial output data


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7.5. Status Interface

Table 23. Status Interface Signals


led_link

block_lock

rx_block_lock

Out Asserted when the link synchronization is successful.

led_an

ethernet_1g_an

Out Asserted when auto-negotiation is completed.

led_char_err

ethernet_1g_char_err

Out Asserted when a 10-bit character error is detected in the RX data.

led_disp_err

ethernet_1g_disp_err

Out Asserted when a 10-bit running disparity error is detected in the RX data.

channel_ready

channel_tx_ready

channel_rx_ready

tx_ready_export

rx_ready_export

Out Asserted when the channel is ready for data transmission.

atx_pll_locked Out Asserted when the TX PLL is locked.

7.6. IEEE 1588v2 Timestamp Interface Signals

Table 24. IEEE 1588v2 Timestamp Interface Signals


tx_egress_timestamp_96b_valid Out [NUM_CHANNELS] When asserted, this signal qualifies thetimestamp,tx_egress_timestamp_96b_data[], and the fingerprint,tx_egress_timestamp_96b_fingerprint[], of the TX frame.

tx_egress_timestamp_96b_data Out [NUM_CHANNELS][96] Carries the 96-bit egress timestamp inthe following format:• Bits 48 to 95: 48-bit seconds field• Bits 16 to 47: 32-bit nanoseconds

field• Bits 0 to 15: 16-bit fractional

nanoseconds field

tx_egress_timestamp_96b_fingerprint

Out [NUM_CHANNELS][TSTAMP_FP_WIDTH]

Specifies the fingerprint of the TXframe that the 96-bit timestamp is for.

tx_egress_timestamp_64b_valid Out [NUM_CHANNELS] When asserted, this signal qualifies thetimestamp,tx_egress_timestamp_64b_data[], and the fingerprint,tx_egress_timestamp_64b_fingerprint[], of the TX frame.

tx_egress_timestamp_64b_data Out [NUM_CHANNELS][64] Carries the 64-bit egress timestamp inthe following format:

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• Bits 16 to 63: 48-bit nanosecondsfield

• Bits 0 to 15: 16-bit fractionalnanoseconds field

tx_egress_timestamp_64b_fingerprint

Out [NUM_CHANNELS][TSTAMP_FP_WIDTH]

Specifies the fingerprint of the TXframe that the 64-bit timestamp is for.

rx_egress_timestamp_96b_valid Out [NUM_CHANNELS] When asserted, this signal qualifies thetimestamp,rx_ingress_timestamp_96b_data[]. The MAC IP core asserts thissignal in the same clock cycle it assertsavalon_st_rx_startofpacket.

rx_egress_timestamp_96b_data Out [NUM_CHANNELS][96] Carries the 96-bit ingress timestamp inthe following format:• Bits 48 to 95: 48-bit seconds field• Bits 16 to 47: 32-bit nanoseconds


nanoseconds field

rx_egress_timestamp_64b_valid Out [NUM_CHANNELS] When asserted, this signal qualifies thetimestamp,rx_ingress_timestamp_64b_data[]. The MAC IP core asserts thissignal in the same clock cycle it assertsavalon_st_rx_startofpacket.

rx_egress_timestamp_64b_data Out [NUM_CHANNELS][64] Carries the 64-bit ingress timestamp inthe following format:• Bits 16 to 63: 48-bit nanoseconds


nanoseconds field

Related Information

IEEE 1588v2 Interface Clocks, Intel FPGA Low Latency Ethernet 10G MAC User Guide

7.7. Packet Classifier Interface Signals

Table 25. Packet Classifier Interface Signals


tx_egress_timestamp_request_in_valid[]

In [NUM_CHANNELS] Assert this signal to requesttimestamping for the TX frame.This signal must be asserted inthe same clock cycleavalon_st_tx_startofpacket is asserted.

tx_egress_timestamp_request_in_fingerprint[][]

In [NUM_CHANNELS][TSTAMP_FP_WIDTH]

Use this bus to specify thefingerprint that validates thetimestamp for the incomingpacket.

clock_operation_mode_mode[][] In [NUM_CHANNELS][2] Use this signal to specify theclock mode.

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• 00: Ordinary clock• 01: Boundary clock• 10: End to end transparent

clock• 11: Peer to peer transparent

clock

pkt_with_crc_mode[] In [NUM_CHANNELS] Use this signal to specifywhether or not a packetcontains CRC.• 0: Packet contains CRC• 1: Packet does not contain

CRC

tx_ingress_timestamp_valid[] In [NUM_CHANNELS] Indicates whether or not theresidence time can be updated.• 0: Prevents update for

residence time• 1: Allows update for

residence time based ondecoded results

When this signal is deasserted,thetx_etstamp_ins_ctrl_out_residence_ti me_updatesignal also gets deasserted.

tx_ingress_timestamp_96b_ data[][]

In [NUM_CHANNELS][96] 96-bit format of ingresstimestamp that holds the dataso that the output can alignwith the start of an incomingpacket.

tx_ingress_timestamp_64b_ data[][]

In [NUM_CHANNELS][64] 64-bit format of ingresstimestamp that holds the dataso that the output can alignwith the start of an incomingpacket.

tx_ingress_timestamp_format[] In [NUM_CHANNELS] The format of the timestampfor calculating the residencetime.• 0: 96 bits• 1: 64 bitsThis signal must be aligned tothe start of an incomingpacket.


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7.8. ToD Interface Signals

Table 26. ToD Interface Signal

Signal Direction

Width Description

master_pulse_per_second

Out 1 Pulse per second (PPS) from the master PPS module. Thesignal stay asserted for 10 ms.

start_tod_sync[] In [NUM_CHANNELS] Use this signal to trigger the ToD synchronization process.The time of day of the local ToD is synchronized to the timeof day of the master ToD. The synchronization processcontinues as long as this signal remains asserted.

pulse_per_second_10g[] Out [NUM_CHANNELS] PPS from the 10G PPS module of channel n. The signal stayasserted for 10 ms.

pulse_per_second_1g[] Out [NUM_CHANNELS] PPS from the 1G PPS module of channel n. The signal stayasserted for 10 ms.


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8. Configuration Registers Description

8.1. Register Access Definition

Table 27. Types of Register Access

Access Definition

RO Read only.

RW Read and write.

RWC Read, and write and clear. The user application writes 1 to the register bit(s) to invoke a definedinstruction. The IP core clears the bit(s) upon executing the instruction.

8.2. Low Latency Ethernet 10G MAC

This topic lists the byte offsets the MAC registers.

Table 28. Primary MAC Address

Byte Offset R/W Name HW Reset

0x2008 RW primary_mac_addr0 0x0

0x200C RW primary_mac_addr1 0x0

Table 29. TX Configuration and Status Registers


0x4000 RW tx_packet_control 0x0

0x4004 RO tx_packet_status 0x0

0x4100 RW tx_pad_control 0x1

0x4200 RW tx_crc_control 0x3

0x4400 RW tx_preamble_control 0x0

0x6004 RW tx_frame_maxlength 0x5EE(1518)

0x4300 RO tx_underflow_counter0 0x0

0x4304 RO tx_underflow_counter1 0x0

Table 30. Flow Control Registers


0x4500 RW tx_pauseframe_control 0x0

0x4504 RW tx_pauseframe_quanta 0x0

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0x4508 RW tx_pauseframe_enable 0x1

0x4680 RW tx_pfc_priority_enable 0x0

0x4600 RW pfc_pause_quanta_0 0x0



0x460C RW pfc_pause_quanta_3 0x0




0x461C RW pfc_pause_quanta_7 0x0

0x4640 RW pfc_holdoff_quanta_0 0x1



0x464C RW pfc_holdoff_quanta_3 0x1




0x465C RW pfc_holdoff_quanta_7 0x1

Table 31. RX Configuration and Status Registers


0x0000 RW rx_transfer_control 0x0

0x0004 RO rx_transfer_status 0x0

0x0100 RW rx_padcrc_control 0x1

0x0200 RW rx_crccheck_control 0x2

0x0400 RW rx_custom_preamble_forward 0x0

0x0500 RW rx_preamble_control 0x0

0x2000 RW rx_frame_control 0x3

0x2004 RW rx_frame_maxlength 0x5EE(1518)

0x2010 RW rx_frame_spaddr0_0 0x0



0x201C RW rx_frame_spaddr1_1 0x0



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0x202C RW rx_frame_spaddr3_1 0x0

0x2060 RW rx_pfc_control 0x1

0x0300 RO rx_pktovrflow_error 0x0

Table 32. TX Timestamp Registers


0x4440 RW tx_period_10G 0x33333

0x4448 RW tx_fns_adjustment_10G 0x0

0x444C RW tx_ns_adjustment_10G 0x0

0x4460 RW tx_period_mult_speed 0x80000

0x4468 RW tx_fns_adjustment_mult_speed 0x0

0x446C RW tx_ns_adjustment_mult_speed 0x0

Table 33. RX Timestamp Registers


0x0440 RW rx_period_10G 0x33333

0x0448 RW rx_fns_adjustment_10G 0x0

0x044C RW rx_ns_adjustment_10G 0x0

0x0460 RW rx_period_mult_speed 0x80000

0x0468 RW rx_fns_adjustment_mult_speed 0x0

0x046C RW rx_ns_adjustment_mult_speed 0x0

Table 34. TX and RX Statistics Registers


0x7000 RO tx_stats_clr 0x0

0x3000 RO rx_stats_clr 0x0

0x7008:0x700C RO tx_stats_framesOK 0x0

0x3008:0x300C RO rx_stats_framesOK 0x0

0x7010:0x7014 RO tx_stats_framesErr 0x0

0x3010:0x3014 RO rx_stats_framesErr 0x0

0x7018:0x701C RO tx_stats_framesCRCErr 0x0

0x3018:0x301C RO rx_stats_framesCRCErr 0x0

0x7020:0x7024 RO tx_stats_octetsOK 0x0

0x3020:0x3024 RO rx_stats_octetsOK 0x0

0x7028:0x702C RO tx_stats_pauseMACCtrl_Frames 0x0

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0x3028:0x302C RO rx_stats_pauseMACCtrl_Frames 0x0

0x7030:0x7034 RO tx_stats_ifErrors 0x0

0x3030:0x3034 RO rx_stats_ifErrors 0x0

0x7038:0x703C RO tx_stats_unicast_FramesOK 0x0

0x3038:0x303C RO rx_stats_unicast_FramesOK 0x0

0x7040:0x7044 RO tx_stats_unicast_FramesErr 0x0

0x3040:0x3044 RO rx_stats_unicast_FramesErr 0x0

0x7048:0x704C RO tx_stats_multicast_FramesOK 0x0

0x3048:0x304C RO rx_stats_multicast_FramesOK 0x0

0x7050:0x7054 RO tx_stats_multicast_FramesErr 0x0

0x3050:0x3054 RO rx_stats_multicast_FramesErr 0x0

0x7058:0x705C RO tx_stats_broadcast_FramesOK 0x0

0x3058:0x305C RO rx_stats_broadcast_FramesOK 0x0

0x7060:0x7064 RO tx_stats_broadcast_FramesErr 0x0

0x3060:0x3064 RO rx_stats_broadcast_FramesErr 0x0

0x7068:0x706C RO tx_stats_etherStatsOctets 0x0

0x3068:0x306C RO rx_stats_etherStatsOctets 0x0

0x7070:0x7074 RO tx_stats_etherStatsPkts 0x0

0x3070:0x3074 RO rx_stats_etherStatsPkts 0x0

0x7078:0x707C RO tx_stats_etherStatsUndersizePkts 0x0

0x3078:0x307C RO rx_stats_etherStatsUndersizePkts 0x0

0x7080:0x7084 RO tx_stats_etherStatsOversizePkts 0x0

0x3080:0x3084 RO rx_stats_etherStatsOversizePkts 0x0

0x7088:0x708C RO tx_stats_etherStatsPkts64Octets 0x0

0x3088:0x308C RO rx_stats_etherStatsPkts64Octets 0x0

0x7090:0x7094 RO tx_stats_etherStatsPkts65to127Octets 0x0

0x3090:0x3094 RO rx_stats_etherStatsPkts65to127Octets 0x0

0x7098:0x709C RO tx_stats_etherStatsPkts128to255Octets 0x0

0x3098:0x309C RO rx_stats_etherStatsPkts128to255Octets 0x0

0x70A0:0x70A4 RO tx_stats_etherStatsPkts256to511Octets 0x0

0x30A0:0x30A4 RO rx_stats_etherStatsPkts256to511Octets 0x0

0x70A8:0x70AC RO tx_stats_etherStatsPkts512to1023Octets 0x0

0x30A8:0x30AC RO rx_stats_etherStatsPkts512to1023Octets 0x0

0x70B0:0x70B4 RO tx_stats_etherStatPkts1024to1518Octets 0x0

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0x30B0:0x30B4 RO rx_stats_etherStatPkts1024to1518Octets 0x0

0x70B8:0x70BC RO tx_stats_etherStatsPkts1519toXOctets 0x0

0x30B8:0x30BC RO rx_stats_etherStatsPkts1519toXOctets 0x0

0x70C0:0x70C4 RO tx_stats_etherStatsFragments 0x0

0x30C0:0x30C4 RO rx_stats_etherStatsFragments 0x0

0x70C8:0x70CC RO tx_stats_etherStatsJabbers 0x0

0x30C8:0x30CC RO rx_stats_etherStatsJabbers 0x0

0x70D0:0x70D4 RO tx_stats_etherStatsCRCErr 0x0

0x30D0:0x30D4 RO rx_stats_etherStatsCRCErr 0x0

0x70D8:0x70DC RO tx_stats_unicastMACCtrlFrames 0x0

0x30D8:0x30DC RO rx_stats_unicastMACCtrlFrames 0x0

0x70E0:0x70E4 RO tx_stats_multicastMACCtrlFrames 0x0

0x30E0:0x30E4 RO rx_stats_multicastMACCtrlFrames 0x0

0x70E8:0x70EC RO tx_stats_broadcastMACCtrlFrames 0x0

0x30E8:0x30EC RO rx_stats_broadcastMACCtrlFrames 0x0

0x70F0:0x70F4 RO tx_stats_PFCMACCtrlFrames 0x0

0x30F0:0x30F4 RO rx_stats_PFCMACCtrlFrames 0x0

Related Information

Low Latency Ethernet 10G MAC User GuideFor the description of the MAC registers.

8.3. PHY

8.3.1. 1G/2.5G/5G/10G Multi-rate PHY

This topic lists the byte offsets of the 1G/2.5G/5G/10G Multi-rate variant registers forIntel Stratix 10 devices.

Register Map

You can access the 16-bit/32-bit configuration registers via the Avalon-MM interface.

Table 35. Register Map Overview

Address Range Usage Register Width Configuration

0x00 : 0x1F 1000BASE-X/SGMII 16

2.5G, 1G/2.5G, 10M/100M/1G/2.5G, 10M/

100M/1G/2.5G/10G, 1G/2.5G/10G

0x400 : 0x41F USXGMII 32 1G/2.5G/5G/10G (USXGMII)

0x461 Serial Loopback 32 1G/2.5G/5G/10G (USXGMII)


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Register Definitions

Observe the following guidelines when accessing the registers:

• Do not write to reserved or undefined registers.

• When writing to the registers, perform read-modify-write operation to ensure thatreserved or undefined register bits are not overwritten.

Table 36. 1G/2.5G/5G/10G Multi-rate PHY Register Definitions

Word Offset Name Description Access HW ResetValue

0x00 control Bit [15]: RESET. Set this bit to 1 to trigger a softreset.The PHY clears the bit when the reset is completed.The register values remain intact during the reset.

RWC 0

Bit[14]: LOOPBACK. Set this bit to 1 to enableloopback on the serial interface.

RW 0

Bit [12]: AUTO_NEGOTIATION_ENABLE. Set this bitto 1 to enable auto-negotiation.Auto-negotiation is supported only in 1GbE.Therefore, set this bit to 0 when you switch to aspeed other than 1GbE.

RW 0

Bit [9]: RESTART_AUTO_NEGOTIATION. Set this bitto 1 to restart auto-negotiation.The PHY clears the bit as soon as auto-negotiation isrestarted.

RWC 0

All other bits are reserved. — —

0x01 status Bit [5]: AUTO_NEGOTIATION_COMPLETE. A value of"1" indicates that the auto-negotiation is completed.

RO 0

Bit [3]: AUTO_NEGOTIATION_ABILITY. A value of"1" indicates that the PCS function supports auto-negotiation.

RO 1

Bit [2]: LINK_STATUS. A value of "0" indicates thatthe link is lost. A value of "1" indicates that the link isestablished.

RO 0


0x02:0x03 phy_identifier The value set in the PHY_IDENTIFIER parameter. RO Value ofPHY_IDEN

TIFIERparameter

0x04 dev_ability Use this register to advertise the device abilitiesduring auto-negotiation.

— —

Bits [13:12]: RF. Specify the remote fault.• 00: No error.• 01: Link failure.• 10: Off-line.• 11: Auto-negotiation error.

RW 00

Bits [8:7]: PS. Specify the PAUSE support. RW 11

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• 00: No PAUSE.• 01: Symmetric PAUSE.• 10: Asymmetric PAUSE towards the link partner.• 11: Asymmetric and symmetric PAUSE towards

the link device.

Bit [5]: FD. Ensure that this bit is always set to 1. RW 1


0x05(1000BASE-X

mode)

partner_ability The device abilities of the link partner during auto-negotiation.

— —

Bit [14]: ACK. A value of "1" indicates that the linkpartner has received three consecutive matchingability values from the device.

RO 0

Bits [13:12]: RF. The remote fault.• 00: No error.• 01: Link failure.• 10: Off-line.• 11: Auto-negotiation error.

RO 0

Bits [8:7]: PS. The PAUSE support.• 00: No PAUSE.• 01: Symmetric PAUSE.• 10: Asymmetric PAUSE towards the link partner.• 11: Asymmetric and symmetric PAUSE towards

the link device.

RO 0

Bit [6]: HD. A value of "1" indicates that half-duplexis supported.

RO 0

Bit [5]: FD. A value of "1" indicates that full-duplex issupported.

RO 0


0x05 (SGMIImode)

partner_ability The device abilities of the link partner during auto-negotiation.

— —

Bit [11:10]: COPPER_SPEEDLink partner speed:• 00: copper interface speed is 10 Mbps• 01: copper interface speed is 100 Mbps• 10: copper interface speed is 1 Gigabit• 11: reserved

RO 00

Bit [12]: COPPER_DUPLEX_STATUSLink partner capability:• 1: copper interface is capable of full-duplex

operation• 0: copper interface is capable of half-duplex

operation

RO 0

Bit [14]: ACK. Link partner acknowledge. A value of 1indicates that the device received three consecutivematching ability values from its link partner.

RO 0

Bit [15]: COPPER_LINK_STATUSLink partner status:

RO 0

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• 1: copper interface link is up• 0: copper interface link is down


0x06 an_expansion The PCS capabilities and auto-negotiation status. — —

Bit [1]: PAGE_RECEIVE. A value of "1" indicates thatthe partner_ability register has been updated. Thisbit is automatically cleared once it is read.

RO 0

Bit [0]: LINK_PARTNER_AUTO_NEGOTIATION_ABLE.A value of "1" indicates that the link partner supportsauto-negotiation.

RO 0

0x07 device_next_page

The PHY does not support the next page feature.These registers are always set to 0.

RO 0

0x08 partner_next_page

RO 0

0x09:0x0F Reserved — — —

0x10 scratch Provides a memory location to test read and writeoperations.

RW 0

Bit [31:16]: Reserved — —

0x11 rev The current version of the PHY IP core. RO Currentversion ofthe PHY


0x12:0x13 link_timer 21-bit auto-negotiation link timer.• Offset 0x12: link_timer[15:0]. Bits [8:0] are

always be set to 0.• Offset 0x13: link_timer[20:16] occupies the lower

5 bits. The remaining 11 bits are reserved andmust always be set to 0.

RW 0

0x14 if_mode Interface Mode Register — —

Bit [0]: SGMII_ENADetermines the PCS function operating mode. Settingthis bit to 1b'1 enables SGMII mode. Setting this bitto 1b'0 enables 1000BASE-X gigabit mode.

RW 0

Bit [1]: USE_SGMII_ANIn SGMII mode, setting this bit to 1b'1 configures thePCS with the link partner abilities advertised duringauto-negotiation. If this bit is set to 1b'0, the PCSfunction should be configured with the SGMII_SPEEDbits.

RW 0

Bit [3:2]: SGMII_SPEEDWhen the PCS operates in SGMII mode (SGMII_ENA= 1) and is not programmed for automaticconfiguration (USE_SGMII_AN = 0), the followingencodings specify the speed:• 2'b00: 10 Mbps• 2'b01: 100 Mbps• 2'b10: Gigabit• 2'b11: Reserved

RW 0

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These bits are not used when SGMII_ENA = 0 orUSE_SGMII_AN = 1.



0x400 usxgmii_control Control Register — —

Bit [0]: USXGMII_ENA:• 0: 10GBASE-R mode• 1: USXGMII mode

RW 0

Bit [1]: USXGMII_AN_ENA is used whenUSXGMII_ENA is set to 1:• 0: Disables USXGMII Auto-Negotiation and

manually configures the operating speed with theUSXGMII_SPEED register.

• 1: Enables USXGMII Auto-Negotiation, andautomatically configures operating speed with linkpartner ability advertised during USXGMII Auto-Negotiation.

RW 1

Bit [4:2]: USXGMII_SPEED is the operating speed ofthe PHY in USXGMII mode and USE_USXGMII_AN isset to 0.• 3’b000: 10M• 3’b001: 100M• 3’b010: 1G• 3’b011: 10G• 3’b100: 2.5G• 3’b101: 5G• 3’b110: Reserved• 3’b111: Reserved

RW 0


Bit [9]: RESTART_AUTO_NEGOTIATIONWrite 1 to restart Auto-Negotiation sequence The bitis cleared by hardware when Auto-Negotiation isrestarted.

RWC 0


0x401 usxgmii_status Status Register — —


Bit [2]: LINK_STATUS indicates link status forUSXGMII all speeds• 1: Link is established• 0: Link synchronization is lost, a 0 is latched

RO 0


Bit [5]: AUTO_NEGOTIATION_COMPLETEA value of 1 indicates the Auto-Negotiation process iscompleted.

RO 0


0x402:0x404 Reserved — — —

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0x405 usxgmii_partner_ability

Device abilities advertised to the link partner duringAuto-Negotiation

— —


Bit [7]: EEE_CLOCK_STOP_CAPABILITYIndicates whether or not energy efficient Ethernet(EEE) clock stop is supported.• 0: Not supported• 1: Supported

RO 0

Bit [8]: EEE_CAPABILITYIndicates whether or not EEE is supported.• 0: Not supported• 1: Supported

RO 0

Bit [11:9]: SPEED• 3'b000: 10M• 3'b001: 100M• 3'b010: 1G• 3'b011: 10G• 3'b100: 2.5G• 3'b101: 5G• 3'b110: Reserved• 3'b111: Reserved

RO 0

Bit [12]: DUPLEXIndicates the duplex mode.• 0: Half duplex• 1: Full duplex

RO 0

Bit [13]: Reserved — —

Bit [14]: ACKNOWLEDGEA value of 1 indicates that the device has receivedthree consecutive matching ability values from its linkpartner.

RO 0

Bit [15]: LINKIndicates the link status.• 0: Link down• 1: Link up

RO 0


0x406:0x411 Reserved — — —

0x412 usxgmii_link_timer

Auto-Negotiation link timer. Sets the link timer valuein bit [19:14] from 0 to 2 ms in approximately 0.05-ms steps. You must program the link timer to ensurethat it matches the link timer value of the externalNBASE-T PHY IP Core.The reset value sets the link timer to approximately1.6 ms.Bits [13:0] are reserved and always set to 0.

[19:14]:RW

[13:0]: RO

[19:14]:1F

[13:0]: 0


0x461 phy_serial_loopback

Configures the transceiver serial loopback in the PMAfrom TX to RX.

— —

Bit [0] RW 0

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• 0: Disables the PHY serial loopback• 1: Enables the PHY serial loopback


Related Information

Intel Stratix 10 Multi-rate Ethernet PHY IP CoreFor detailed description of the configuration registers of the 1G/2.5G/5G/10G PHYIP.

8.4. Transceiver Reconfiguration

Table 37. Transceiver Reconfiguration Register Map

WordOffset Name Bits Description Access HW Reset

0x00 logical_channel_number

[9:0] The logical number of the reconfiguration block. RW 0x000

[31:10] Reserved

0x01 control [1:0] Specify the new operating speed:• 00: 1 Gbps• 01: 2.5 Gbps• 10: Reserved• 11: 10 Gbps

RW 0x00

[15:2] Reserved — 0x000

[16] Writing 1 to this bit when it is 0 starts thereconfiguration process. The bit clears when theprocess is completed.

RWC 0x0

[31:17] Reserved — 0x000000

0x02 status [0] When set to 1, indicates the reconfigurationprocess is in progress.

RO 0x0

[31:1] Reserved — —

8.5. TOD

Table 38. TOD Register Map

Byte Offset Name Bits Description Access HW Reset

0x0000 SecondsH [15:0] The upper 16 bits of the second field. RW 0x0

[31:16] Reserved. — —

0x0004 SecondsL 32 The lower 32 bits of the second field. RW 0x0

0x0008 NanoSec 30 The nanosecond field. RW 0x0

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Byte Offset Name Bits Description Access HW Reset

0x0010 Period [15:0] The time of day. The period in fractionalnanosecond.

RW n (1)

[19:16] The time of day. The period in nanosecond.

[31:20] Reserved. — —

0x0014 AdjustPeriod

[15:0] The offset adjustment period. The period infractional nanosecond.

RW 0x0

[19:16] The offset adjustment period. The period innanosecond.

[31:20] Reserved. — —

0x0018 AdjustCount

[19:0] The number of adjusted period in clock cycles. RW 0x0

[31:20] Not used. — —

(1) The default value for the period depends on the frequency of the PHY speed. For example, iffrequency is 125 MHz, the period is 8 ns (PERIOD_NS = 0x0008 and PERIOD_FNS = 0x0000).


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9. Low Latency Ethernet 10G MAC Intel Stratix 10 FPGAIP Design Example User Guide Archives

IP versions are the same as the Intel Quartus Prime Design Suite software versions upto v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IPcores have a new IP versioning scheme.If an IP core version is not listed, the user guide for the previous IP core version applies.

IP Core Version User Guide

19.2.0 Low Latency Ethernet 10G MAC Intel Stratix 10 FPGA IP Design Example User Guide

19.1 Low Latency Ethernet 10G MAC Intel Stratix 10 FPGA IP Design Example User Guide

18.0 Low Latency Ethernet 10G MAC Intel Stratix 10 FPGA IP Design Example User Guide

17.1 Intel FPGA Low Latency Ethernet 10G MAC Design Example User Guide for Intel Stratix 10Devices

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https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/archives/ug-20073-19-2-0.pdf

https://www.intel.com/content/dam/altera-www/global/en_US/pdfs/literature/ug/archives/ug-20073-19-1.pdf








10. Document Revision History for the Low LatencyEthernet 10G MAC Intel Stratix 10 FPGA IP DesignExample User Guide

Document Version Intel QuartusPrime Version

IP Version Changes

2019.12.13 19.3 19.3.0 • Added a note to the procedure steps in theCompiling and Simulating the Design section.

• Added a new Topic—Updating PHY IP Design FileNames.

• Updated the procedure steps in the ChangingTarget Device in Hardware Design Example section.

• Updated for latest Intel branding standards.

2019.10.02 19.3 19.3.0 • Added new topic—Changing Target Device inHardware Design Example.

• Updated references to Intel Stratix 10 GX SignalIntegrity H-Tile (ES) Development Kit as IntelStratix 10 GX Signal Integrity H-Tile (Production)Development Kit.

• Updated the Generating the Design topic to add anote to Step 8.

• Updated Figure: Example Design Tab.• Updated the Hardware and Software Requirements

topics for all design example chapters• Updated Table: 1G/2.5G/5G/10G Multi-rate PHY

Register Definitions.

2019.07.01 19.2 19.2.0 • Updated all references to Stratix 10 H-Tile GXTransceiver Signal Integrity Development Kit toStratix 10 GX Signal Integrity H-Tile (ES)Development Kit.

• Updated Table: Parameters in the Example DesignTab:— Updated the parameter name Example Design

Files for Simulation or Synthesis toExample Design Files.

— Updated the parameter name Enable NPDMEsupport to Enable Native PHY Debug MasterEndpoint (NPDME).

• Updated Figure: Example Design Tab.• Updated Table: Design Components of the

10GBASE-R Ethernet design example to update thedescription for FIFO.

• Made editorial edits through out the document.

2019.04.30 19.1 19.1 • Updated Table: Parameters in the Example DesignTab to update the description for Select Board.

• Updated Figure: Block Diagram of the HardwareSetup.

• Updated the hardware requirements in theHardware and Software Requirements topics for alldesign examples.

continued...

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IP Version Changes

2019.04.24 19.1 19.1 • Changed Altera Debug Master Endpoint (ADME) toNative PHY Debug Master Endpoint (NPDME).

2018.09.24 18.0 18.0 • Updated Table: Parameters in the Example DesignTab to include a note to parameters EnableNPDME support and Analog Voltage to clarifythat these options are only available from IntelQuartus Prime Pro Edition version 17.0 onwards.

• Removed Debug Signals topic from the 10GBASE-REthernet Design Example for Intel Stratix 10Devices chapter.

• Updated the Configuration Registers Descriptionchapter:— Added the following topics:

• Register Access Definition• 1G/2.5G/5G/10G PHY

— Removed the Register Map topic.• Added Timing Constraints topic to the following

design example chapters:— 10M/100M/1G/2.5G/10G Ethernet Design for

Intel Stratix 10 Devices— 1G/2.5G Ethernet Design Example with IEEE

1588v2 Feature for Intel Stratix 10 Devices— 1G/2.5G/10G Ethernet Design Example with

IEEE 1588v2 Feature for Intel Stratix 10Devices

2018.08.08 18.0 18.0 • Updated Table: Hardware Test Cases of the10GBASE-R Ethernet Design Example for IntelStratix 10 Devices chapter to update thedescription for source gen_conf.tcl commandof the SFP+ loopback test case.

• Updated Figure: Interface Signals of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet DesignExample.

• Updated Table: Avalon-MM Interface Signals:— Added the following signals:

• csr_mch_write

• csr_mch_writedata

• csr_mch_read

• csr_mch_readdata

• csr_mch_address

• csr_mch_waitrequest

— Removed the following signals:• csr_write

• csr_writedata

• csr_read

• csr_readdata

• csr_address

• csr_waitrequest

2018.05.16 18.0 18.0 • Updated for latest branding standards.• Made editorial text updates throughout the

document.• Added support for Xcelium simulator.• Renamed the document as Low Latency Ethernet

10G MAC Intel Stratix 10 FPGA IP Design ExampleUser Guide.

continued...

10. Document Revision History for the Low Latency Ethernet 10G MAC Intel Stratix 10 FPGA IPDesign Example User Guide

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IP Version Changes

• Updated the procedure steps of the Compiling andTesting the Design in Hardware topic.

• Updated the Test Cases topic of the 10BASE-REthernet Design Example for Intel Stratix 10Devices chapter.

• Updated the 10G USXGMII Ethernet DesignExample for Intel Stratix 10 Devices chapter:— Updated all references to 10G USXGMII

references to 10M/100M/1G/2.5G/5G/10G(USXGMII).

— Added 1588v2 feature support to the 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernetdesign example chapter.

— Added new Simulation topics:• Test Case—Design Example with the IEEE

1588v2 Feature• Test Case—Design Example without the IEEE

1588v2 Feature— Updated Table: Command Parameters.— Updated Table: Register Map to include byte

offset for Native PHY Reconfiguration block.• Updated the Test Procedure topic of the 10M/

100M/1G/2.5G Ethernet Design Example for IntelStratix 10 Devices chapter.

• Updated the Hardware and Software Requirements,Design Components, and Hardware Testing topicsfor all design example chapters.

• Updated the following Tables:— Directory and File Description— Parameters in the Example Design Tab— Clock and Reset Interface Signals

• Updated the following Figures:— Block Diagram—10GBASE-R Ethernet Design

Example— Clocking and Reset Scheme for 10GBASE-R

Design Example— Reset Scheme for 10M/100M/1G/2.5G/10G

Ethernet Design Example— Block Diagram—1G/2.5G Ethernet Design

Example with IEEE 1588v2 Feature— Block Diagram—1G/2.5G/10G Ethernet Design

Example with IEEE 1588v2 Feature— Reset Scheme for 1G/2.5G/10G Ethernet Design

Example with IEEE 1588v2 Feature— Clocking Scheme for 10M/100M/1G/

2.5G/5G/10G (USXGMII) Ethernet DesignExample Without IEEE 1588v2 Feature

— Interface Signals of the 10M/100M/1G/2.5G/5G/10G (USXGMII) Ethernet DesignExample

2018.03.28 17.1 17.1 • Updated Figure: Clocking Scheme for 10G USXGMIIEthernet Design Example.


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Date Version Changes

November 2017 2017.12.04 • Updated Figure: Example Design Tab.• Added Hardware Testing, Test Cases, and Debug Signals topics for the

10BASE-R Ethernet Design Examplechapter.• Updated the description in the Hardware Testing topic for the following

Ethernet design examples:— 10M/100M/1G/2.5G/10G— 1G/2.5G with IEEE 1588v2 Feature— 1G/2.5G/10G with IEEE 1588v2 Feature— 10G USXGMII

• Added Changing to SFP+ Setting topic for 1G/2.5G/10G Ethernetdesign example with IEEE 1588v2 Feature chapter.

• Made editorial text and structure update.

2017.11.06 • Rebranded as Intel.• Renamed the document as Intel FPGA Low Latency Ethernet 10G MAC

Design Example User Guide for Intel Stratix 10 Devices.• Updated the Quick Start Guide section:

— Updated the "Directory and File Description" table.— Removed rtl directory from the "Directory and File Description"

table.— Changed heading title of the Design Parameters Description topic to

Design Example Parameters.— Updated the "Parameters in the Example Design Tab" table:

• Added Analog Voltage and Enable ADME support parametersand descriptions.

• Updated the descriptions for Generate File Format and SelectBoard parameters.

— Updated the Procedure subtopic under the Compiling and Simulatingthe Design topic.

— Updated the Procedure subtopic under the Compiling and Testingthe Design in Hardware topic.

• Updated entire 1G/2.5G/10G Ethernet Design Example chapter to 10M/100M/1G/2.5G/10G Ethernet Design Example chapter.

• Updated the 1G/2.5G Ethernet Design Example with IEEE 1588v2Feature for Intel Stratix 10 Devices topic.

• Added 10G USXGMII Ethernet Design Example chapter.• Added 1G/2.5G/10G Ethernet Design Example with IEEE 1588v2

Feature chapter.• Updated the description in the "Features" topic for the 10GBASE-R,

10M/100M/1G/2.5G/10G, 1G/2.5G with IEEE 1588v2 Feature, 1G/2.5G,1G/2.5G/10G with IEEE 1588v2 Feature, and 10G USXGMII Ethernetdesign examples.

• Updated the "Design Component" table for the 10GBASE-R, 10M/100M/1G/2.5G/10G, 1G/2.5G with IEEE 1588v2 Feature, 1G/2.5G, 1G/2.5G/10G with IEEE 1588v2 Feature, and 10G USXGMII Ethernetdesign examples.

• Updated the Hardware and Software Requirements topic for the10GBASE-R, 10M/100M/1G/2.5G/10G, 1G/2.5G with IEEE 1588v2Feature, 1G/2.5G, 1G/2.5G/10G with IEEE 1588v2 Feature, and 10GUSXGMII Ethernet design examples.

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Date Version Changes

• Updated Figures:— Example Design Tab— Block Diagram of the Hardware Setup— Block Diagram—10GBASE-R Design Example— Clocking and Reset Scheme for 10GBASE-R Design Example— Clocking Scheme for 10M/100M/1G/2.5G/10G Ethernet Design

Example— Reset Scheme for 10M/100M/1G/2.5G/10G Ethernet Design

Example— Clocking Scheme for 1G/2.5G Ethernet Design Example with IEEE

1588v2 Feature— Reset Scheme for 1G/2.5G Ethernet Design Example with IEEE

1588v2 Feature— Interface Signals of the 1G/2.5G Ethernet Design Example with IEEE

1588v2 Feature— Clocking Scheme for 1G/2.5G/10G Ethernet Design Example with

IEEE 1588v2 Feature— Reset Scheme for 1G/2.5G/10G Ethernet Design Example with IEEE

1588v2 Feature— Interface Signals of the 1G/2.5G/10G Ethernet Design Examples

with IEEE 1588v2 Feature— Clocking Scheme for 10G USXGMII Ethernet Design Example— Reset Scheme for 10G USXGMII Ethernet Design Example— Interface Signals of the 10G USXGMII Ethernet Design Example

• Updated the "RX Configuration and Status Registers" table: Updatedthe HW Reset value for 0x2004 from 1518 to 0x5EE(1518).

• Updated the Configuration Registers Description chapter:— Updated the PHY topic:

• Removed the "PMA Registers", "PCS Registers", and "Stratix 10GMII PCS Registers" tables.

• Added Register Map and Register Definitions subtopics.— Merged the 10G TOD and 1G TOD topics with the Master TOD and

changed heading title to ToD.— Updated "ToD Register Map" table: Added bits information.

• Made text updates throughout the document.

May 2017 2017.05.08 • Updated the Procedure topic in the Quick Start Guide chapter.• Added the Compiling and Testing the Design in Hardware topic in the

Quick Start Guide chapter.• Updated the Software Requirements topic in the 10GBASE-R Design

Example for Stratix 10 chapter.• Updated the Register Map table in the 10GBASE-R Design Example for

Stratix 10 chapter.• Updated the Clocking and Reset Scheme for 10GBASE-R Design

Example figure.• Added 1G/2.5G Ethernet Design Example with IEEE 1588v2 Feature

chapter.• Added 1G/2.5G/10G Ethernet Design Example chapter.• Added Interface Signals Description for Stratix 10 chapter.• Added Configuration Registers Description for Stratix 10 chapter.• Updated the description for csr_clk signal in the Clock and Reset

Interface Signals table.• Editorial fix to the Interface Signals and Configuration Registers topics

for 10GBASE-R Design Example chapter.• Updated document part number from UG-20016-S10 to UG-20073.

October 2016 2016.10.31 Initial release.


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