low losses pwm for high power press-pack igbt inverters

Low Losses PWM for High Power Press Pack IGBT Inverters

D. Begin, B. Gollentz and N. GruauAlstom T&D, Power Conversion business

M&O Special Project3, avenue des trois chênes

90018 BELFORT Cedex, FRANCETel: 33 (0)3 84 55 64 50/fax: 33 (0)3 84 55 19 49

[email protected] / [email protected] /[email protected]

Key words:Press Pack IGBT, Neutral Point Clamped Inverter, Low losses PWM, Total Harmonic Distortion.

Abstract:This paper describes the approach to design of a Neutral Point Clamped (NPC) Insulated Gate

Bipolar Transistor (IGBT) Voltage Source Inverter (VSI), especially designed for marine applications,where a strong requirement is to minimise the size of the cubicles. To achieve this requirement, thereare two complementary approaches. First approach is to optimise the PWM pattern and thus tomaximise the drive performances. Second approach is to use a new technology of press pack IGBTs,which gives high compactness and reliability.

1 IntroductionThe medium voltage VSIs have become a most attractive solution for a wide range of applications,

typically from 3MW to 30MW, and from 0 to 300Hz load frequency, thus replacing the former drivestechnologies using thyristors. The demand for VSIs, besides standard drives, is for low speed drives,typically 150 rpm motors for marine propulsion, as well as for high speed drives up to 20 000 rpm.

A range of drives is under development, using the three level NPC topology. The PWM schemeshave been studied and optimised in order to get the maximum output power throughout the range offrequency.

This paper describes the approach to design of a NPC IGBT VSI, especially designed for marineapplications, where a strong requirement is to minimise the size of the cubicles. In order to achievethis requirement, there are two complementary approaches. First approach is to use the power switchesin optimal conditions in order to maximise the drive performances. The aim is to determine the properswitching frequency and modulation type which give a suitable Total Harmonic Distortion (THD) inthe load, and minimise the switching losses. For all applications, standard drives and also low speeddrives and very high speed drives, specific three level PWM schemes are selected and characterised.Second approach is to use a new technology of press pack IGBTs, which gives high compactness andreliability.

2 PWM CriteriaIn order to get the highest available power from the IGBT inverter, three main criteria have to be

respected:• The IGBT maximum junction temperature must be below 125°C,• The maximum output current must stay within the Safe Operating Area (SOA),• The AC current must have the lowest THD.Taking into account these three criteria defines the switching frequency, as explained in Figure 1.

Low losses PWM for high power press-pack IGBT inverters BEGIN David

EPE 2003 - Toulouse ISBN : 90-75815-07-7 P.1

Figure 1: IGBT Characterisation

Figure 1 shows that for low switching frequencies, the limitations are the maximum switchedcurrent, according to the SOA, (which is characterised by the IGBT) and the THD current. For higherfrequencies, the limitation is the junction temperature. Actually, the IGBT can not be used at the SOAlimit, because switching losses are prevailing. Also the THD current varies in inverse ratio to theswitching frequency. The main point is to detect the optimal switching frequency, which correspondsto a switched current as high as possible, with no derating of the available output current.

This optimum point depends mainly on the quality of the heat sink (technology part), but also onthe PWM pattern (control part).

The design of the PWM pattern is made according to three main compromises:• Optimal current THD, for a given switching frequency,• Minimal DC capacitors,• Ability of high modulation.In paragraph 3, several patterns of PWM are described.

3 Three level PWM scheme optimisationsFigure 2 shows the structure of a three level inverter, on a R,L,E load, which represents an AC

motor. On each phase, it is possible to apply a voltage of Vdc/2 by turning on the switches 2+/1+(status +1), or to apply a voltage of 0 by turning on the switches 1+/2- (status 0), or to apply a voltageof –Vdc/2 by turning on the switches 1-/2- (status -1).

Figure 2: Three level Inverter, on a R,L,E load.

0 0.5 1 1.5 2 2.50

0.2

0.4

0.6

0.8

1

IGBT characterisation

rated switching frequency

rate

d ou

tput

cur

rent

SOA limits

Thermal limits

Optimal working point

Vdc2

Vdc2

2+

1+

2-

1-

~

~

~

R L



3.1 Sine triangle PWM / Space vector PWMTo implement PWM control, there are mainly three approaches: the sine triangle PWM, the space

vector PWM (see Figure 3), and the precalculated PWM (see paragraph 3.2).• The sine triangle PWM consists of comparing the voltage reference with a triangle carrier,

and the intersections define the switching happening. One freedom degree is the zerosequence voltage which can be added to the three voltage references,

• The space vector PWM consists of selecting in advance the different inverter status. Figure 3illustrates one example of voltage reference. To achieve the voltage reference, one possibilityis to reach status (1,0,0), (1,0,-1), (0,0,-1), (0,-1,-1), then (0,-1,-1), (0,0,-1), (1,0,-1), (1,0,0)for phases U, V, W. The computation consists of calculating the duration of each status.Because the status (1,0,0) and (0,-1,-1) give the same phase to phase voltage, the freedomdegree is the duty cycle on these two status.

• If the status are neighbour status, the sine triangle and the space vector methods areequivalent, and the freedom degree of duty cycle in space vector PWM corresponds to achoice of zero sequence voltage reference.

Figure 3: Space vector and sine triangle PWM

3.2 Precalculated PWM

By defining N switching angles between 0 and 90°, the whole PWM pattern is defined becauseof symmetry. The harmonic voltage contains only odd ranks, given by the following formula:

∑=

+ −++

=N

n

nnk k

kV

112 )1).().12cos((

)12(4

απ

where α1, α2, … αn are the switching angles between 0 and 90°.There are N freedom degrees, one is used for the fundamental, and (N-1) degrees are used to

eliminate (N-1) typical harmonics. The harmonics multiple of three represent zero sequence voltage,the same voltage is applied on all three phases. Then We can establish two kinds of strategy:

• First strategy is to suppress the N-1 first odd harmonics. The result is close to the sinetriangle PWM seen in paragraph 3.1, without zero sequence voltage,

• Second strategy is to suppress the N-1 first harmonics non multiple of three. So it ispossible to suppress harmonics up to 1.5 times the frequency of first strategy. This resultcan also be reached with the sine triangle PWM by choosing an appropriate zero sequencevoltage (made of harmonics multiple of three).

0

2+Command

1+Command

Vdc2

Vdc2

+

-

(-1,1,-1) (0,1,-1) (1,1,-1)

(1,0,-1)

(1,-1,-1)

(1,-1,0)

(1,-1,1)(0,-1,1)(-1,-1,1)

(-1,0,1)

(-1,1,1)

(-1,1,0)(0,1,0)

(1,0,-1)

(1,1,0)

(0,0,-1)

(0,1,1)

(-1,0,0)

(1,1,1)

(0,0,0)

(-1,-1,-1)

(1,0,0)

(0,-1,-1)

(0,0,1)

(-1,-1,0)

(1,0,1)

(0,-1,0)

Space vector

U

W

V

Vref



One result of the second strategy is presented in Table 1 and Figure 4, when using the N-1freedom degrees to suppress typical phase to phase harmonics (non multiple of three).

Number of angles EliminatedHarmonics

Lowest remainingharmonic

Switching frequency(in multiple offundamental)

9 5,7,11,13,17,19,23,25

29 9

11 5,7,11,13,17,19,23,25,29,31

35 11

21 5,7,11,13,17,19,23,25,29,31,35,37,41,43,47,49,53,55,59,61

65 21

Table 1: Precalculated PWM criteria

0 10 20 30 40 50 60 70 80 90 10010

20

30

40

50

60

70

80

90

9 angles precalculated PWM

Modulation (%)

switc

hing

ang

le (

°)

0 10 20 30 40 50 60 70 80 90 10010

20

30

40

50

60

70

80

90

21 angles precalculated PWM

Modulation (%)

switc

hing

ang

le (

°)

Figure 4: Switching angles between 0 and 90°, as function of modulation.

From this precalculated PWM, it is possible to draw the following conclusion: for a given PWMswitching frequency fs, it is possible to eliminate the phase to phase voltage harmonics up toapproximately 1,5 times the switching frequency. Besides, this can be obtained by inhibiting theswitching in a window of 30° each quarter of a period.

3.3 Three Level Clamped PWM (3LC PWM)This PWM method gives equivalent result to the precalculated PWM seen on paragraph 3.2. The

modulator signal used by this PWM is clamped to 0 during 2x60° for low modulation depth. Forhigher modulation depth, one part of the clamped to 0 duration is changed into a clamping to status +1or status -1. The PWM features are the following:• Switching losses reduction compared to sine triangle PWM without zero sequence voltage, at

same triangle carrier frequency,• Lowest current harmonic is at switching frequency times 1.5,• Reduced zero sequence voltage in the motor.

No switching

No switching



Figure 5 shows the phase to DC link middle voltage, and its reference.

Figure 5: 3LC PWM Figure 6: GD PWM

3.4 Generalised Discontinuous PWM (GD PWM)

This PWM scheme is obtained thanks to a zero sequence signal added to the sine modulator [1],[3]. The zero sequence signal is calculated in order to get no modulation on each phase during 2x60°(see Figure 6). This duration can be shifted in order to be in phase with the peak of current, so the zerosequence voltage is depending on the current. The main features of this PWM are the following:• Optimal switching losses reduction because the phase with the highest current is not switched [4] [5],• Lowest current harmonic is at switching frequency times 1.5 (like 3LC PWM),• Improved thermal stress sharing between IGBTs in a NPC structure as shown in Figure 7,• Optimal at high modulations because it avoids problems of voltage reference non-linearity.

0 0.2 0.4 0.6 0.8 10

0.5

1

Mod. depth

Loss

es

Sinus + Harm3 PWM

0 0.2 0.4 0.6 0.8 10

0.5

1

Mod. depth

Loss

es

3LC PW M

0 0.2 0.4 0.6 0.8 10

0.5

1

Mod. depth

Loss

es

GD PWM

Clamp diodesNeutral point IGBTs+ & - IGBTs

Figure 7: Comparison of switching+conduction losses for several PWMpatterns at constant carrier frequency

No switching

No switching



3.5 DC Capacitance BalancingWith a three level topology, the current in the DC middle point is the following:

( ) ( ) ( ) wvun ImwImvImuI ⋅−+⋅−+⋅−= 111where mu, mv, mw are the status of phase U, phase V and phase W, i.e. (-1, 0, or +1), and Iu, Iv,

Iw are the phase currents. This current in the DC middle point generates an oscillation in the half DClink voltage, at frequency three times the fundamental frequency. An adequate zero sequence voltagecan minimise this oscillation. This zero sequence voltage also depends on the current. At power factor1, this PWM corresponds to the reference THIPWM1/4 [1].

The PWM features are the following:• Minimal voltage oscillations of the middle point of the DC link,• Optimal THD current for a given frequency of triangle carrier.

3.6 Comparison between PWM

3.6.1 THD performancesThe performances of the three PWM described in paragraphs 3.3 to 3.5 can be compared with

regards to several criteria. The most important criteria is the ability to provide maximal AC currentwith the best THD, and to minimise the DC capacitors.

It is possible to qualify the THD current without knowing the parameters of the load [1]. In firststep, knowing that the load is mainly inductive at the switching frequency, the difference between thevoltage reference and the voltage applied has to be integrated in order to calculate the currentdistortion. The harmonic distortion is the following:

∫ ∫ ⋅

⋅−= dtdtVV

TReal

TTHD refCurrent

2** ))(

1(

1

where Vref* and V* are the complex form of the voltage reference and the applied voltage.

Red

uced

TH

D o

f cur

rent

0 2 4 6 8 10 12 14 16 18 200

2

4

6

8

x 10-4

Frequency (Hz) for a 20 Hz motor

GDPWM

3LCPWM

THIPWM1/4

THIPWM1/6

3LCPWM at carrier frequency 3/2

Figure 8: THD for different PWM

Figure 8 shows a comparison of THD of current for different PWM using the same trianglecarrier. The best result is given by the PWM1/4 which gives also the minimum voltage oscillations ofthe DC link middle point. But the GDPWM and the 3LC PWM have reduced switching. Whencompared at the same average switching frequency or losses, the 3LC PWM and the GDPWM havebetter results, (see the THD curve with the 3LC PWM at carrier frequency 3/2 in Figure 8).



3.7 DC Capacitor designIt has been calculated that the current through the DC capacitors is independent of the PWM

pattern, for a given switching frequency, but only depends on the voltage modulation and the powerfactor. However the PWM modifies the spectrum of the current. For GDPWM, there is a harmoniccurrent at three times the fundamental, and for THIPWM1/4, there is no harmonic at low frequency.The harmonic is at carrier frequency. This gives minimal DC link voltage oscillation. Figure 9 showsthe rms current of the DC capacitors for different power factors.

0 5 10 15 2010

20

30

40

50

60

70

DC

cap

acito

r cu

rren

t in%

of A

C m

otor

cur

rent

DC capacitor current vs motor frequency (rated frequency: 20Hz)

0 5 10 15 2010

20

30

40

50

60

70

Motor frequency (Hz)

Power factor = 0 Power factor = 0.26 Power factor = 0.5 Power factor = 0.71 Power factor = 0.86 Power factor = 1

Figure 9: DC capacitor current for different power factors.

Referring to Figure 9, the highest current is reached at power factor 0, at modulation rate 0.5, andis equal to 130% of the AC rms current. At modulation 0.83, the current is independant of the powerfactor and is equal to 80% of the AC rms current.

4 Technology optimisationA new range of medium voltage IGBT drives is being developed using the PWM described in the

previous paragraphs and the new press-pack IGBTs, which together with de-ionised water coolingsignificantly reduces the overall dimensions of the drive system.

The press pack IGBT has been chosen for its outstanding features:• The IGBT has the capability to limit the current, allowing its safe turn-off under all operating

conditions, including short-circuit, with no need of fuses,• The IGBT is controlled by simple gate drivers which provide voltage command,• The IGBT is switched at high frequency, typically 1000Hz,• The press-pack IGBT is doubled-side cooled which provides higher current rating,• The press pack IGBT features no derating at low frequencies and is more robust compared to the

flat pack IGBT, thanks to its technology with no wire bonds,• The press pack IGBT is very well suited to serial connections, because the IGBT is always short-

circuited in case of failure, which also allows n+1 redundancies,• The press pack IGBT leads to a very compact stack design, which is a major advantage for marine

applications (Figure 10).



A whole range of drives, from 3 to 32 MW, which deliver all load frequencies from 0 to 300 Hz, isbeing designed. The range features several types of IGBTs, in order to get the appropriate drivespower ratings for each one of the standard voltage levels: 3.3 kV, 4.16kV and 6.6kV.

Each drive is made of a rectifier (12 pulse diode or IGBT converter), an IGBT inverter, a de-ionised water cooling unit and a controller. The drive is particularly suitable for induction motors, andcan also feed synchronous motors, permanent magnet motors…

Table 2 shows the range of drives. The first column indicates the connection types: xP indicatesthe number of IGBT stacks in parallel, and yS indicates the number of IGBTs in series

XPyS Volts MW Hz

1P1S 1650 4 0 – 300

1P1S 6 0 – 3001P2S 3300 8 0 – 300

2P1S 12 0 – 300

2P2S 16 0 – 300

1P1S 3 0 – 3002P1S 4160 6 0 – 300

1P3S 10 0 – 300

2P3S 20 0 – 300

1P2S 5 0 – 3002P2S 10 0 – 300

1P2S 6600 12 0 – 300

1P4S 16 0 – 300

2P2S 24 0 – 300

2P4S 32 0 – 300

Table 2: range of drives

Figure 10:View of a 6MW / 3.3 kVconverter(inverter size is 1000mmx1000mm x2200 mm)



5 ConclusionThis paper has presented the research work on the optimised PWM patterns for a three level NPCpress-pack IGBT VSI, in order to obtain the maximum output active power. The low losses PWMstrategies improve the ratio converter power / cubicle size, and they don’t degrade the motor voltagewaveform quality at a constant losses level. The press-pack technology also reduces significantly theoverall dimensions, gives to the drive a solid robustness and improves the life duration, thanks to abetter thermal cycling capability. So, this VSI is particularly suitable for induction machines in marineapplications.

6 References[1]. A. M. Hava, R. J. Kerkman, T. A. Lipo, “Simple Analytical And Graphical Methods For Carrier Based

PWM-VSI Drives,” IEEE Transactions on Power Electronics, Vol.14, pp. 49-61, January 1999.

[2]. H. W. Van der Broeck, “Analysis of the harmonics in voltage fed inverter drives caused by PWM schemeswith discontinuous switching operation,” Conf. Rec. EPE, 1991, vol. 3, pp. 261–266.

[3]. A. M. Hava, S. Sul, R. J. Kerkman, and T. A. Lipo, “Dynamic overmodulation characteristics of triangleintersection PWM methods,” IEEE-Industrial Application Soc. Conf. Rec., New Orleans, LA, 1997, pp.1520–1528.

[4]. O. Harling, H. Raffel, B. Orlik, "Energy-efficient quasi-direct converter with reduced switching lossesusing an intelligent modulation strategy", Conf. Rec. EPE, 2001.

[5]. Dae-Woong Chung, Seung-Ki Sul, "Minimum-Loss PWM Strategy for 3-Phase PWM Rectifier", IEEETrans on Industrial Electronics,Vol.46,No.3, June 1999, pp. 517-526.

[6]. M. Nahrstaedt, U. Putz, D. Wendt, "High speed, high power compressor drives with medium voltageinduction motors", Conf. Rec. EPE, 2001.



low losses pwm for high power press-pack igbt inverters

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