low power designs in memories
DESCRIPTION
Low Power designs in Memories. Dr Elwin Chandra Monie. 4T & 6T SRAM cell Implementation. 4T Bistable Latch. __ BIT/BIT : Data line WORD : RD/WT. 6T Bistable Latch. Reading a Cell. I cell. D V = I cell * t ----- C b. Sense Amplifier. 1 -> 0. 0 -> 1. Writing a Cell. - PowerPoint PPT PresentationTRANSCRIPT
Low Power designs in Memories
Dr Elwin Chandra Monie
2
4T & 6T SRAM cell Implementation
6T Bistable Latch
4T Bistable Latch
__BIT/BIT : Data lineWORD : RD/WT
3
Reading a Cell
Icell
DV = Icell * t
----- CbSense Amplifier
4
Writing a Cell
1 -> 00 -> 1
SRAM cell
Precharge
Column Decode
6
SRAM, Putting it all together
2n rows, 2m * k columns
n + m address lines, k bits data width
7
SRAM Partitioning
8
SRAM Partitioning Divided Wordline Architecture
Memory Subsystems Organization (1)
Two or more memory chips can be combined to create memory with more bits per location (two 8X2 chips can create a 8X4 memory)
Memory Subsystems Organization (2)
Two or more memory chips can be combined to create more locations (two 8X2 chips can create 16X2 memory)
11
Partioning summaryPartitioning reduces switched
capacitancePartioning involves a trade off between
area, power and speedFor high speed designs, use short
blocks(e.g 64 rows x 128 columns )◦Keep local bitline heights small
For low power designs use tall narrow blocks (e.g 256 rows x 64 columns)◦Keep the number of columns same as the
access width to minimize wasted power
Pulsed Word LinePulsed WORD line to
limit the duration of reading so that the BIT line has lesser swing
Pulsed Word Line
Q
R S
Reset from dummy sense-amp Word enable
SA Sense Amplifiers
Memory Core
Accessed Row
Dum
my
Col
umn
Wor
d D
river
Wor
d D
ecod
er
Bit Line Isolation Main idea: Isolate sense amplifiers from bit line after
sensing, to prevent from having large voltage swings
Pulsed sense amplifier
Reducing power in decode circuit
Two stage decoder
17
Differential Sensing - SRAM
Diff.SenseAmp
BLBL
SRAM cell i
x xy yD D
VDDVDD
WLi
PC
EQ
VDD
x x
y
SE
V DD
x x
y
SE
(b) Doubled-ended Current Mirror Amplifier
y
(a) SRAM sensing scheme.(c) Cross-Coupled Amplifier
M1 M2
M4M3
M5
18
Latch-Based Sense Amplifier
VDD
BL
SE
SE
BLEQ
Initialized in its meta-stable point with EQOnce adequate voltage gap created, sense amp enabled with SEPositive feedback quickly forces output to a stable operating point.
20
Bit Line Precharging
equalization transistor - speeds up equalization of the two bit lines by allowing the capacitance and pull-up device of the nondischarged bit line to assist in precharging the discharged line
Static Pull-up Precharge
BL !BL
clock
Clocked Precharge
!BLBL