Low Power SOC Sensor Interface Designfor High Temperature Applications

————————-Doctor of Philosophy

Thesis Proposal

Nima Sadeghinimas@ece.ubc.ca

Department of Electrical and Computer EngineeringUniversity of British Columbia

Co-supervisors:Dr. Shahriar Mirabbasi andDr. Chad P.J. Bennington

May 1, 2009

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Contents1 Introduction and Overview 1

1.1 Improvement in Pulp and Paper Digester Operation Efficiency . . . . . . . . . . . 11.2 State-of-the-Art Background Survey on High Temperature Circuit Design . . . . . 21.3 High Temperature Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3.1 Mobility Variation over Temperature . . . . . . . . . . . . . . . . . . . . . 41.3.2 Threshold Voltage Variation over Temperature . . . . . . . . . . . . . . . 51.3.3 Junction (Reverse-Biased Diode) Leakage Current . . . . . . . . . . . . . 6

1.4 High Temperature Compensation Techniques . . . . . . . . . . . . . . . . . . . . 8

2 Fabricated SmartChip Building Blocks using 0.13 µm Bulk CMOS Technology 92.1 Bias Circuit Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.1.1 Supply-Independent Bootstrapped Design . . . . . . . . . . . . . . . . . . 92.1.2 Supply-Independent Start-Up for Bootstrap . . . . . . . . . . . . . . . . . 102.1.3 Bias Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.1.4 Bias Circuit Simulation Results . . . . . . . . . . . . . . . . . . . . . . . 12

2.2 Amplifier Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.2.1 Folded Cascode Amplifier Design . . . . . . . . . . . . . . . . . . . . . . 152.2.2 Amplifier Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . 162.2.3 Amplifier Performance Comparison . . . . . . . . . . . . . . . . . . . . . 18

2.3 Voltage Reference Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 192.3.1 Negative Temperature Coefficient Voltage . . . . . . . . . . . . . . . . . . 202.3.2 Positive Temperature Coefficient Voltage . . . . . . . . . . . . . . . . . . 202.3.3 Bandgap Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202.3.4 Bandgap Voltage Reference Design . . . . . . . . . . . . . . . . . . . . . 212.3.5 Bandgap Voltage Reference Simulation Results . . . . . . . . . . . . . . . 22

2.4 Oscillator Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242.4.1 Oscillator Delay Cell Design . . . . . . . . . . . . . . . . . . . . . . . . . 262.4.2 Oscillator Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . 26

2.5 Additional Temperature Testing Blocks . . . . . . . . . . . . . . . . . . . . . . . 28

3 Conclusion and Future Work 283.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283.2 Planned Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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1 Introduction and OverviewReliable electronics operation at high temperature environments is required for several applicationsincluding automotive sensors and electronics, oil field devices, and multi-phase chemical reactorsused in pulp and paper industry as shown in Fig 1. Our target application is the pulp and paperindustry, in which they need to optimize the process at high temperature operation up to 180 Cby obtaining the temperature and pressure inside their digester though the process. Thereforethey require data acquisition on the operating conditions at high temperature which introducesnew challenges. Implementing a chip to provide such data results an increase of the operationalefficiency of pulp and paper digester up to 5%. It is worthwhile to notice that in Canada only a 1%improvement in digester operation efficiency is worth $80 million/year.

ctor of 2 Drop of threshold voltage from 25 °C to 250 °C

y yHigh Temperature

Automotive sensorsand electronics

Multi-phasechemical reactorsOil field devices

Pulp and Paper Industry

Figure 1: Some application examples that require electronic circuitry operating at high temperature.

1.1 Improvement in Pulp and Paper Digester Operation EfficiencyOur intention is to implement a smart sensor device for data acquisition within Kraft Pulp Digester,the results of which are expected to improve digester operational efficiency by up to 5%. Weplan to build an entire System-On-Chip (SOC) data acquisition device, called SmartChip, able towithstand high temperature operation, up to 180 C for several hours. The implementation of sucha smart sensor platform has not been addressed in the past, but we know how to do it and aretrying to use the knowledge for high temperature design [1]-[8] to implement the smart chip. Incontrast to other published work [1]-[8] our first intention is to minimize the power consumptionof our design using more recent 0.13 µm CMOS technologies with 2.5 V supply voltage. Thelow power/voltage requirements are due to autonomous battery operation and small size imposedby the proposed application. The entire sensor chip size needs to be at most about a match box,

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the same size of a wood chip used in digester. Although individual electronic components areavailable that could withstand the process conditions, they would need to be packaged together,and therefore they could not satisfy the sizing requirement. Furthermore almost all commerciallyavailable high-temperature circuitry use non-CMOS or non-standard CMOS processes which aremore expensive than the standard bulk CMOS technologies. For instance, Silicon-On-Insulator(SOI) chips which are designed for up to 200 C usually require 5 V or more, need high powerusing around 20 mA per component and can cost in excess of $200 per component. Also The lowpower/voltage requirements of our SmartChip are due to its required autonomous battery platformto operate during the entire process of digester, for about 20 hours, in a harsh environment.

We have considered the recent published work in bulk CMOS high temperature electronics[1]-[8] and try to improve the trade off between power and performance. We use switch capacitordifferential circuit architectures with Correlated Double Sampling (CDS) as the basic circuit blocksdue to their correction capability of leakage currents and voltage offsets. We first simulate thecircuit at 125 C, since the available spice model is not valid above 125 C, and calculate thecircuit parameters such as noise, power and voltage headroom which could be affected by the hightemperature effects. Then we will fabricate a test chip leaving enough margins for 180 C operationto measure the chip results at that temperature of interest and check our design.

The SOC sensor is divided into MEMS sensors and electronic sensor interface parts as shownin Fig 2. The MEMS sensors are studied and designed with another college of mine in our group,we only look at electronic sensor interface on this paper.

Smart Chip SOC Sensors

MEMSSensors

Amplifier

Power Management

ADC

Electronics Sensor Interface

Memory

Oscillator ControlLogic

BiasCircuitry

Figure 2: Smart Chip main system blocks.

1.2 State-of-the-Art Background Survey on High Temperature Circuit De-sign

Recent research show that high temperature sensor interface components implemented in standardCMOS processes can operate at high temperature more than 200 C [1]-[8], which is well above forwhat our application aimed, but we still have more constraints on power consumption and supply

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voltage of our Smart Chip. These addressed works used 0.5 um bulk CMOS technology with 5V supply voltage source, our intention, however, is to design a chip using more recent CMOStechnologies, 0.13 µm CMOS technology with 2.5 V as a voltage source.

Also, as shown in Fig 2, our Smart Chip sensor interface besides an amplifier, an Analog-to-Digital Converter (ADC), an oscillator and a control logic blocks, which are addressed in almostall previous works [4]-[8], consists of a voltage reference as well as a non-volatile memory blocks,which have not been addressed in the bulk CMOS for high temperature environment up to 180 C.Therefore our Smart Chip can be considered as an independent self-functional data acquisitionsystem at high temperature without using any external memory and supply voltage.

As a quick over view of the system blocks shown in Fig 2, almost all analog blocks consist anamplifier including the integrator and comparator used in the ADC, the oscillator, and the voltagereference. Based on their design requirements for different purposes, different structures will beused. Since we want large dc gain and ability to drive capacitive loads at Pre-Amplifier stage, wechose the fully differential folded-cascode amplifier with switched-capacitor structure [10]. Al-though the authors of [4]-[8] used this type of amplifier, for the output stage, however, a tow-stageamplifier might perform better in terms of large output swing due to our low voltage limitation.

After amplification we want to sample sensors data for data acquisition. Sigma-delta modu-lator, Σ∆ ADC, has been reported as a robust analog-to-digital converter [18] by means of thenoise shaping technique. Hence the feasibility of ADC in high temperature application has beenaddressed [4] and [8], and we also chose this type of ADC to mitigate analog device impairmentsat high temperature. The oscillator is generating the clock for using in ADC and micro controllerunit. To build an entire SOC smart chip without using off-chip components, such as crystal and ca-pacitors, also to prevent dealing with inductors quality in standard CMOS, we can possibly choosea differential ring oscillator [10] which has been shown functional at high temperature [4]. Themicro controller is a simple control logic unit to control ADC clock for different sampling ratesand to manage recording data on memory.

In this proposal we study the design and implementation of the SmartChip building blocks thatwe have fabricated so far such as different structures of bias circuit, amplifier, voltage reference,and oscillator. The remaining building blocks will be focused as our future work plan. In thefollowing section, before looking at our fabricated blocks, we first look at high temperature impacton CMOS electronics in general and the technique we can use to develop our SmartChip.

1.3 High Temperature ConsiderationsAt high temperature, these main blocks shown in Fig 2 implemented in standard CMOS presentmany impairments, including reduced electron/holes mobility, threshold voltages drop, and in-creased junction leakage currents [11]-[15], which introduce new design challenges. Among theseimpairments, excess leakage current at high temperature causes the most serious problem such asshifting the operating points in our analog circuits, lowering output resistance of high-impedancenodes, being a source of latch up triggering current, or greatly increasing offset among matchingdevices. It can bring the loss of charge stored at dynamic node or severely reduce circuit perfor-mance due to loss of bias current. So, the leakage is among the most serious challenges in siliconhigh temperature electronics [12].

Before we discuss the impact of high temperature on the mobility, threshold voltage and leak-age current in the following sections, it is worthwhile to notice that in general the single-ended

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circuitry is very sensitive to common mode errors including the ones caused by high temperaturesuch as leakage current. The key is to choose a robust circuit architecture to mitigate the commonmode errors, i.e. fully-differential. We use fully differential switch capacitor architectures due totheir reduction capability of leakage currents at high temperature [8].

1.3.1 Mobility Variation over Temperature

In silicon material at high temperature the carrier (electron/holes) mobility is mainly affected bya basic scattering mechanism, called lattice scattering. This means by the vibration of the latticea traveling carrier through the silicon crystal is scattered. The carrier mobility from the latticescattering decreases as temperature increases. The temperature dependence of such a decrement isabout T−1.5 [4].

Figure 3: NMOS channel electron mobility measurement vs. temperature ([4]).

In Fig 3 an example of an NMOS channel electron mobility measurement versus temperature isdepicted. In the temperature range of our interest here, from room temperature, 27 C (300 K) upto 180 C (453 K), we notice that the mobility linearly decreases over temperature. This measuredresults are fitted to the following simplified model provided by [12].

µ(T ) = µ(T0)

(T

T0

)−1.5

(1)

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1.3.2 Threshold Voltage Variation over Temperature

The physical expression for the threshold voltage of a long channel MOS transistor without sub-strate biasing is given in Equation (2) according to [13].

Vth = φms −QSS

COX

± 2φF ± γn,p

√2φF (2)

where + sign represents NMOS and - sign represents PMOS. Here COX is the gate capacitanceper unit area, γn,p is the body-effect constant, QSS is the surface-state charge density, φF is theFermi potential of the bulk, and φms is the contact potential difference between the gate and thesubstrate. The physical expressions for φF and φms are given by:

φF =kT

qln

(NB

ni

)(3)

φms(NMOS) =kT

qln

(NBNg

ni2

)φms(PMOS) =

kT

qln

(Ng

NB

)(4)

where NB and Ng are the doping levels for the bulk and the gate, respectively.The temperature dependency of threshold voltage can be derived by taking the derivative of

these quantities with respect to temperature as follow:

δ(2φF )

δT=

1

T

(2φF −

Eg

q− 3kT

q

)(5)

δφms

δT=

1

T

(φms +

Eg

q+

3kT

q

), (NMOS) (6)

δφms

δT=φms

T, (PMOS) (7)

By substituting Equations(5) and (6) into the temperature derivative of Equation (2), one canobtain the NMOS threshold voltage temperature dependency given by the following equation [4].

δVth

δT=φms

T+

2φF

T+

γn√2φF

δφF

δT, (NMOS) (8)

For a typical CMOS process this dependency at room temperature, i.e., 300 K, results in avalue of -3.10 mV/C for the first term, 2.70 mV/C for the second term, and -0.4 mV/C forthe last term [4], which show that the threshold voltage of an NMOS transistor decreases when thetemperature increases.

On the other hand, the threshold voltage temperature dependency for a PMOS device becomes

δVth

δT=φms

T− 2φF

T− γp√

2φF

δφF

δT+

1

T

(Eg

q+

3kT

q

), (PMOS) (9)

where comparing to Equation (8), for a typical CMOS process this dependency at room tem-perature, i.e., 300 K, results in the decreased magnitude of first term which is about -0.5 mV/C,the negative sign of second and third terms and an extra added term with a value of about 4.3mV/C at 300 K [19]. As a result, by increasing the temperature the NMOS threshold voltage

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turns to be more negative and PMOS threshold voltage urns to be more positive, in other words, forboth NMOS and PMOS the absolute value of threshold voltage decreases as temperature increases.Also we notice that the change of PMOS threshold voltage is a bit faster than that of NMOS.

Such trend is also confirmed by experimental results showing that for a typical CMOS processfor both NMOS and PMOS a 0.5 V change of the threshold voltage happens while temperaturechanges from 25 C to 250 C [15]. Fig. 4 shows the measurement results of an NMOS transistoroperating over a such wide range of temperature variation (up to 250 C).

Figure 4: NMOS threshold voltage measurement vs. temperature ([15]).

For the next section we focus on the leakage current variation over temperature. A rule ofthumb to keep in mind in general to prevent relatively large channel leakage for high temperatureoperation is to use long channel devices, however, obtaining constant W

L, increasing the channel

length forces to increase the width as well which leads to extra junction leakage. Hence there isa trade of between these two different source of leakage currents that we have to take into ourconsideration as follows.

The high temperature variation causes two sources of leakage currents, one is sub-thresholdchannel leakage current and the other is junction-to-substrate leakage current. The sub-thresholdchannel leakage current exponentially increased due to decreased Threshold Voltage (A half-voltVt decreases from 25 to 250 C) and decreased Carrier Mobility ( At 250 C is less than 1

2the

mobility at 25 C), however all the building blocks of our SmartChip shown in Fig 2 operate inStrong Inversion, so we only consider the junction-to-substrate leakage current in our study here.This leakage current increased (About 5 orders of magnitude from 25 to 250 C) due to increasedIntrinsic Carrier Concentration ni(T ) that we discuss in the following section [4].

1.3.3 Junction (Reverse-Biased Diode) Leakage Current

This section refers to the work presented in [4] about high temperature impacts on leakage current.At room temperature, the leakage current is very small, usually on the order of pA. As temperature

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rises, two different effects cause the increase of the junction leakage current, drift current anddiffusion current as follow:

ILeak = IL.Diffusion + IL.Drift∼= −

qAni2(T )

ND

√DP

τ− qAni(T )W

2τVA (10)

where ni(T ) is the intrinsic carrier concentration, A is the area of the p− n junction, VA is thereverse bias voltage, which is negative, ND is the n − type doping density, W is the width of thejunction depletion region at applied VA, DP is the minority carrier diffusion constant, and τ is theminority carrier lifetime. The first term is diffusion current and the second term is drift current.

Drift (generation-recombination) current is due to the thermally generated electron-hole pairsin the depletion region. This current is proportional to ni(T ), and dominates to temperatures upto 100 − 150 C. It doubles the leakage current for every increase of 10 C based on the formulaprovided here.

Diffusion current is due to the thermally generated minority carriers away from the junctionarea. This current is proportional to ni

2(T ) and dominates at higher temperature 150− 300 C. It,however, quadruples the leakage current for every increase of 10 C.

Figure 5: Comparison of the Drain Junction Measured Leakage Currents for NMOS vs PMOS over theHigh Temperature Variation [5].

Measured drain junction leakage currents for both NMOS and PMOS devices are presentedin Fig 5. The leakage current increases about 5 orders of magnitude from 25 to 250 C. NMOSand PMOS have different doping concentrations. For NMOS the p-type epitaxial layer dopingconcentration is NA = 1015 cm−3, while for PMOS the n-well doping concentration is ND =4 × 1016 cm−3. More importantly, The concentration of minority carriers is a strong functionof the temperature but is inversely proportional to the doping concentration. Therefore, PMOStransistors have much less leakage current than NMOS in an n-well process and as depicted in this

7

plot the PMOS leakage current is about 3 orders of magnitude less than NMOS [4]. Therefore fortemperature robustness it is better to use more PMOS based structures in our building blocks ratherthan NMOS counterparts if possible.

1.4 High Temperature Compensation TechniquesThere are some improving techniques to decrease the impact of high temperature leakage currents,which in general depend on the specific requirements and the structure of the particular circuit,for instance zero temperature coefficient gate biasing, substrate biasing feedback, leakage currentfeedback cancellation, and constant-Gm biasing are addressed in [4].

Among these techniques, the constant-gm biasing is a classic and popular technique that iscommonly used in regular circuits [10] as well as high-temperature circuits [3, 4]. We will use thisstructure with a modification to improve its performance in the presence of temperature variations.The design will be discussed in more details in the next section.

Also threshold voltage drop and leakage current might cause the voltage offset problem. It hasbeen shown that auto-zeroing, chopper stabilization and correlated double sampling could reducethe voltage offset [16] and [17].

As explained earlier, in the SmartChip system, we would like to have a relatively low supplyvoltage (less or equal to 3 V which is available from a coin-type battery). Furthermore, to improvethe battery longevity, power consumption must be minimized. However, low DC bias currentmeans increased sensitivity to currents variations due to the increased leakage at high temperatures.Therefore, during the design, special care has to be given to this trade-off.

Since the spice model available from foundry is not valid at temperature beyond 125 C, wesimulate the circuit at 125 C and calculate the circuit parameters such as noise, power and voltageheadroom which could be affected by the high temperature effects. Knowing these impacts, wecould find and leave enough margin for 180 C operation as we need. Then we will fabricate atest chip and afterward measure the circuit results at the temperature of interest up to 180 C tocheck the functionality of the design. We are now looking at each component of our Smart Chipto explore its functionality at high temperature and its possible circuit topologies.

Figure 6: Layout of our fabricated SmartChip building blocks as a high-temperature test chip.

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2 Fabricated SmartChip Building Blocks using 0.13 µm BulkCMOS Technology

For our first fabrication run, we taped out some of the SmartChip building blocks using CMC CADtool in 0.13 µm Bulk CMOS Technology IBM design kit. Our chip consists the following blocks:a bias circuit, an OpAmp, a voltage reference, and an oscillator as the main SmartChip buildingblocks as well as different size switches, different size inverters and different type of resistors forstudying their temperature behavior. The lay out of our taped out test chip is presented in Fig 6and we explain each fabricated block in the following separate sections.

2.1 Bias Circuit ImplementationConsidering the simple current mirror circuit shown in Fig 7, we notice that since the referencecurrent created from a simple resistor, if we assume we have a variation in our supply, we canderive the output variations in current and voltage as follow:

Figure 7: Supply-Dependent Biasing.

So the output voltage is quite sensitive to the supply variation is this biasing, we now look atanother biasing to solve this problem.

2.1.1 Supply-Independent Bootstrapped Design

If we have a feedback from our output to sense our reference input like the bootstrapped circuitshown in Fig 8, by writing a KVL over M3 and M4 in top current mirror and assuming both currentare equal due to using long channel devices to eliminate channel length modulation we notice thatthere is no dependency on supply voltage at the output as derived equation in this figure shows,however it is still highly dependent on temperature due to µp, Cox and Rs that we discuss in detailslater on.

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Figure 8: Supply-Independent Bootstrapped Biasing.

2.1.2 Supply-Independent Start-Up for Bootstrap

It is worthy to mention that for switching supply voltage (On/Off) scenario, if the initial value ofour current reference in Fig 8 happens to be equal zero, it will remain zero for ever, so we need astart-up circuitry to ensure our previous assumption which is the reference current has the initialnon-zero value. The start-up circuitry could be a diode-connected transistor which is added intocircuit Fig 8 to provide a current path from VDD through M3 and M1 and forces M2 and M4 tostart conducting current.

...

2.1.3 Bias Circuit Design

A generic constant-gm biasing circuit is shown in Fig. 9.(a). The transconductance (gm) of devicesis a critical parameter affecting gain, bandwidth, and stability of an amplifier. Therefore, it isimportant to minimize gm variations over the desired temperature range of operation. A classicbias circuit for having constant-gm biasing [10] is shown in Fig. 9.(a). It is well-known that the gm

of a MOS transistor in saturation region, assuming long-channel devices and neglecting channellength modulation and the body effect, is given by [10]

gm =

√2µnCox

(W

L

)ID. (11)

Since gm is proportional to mobility, if one can generate a bias current that is inversely propor-tional to the mobility, then the gm of any transistor whose bias current is derived from such currentis ideally independent of the mobility. This is the task of the classic constant-gm bias circuit ofFig. 9.(a), and it can be shown that IB in this circuit (again, assuming long-channel devices andneglecting channel length modulation and the body effect) is given by [10]:

IB =2

µnCoxRB2

(√L1

W1

−√L2

W2

)2

. (12)

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Constant Gm Biasing

BIBR

DDV

1M

8M

6M

4M

2M

7M

5M

3M

( )a

9M

10M

11M

12M

NcasV

PcasVPbiasV

NbiasV

13M

14M

CMV

StartupCircuit

1BR

2BR

BR≡

( )b

TCNegative

TCPositive

Figure 9: (a) Bias circuit using constant-gm biasing. (b) our modification; using two resistors in series withnegative and positive TC.

From Eqs. 12 and 11, the gm of M2 is given by

gm2 =2

RB

(1− 1√

K

)(13)

where K is the relative sizing factor of M2 and M1; W2/L2

W1/L1. Thus gm2 to the first order of

approximation is independent of the bias current, and is inversely proportional to RB. Hence,although the bias current would increase due to change in the temperature, gm would ideally bestable over temperature if the bias resistor, RB, has a zero temperature coefficient (TC). In [3], themain core of the circuit of Fig. 9 have been used and with acceptable performance has been reportedwhenRB is implemented using a conventional poly resistor with TC of about 1000ppm/C. In thiswork, we further improve the performance by using an alternative implementation for this resistor.

First, in the 0.13µm CMOS technology that we are using, a resistor with TC on the order of100ppm/C is available. Using this resistor which is less sensitive to temperature further improvesthe temperature stability of the circuit. Second and the more important modification is the realiza-tion of RB using a series combination of two different type of resistors, one with a positive TC andanother with a negative TC (the magnitude of their temperature coefficients differ by a factor oftwo ), thus using a proper ratio of resistors we minimize the effective TC of the series combination,as shown in Fig. 9.(b). Implementing these two modifications, the temperature stability of the cir-cuit has been improved. We present our constant-gm performance over temperature in simulationresults section.

We can think of an alternative approach in which we still use constant-gm biasing circuit shown

11

in Fig. 9, but we try to make the bias current constant rather than gm. The constant bias currentensure to obtain constant voltage bias points to compensate temperature variations. If we againconsider Eq. 12, we notice that IB has two temperature dependent parameters; µn and RB

2. Weknow that µn linearly decreases over temperature as we discussed in previous section on Eq. ??,hence to make IB constant we can use a biasing resistor, RB, which has a positive temperaturecoefficient. Using this alternative constant-IB, we can further improve the temperature perfor-mance of the biasing circuit. We implemented and fabricated the circuit of both constant-gm andconstant-IB approaches as we discuss in more details in following section.

2.1.4 Bias Circuit Simulation Results

Since the foundry models for the 0.13 µm CMOS technology used here are only validated upto 125 C, all simulation results presented in this work are for temperatures up to 125 C. Thesimulation results of the bias circuit here and the amplifier in the next section are compared withthe corresponding simulation results presented in [4] as well as measured results reported in [3].

Ibias

25 50 75 100 125

Temperature (°C )

DC Response: Constant gm Biasing

I (µA)

10

10.5

11

11.5

12

12.5

13

13.5

Figure 10: Ibias versus Temperature variations of series combination of two different type of resistors forConstant gm Biasing circuitry.

First we look at our constant-gm approach using a series combination of two different type ofresistors with positive and negative TC. We simulated the circuit shown in Fig. 9.(a) to obtain IBvs temperature. The bias current IB changes from 10.3 µA at room temperature (25 C) and almostlinearly increases to 13.05 µA at 125 C as shown in Fig. 10. The reason for such linear increase inIB for constant-gm approach, while we almost keep RB value constant using a series combination

12

of positive and negative TC Resistors, is the µn temperature behavior which is linearly decreasingbased on Eq. 12.

In comparison, the same bias current in [4] varies from ∼ 9 µA to 14µA for the same temper-ature range. Both results are based on simulations. In [3] the measured bias current varies from∼ 15 µA to 20 µA for the same temperature variation.

In the next simulation we compare the two constant-gm and constant-IB approaches. In thissimulation we decrease the amount of bias current to achieve a lower power consumption. Thestraight line in Fig. 11 represents the constant-gm approach in which the bias current IB shows thesame characteristic as previous simulation. IB changes from 6.4 µA at room temperature (25 C)and almost linearly increases to 8.2 µA at 125 C. The IB variation over this temperature range inthe constant-gm approach is about 1.8 µA. The gm variation over this temperature range is about5 µΩ−1 from 82.51 to 77.55 µΩ−1. The reason for this minor variation of gm is due to overalltemperature coefficient of R1 and R2 in series which is not absolutely zero. In order to obtain abetter constant-gm characteristic we can properly adjust the ratio of R1 and R2 regarding to theirtemperature coefficient value.

The second plot in Fig. 11, however, illustrates the characteristic of the constant-IB approach.As we mentioned we use a positive temperature coefficient biasing resistor for RB to compensatethe negative temperature coefficient behavior of µn in Eq. 12. IB obtain its minimum value of6.26 µA at room temperature (25 C) and its maximum value of 6.68 µA at around 85− 90 C. IBbehaves almost as a flat curve in this temperature range. This IB variation over the temperaturerange of 25 − 125 C in the constant-IB approach is about 0.42 µA which is less than 1/4 of thatof constant-gm approach, 1.8 µA.

Figure 11: Comparison of Ibias versus Temperature Variations between constant-gm approach and constant-IB approach for Constant gm Biasing Circuitry.

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Figure 12: Ibias versus Temperature Variations of Different TC Resistors for Constant gm Biasing Circuitry.

In Fig. 12 we simulate different type of resistors having different temperature coefficient avail-able in IBM 0.13µ CMOS technology. As IB behavior moves from linear to almost flat curve, theTC of corresponding resistors changes from highest negative values to highest positive values aswe expected to compensate the negative temperature behavior of µ in Eq. 12. Hence we chooseone of the resistors with highest positive TC in this simulation for our constant-IB approach.

The summarized comparison between our bias circuit designs and [4] at simulation level aswell as [3] at implementation level is presented in Table 1. Our design used 0.13 um CMOStechnology while the other two used older 1.5 um CMOS technology. Both of our constant-gm andconstant-IB approaches show a lower power consumption as well as a lower temperature variationcompared to [4] and [3].

Design Cons-gm Cons-IB [4] (Sim.) [3] (Mes.)Technology (µm) 0.13 0.13 1.5 1.5

Vdd (V ) 2.5 2.5 5 5IB (µA) from 25 to 125 C 6.4 to 8.2 6.26 to 6.68 9 to 14 15 to 20

Table 1: Bias Circuit Performance Comparison.

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+oV− +

−+ −oV

DDV

biasV

Open loop OpAmp Block Diagram

OpAmpBias

Circuitry

DDV

+iV

−iV SCCMFB

DDV

Figure 13: Open-Loop OpAmp Block Diagram.

2.2 Amplifier Implementation2.2.1 Folded Cascode Amplifier Design

Our amplifier open-loop block diagram shown in Fig 13, consists of a core amplifier, a bias circuitand a switch-capacitor common-mode feedback. We used the constant gm bias topology which wepresented above as the bias circuit here, now we explain the implementation of other two blocks inmore details.Folded Cascode OpAmp2

DDV

7M 8M

3REFI

1M 2M+oV

2REFI

11M

−inV

NcasV

PcasV

5M 6M

3M 4M

9M 10M

NbiasV NbiasV

cmfbPbiasV

+inV −oV

1REFI

Figure 14: Folded-cascode amplifier.

Since a large-gain amplifier is desired (so that when the gain drops due to temperature in-crease [8, 9] it still has sufficient gain) and also it should be capable of driving capacitive loads

15

(e.g., input capacitance of the ADC), a fully differential folded-cascode topology [10], shown inFig. 14, with a classic switched-capacitor common-mode feedback (CMFB) circuit is chosen sinceit has been proved operational at high temperatures [8]. It also provides good stability performanceand has lower voltage headroom requirement as compare to the telescopic structure [10]. An am-plifier with NMOS input pair is chosen to to achieve larger gm with reasonable device sizes. Allamplifier bias voltages are generated using the bias circuit shown in Fig. 9.(a).

The CMFB is to maintain the common-mode output voltage around Vdd

2. Such a CMFB is

shown in Fig. 15.(a) and its functionality at high temperature is confirmed in [8]. Here, Vpbias,provided from the bias circuit is used in CMFB circuit to adjust VcmfbPbias for controlling the biasvoltage of the M9−10 of the amplifier. All the switches in this figure are CMOS transmission gates,shown in Fig. 15.(b). The constant gm biasing circuit is also used to generate VCM = Vdd

2= 1.25 V .

As shown in the simulation section the output common-mode voltage will settle to the desiredvoltage of 1.25 V after about 8 clock cycles.

SC CMFB

SWCCMC

+OV −OV

cmfbPbiasV

CMV

PbiasV

SWC

CMV

PbiasV

CMC

1Clk

1Clk

2Clk

2Clk

1Clk

1Clk

2Clk

2Clk

1Clk

NMOS

PMOS

1Clk

1Clk

GateonTransmissi( )b

( )a

Figure 15: Switched-capacitor CMFB.

2.2.2 Amplifier Simulation Results

The amplifier is simulated over the temperature range from 25 C to 125 C. At 125 C the biascurrents, IREF1, IREF2 and IREF3, shown in Fig. 14 are 60, 64, and 124 µA, respectively. Notethat the larger the bias currents, the less sensitive the performance of the circuit to the increase ofleakage at high temperature. Hence, there is a trade off between power performance and tempera-ture stability. The magnitude frequency response of the amplifier at 25 C (and 125 C) are shownin Fig. 16. The open-loop DC gain is 72 dB (69 dB) and the unity gain bandwidth of the amplifieris 4.25 MHz (4.13 MHz). The phase margin is relatively insensitive to temperature and is greaterthan 86 over the temperature range as shown in Fig. 17.

In [4], IREF1, IREF2 and IREF3 are chosen as 180, 270, and 450 µA at 125 C and the simulatedopen-loop gain of the amplifier is 57 dB.

16

GainACboth25-125

UGBW ~ 4.13-4.25 (MHz)Tem. from 125 to 25 ºC

at 125 ºC

at 25 ºC

Figure 16: Amplifier frequency response; open-loop gain over the temperature range from 25 C to 125 C.

Phase

UGBW 4 (MHz)

Phase Margin88 (deg)

at 25 (deg C)at 125 (deg C)

Figure 17: Amplifier frequency response; phase over the temperature range from 25 C to 125 C.

The amplifier transient response at 125 C is shown in Fig. 18. In this figure, 100 Hz inputsignal is used. The common-mode of the output voltage, at the beginning is close to the grounddue to the higher leakage current of NMOS as compared to that of PMOS transistors at 125 C.However, the CMFB circuit gradually sets the common-mode of the output to the desired valueof Vdd

2= 1.25 V. Table 2 summarizes the performance of the presented amplifier and compares

it with that of [3] and [4]. Here, the variations of IB correspond to the temperature range from25 C to 125 C, however, based on the measurement results presented in [3] this current contin-

17

Transient Gain2

2ddV

Figure 18: Amplifier transient response at 125 C. The CMFB gradually sets the common-mode of theoutput to the desired value of Vdd

2 = 1.25 V.

ues to increase (approximately) linearly as temperature goes beyond 125 C (up to approximately200 C). Given the similarity between the structure of the amplifier presented here and that of [3],it is expected that IB increases to 14.6 µA,DCgain remains above 67 dB, and the amplifier remainsfunctional as temperature increases to 180 C.

2.2.3 Amplifier Performance Comparison

The summarized comparison between our design and [4] at simulation level as well as [3] at im-plementation level is presented in Table 2. Our design used 0.13 um CMOS technology while theother two used older 1.5 um CMOS technology.

Design This Work [4] (Sim.) [3] (Mes.)Technology (µm) 0.13 1.5 1.5

Vdd (V ) 2.5 5 5IREF3 (µA) at 125 C 124 450 N.A.

Amp. Power (mW) at 125 C 0.62 4.5 N.A.IB (µA) from 25 to 125 C 10.3 to 13.05 9 to 14 15 to 20DCgain (dB) at 125 C 69 57 56

Table 2: Amplifier Performance Comparison.

Our design outdo in both power performance and temperature stability in comparison of ourdesign and [4] at simulation level. In the first part of Table 2 we look at power performance com-parison. Our power supply is half of the other two design and give us a better power performancein general. More specifically the power improving factor can be seen as 5(V )·450(uA)

2.5(V )·124(uA), which is

18

more than 6 times. In the second part of the table we look at temperature stability comparison.We obtained about half a bias current variation over the temperature range of 25-125 C due to ourdesign modification of constant gm biasing circuitry compared with [4] simulation result. Also theresults from [3] shows the same bias current variation as [4] with shifted to the 15-20 uA for thesame temperature variation, however, this results are at implementation level. In overall for theamplifier performance we achieved more than 10 dB open loop DC gain at high temperature, 125C. Since our SPIC simulations show a better performance compared with [4] up to 125 C, we canexpect its performance improvement for the test chip when we test the fabricated chip up to ourtarget temperature, 180 C.

2.3 Voltage Reference ImplementationFig 19 presents our voltage reference block diagram. It consists of a core voltage reference cir-cuitry, a single-ended amplifier including its bias circuit. We get into the implementation detailsof voltage reference core in this section. The single-ended amplifier has the same topology as ourfully differential amplifier and the only difference is to change the biasing of one output to make itsingle-ended. For the amplifier bias circuit, we used the same constant gm bias topology as before.

oV− +

−+

DDV

biasV

Voltage Reference Block Diagram

OpAmpBias

Circuitry

DDV

+iV

−iVVoltage

Reference

DDV

REFV

Figure 19: Voltage Reference Block Diagram.

The voltage reference is a dc voltage independent of three main parameters; temperature, sup-ply voltage, and process variations. The temperature has the most impact and it has the mostconcern of our study here. The supply voltage has the moderate level of importance and we useda bootstrapped, supply-independent biasing, design as we discussed priorly to compensate sup-ply variation of the voltage reference. The process variation has less effect since most processparameters vary with temperature, so if our design is temperature independent, then it is processindependent as well [10]. Therefore we explain how to design a temperature-independent voltagereference and discuss more details of the design and simulation results.

The solution to have almost constant voltage reference over the temperature is based on havingtwo different electrical characteristics; negative temperature coefficient (N-TC) voltage and posi-tive temperature coefficient (P-TC) voltage. Then by adding these two together with some properscaling we can obtain the constant voltage reference. The bipolar transistors have well-definedquantities for N-TC and P-TC. The bandgap reference is a common circuit to obtain proper tem-perature compensation solution using BJT transistors with N-TC and P-TC.

19

2.3.1 Negative Temperature Coefficient Voltage

The bipolar pn-junction temperature characteristic expresses as follows:

VBE = VT · ln(IC/IS) (14)

where IS ∝ µ · k · T · ni2. If we assume that the collector current is constant, we have the

derivative of base-emitter voltage as follows [10]:

δVBE

δT=VBE − (4 +m)VT − Eg/q

T(15)

where m is a constant about -1.5 and Eg is bandgap energy of silicon which is about 1.12 eVand has temperature dependency. For typical base-emitter voltage (750 mV ) at room temperature(300 K) we get the value of -1.5 mV/ K for this derivative. Therefore the bipolar base-emittervoltage has negative TC characteristic.

2.3.2 Positive Temperature Coefficient Voltage

Two bipolar transistors with unequal bias current have ∆VBE proportional to absolute temperature(PTAT) characteristic. Considering Eq 14 for Is1 = Is2 and small base current assumption, so wederive the following equation:

∆VBE = VT lnnI0IS1− VT ln

I0IS2

= VT lnn (16)

where n is the ratio of currents. If we take the derivative of the above equation we will find:

δ∆VBE

δT=k

qlnn (17)

which is a constant. Therefore the bipolar base-emitter voltage has positive TC characteristic.In the following section we explain how to create a constant voltage reference using N-TC andP-TC voltages.

2.3.3 Bandgap Reference

The idea is to properly add N-TC and P-TC voltages to cancel out the impact of temperature onreference voltage. The circuit which does this for us called bandgap. One bandgap example isshown in Fig 20. The opAmp ensures that the voltage at X is equal to the voltage at Y . So byapplying the KVL over the loop of Q1, R1 and Q2 we can find that the voltage of R1 is equal to∆VBE , so in this branch we add a N-TC voltage, base-emitter voltage of Q2, with a P-TC voltage,R1 voltage.

The example design values for R0, R1 and n in the Fig 20 is given as follow. For room tempera-ture and VBE =750mV we obtain δVBE/δT ≈ -1.5mV/ K and δVT/δT ≈+0.087mV/ K [10],hence for nominally zero TC we set:

lnn

(1 +

R0

R1

)· (0.087mV/ K) = 1.5mV/ K (18)

we may choose n = 31 and R0

R1= 4.

20

Figure 20: Bandgap Voltage Reference Example Circuit.

2.3.4 Bandgap Voltage Reference Design

The bandgap topology shown in Fig 21 is based on PTAT current which flow through a resistor tocreate a Positive Temperature Coefficient (P-TC) voltage to add up with a Negative TemperatureCoefficient (N-TC) voltage which is a base-emitter voltage of a BJT. In order to obtain a PTATcurrent we used our amplifier which has been designed and studied early on. therefore we canassume to have a high open-loop gain opAmp based on our simulation results.

Figure 21: Implemented Bandgap Voltage Reference.

We use PMOS transistors for PTAT current mirror in our design to take advantage of obtainingabout 3 orders of magnitude less leakage current in our wide range of temperature variation asstudied early on. To minimize the effect of channel length modulation in our PMOS mirror deviceswe use about a two times the minimum length transistor sizes, which decreases the mismatch

21

characteristic of copying the PTAT current. The output voltage reference,similar to our previousdiscussion, could be derived as follows [10]:

VREF = VBE6 +R2

R1

VT lnn (19)

Although the output voltage reference is depend on the resistor components which are tem-perature dependent, they essentially do not change the temperature characteristic of our P-TC andN-TC topology since the ratio of these resistors shows up in this equation and this ratio will cancelout this dependency.

Before discussing the simulation results, it is worthwhile to mention how we can physicallyimplement PNP BJTs in standard CMOS technology. A PNP transistor interestingly has a nicecompatibility in an n-well CMOS process. As presented in Fig 22, the emitter could be the p+inside the n-well region, the n-well itself considered as the base and the p-substrate is the collector.One issue is that the collector is inevitably connected to ground, so we can not easily use thecascade topology.

Figure 22: Implementation of PNP BJT in CMOS Technology.

2.3.5 Bandgap Voltage Reference Simulation Results

Our bandgap reference voltage circuit shown in Fig 21 is simulated to obtain the following re-sults. First we plot the negative TC voltage and PTAT current variations versus temperature shownin Fig 23. The Base-Emitter voltage of Q6 shows a N TC characteristic and current flowingthrough R2 has PTAT behavior as discussed above. Adding the NTC VBE and PTAT IR2 timesR2, R2=5.8 KΩ, almost compensates temperature variation and leads to a fairly stable voltagereference at the output.

Fig 24 zoom into the out put reference voltage variation over temperature for more variation de-tails. Vref changes from 1.2544 V at 0 C and linearly increases to 1.2620 V at 125 C which givesabout 7.6mV variation. It gives a voltage reference of 1.258.2 V with a variation of±3.8mV in therange of 0− 125 C. This result turns out to obtain a temperature coefficient (TC) of 48.3 ppm/Cbased on the following calculation.

22

Figure 23: Voltage Reference Output vs Temperature. NTC VBE added to PTAT Output Current times R2

Leads to Almost a Constant Vref over Temperature.

Figure 24: Voltage Reference Output vs Temperature.

23

Vref − TC =7.6 (mV )

1.2582 (V )× 1

(125− 0)(C)= 48.3 (ppm/C) (20)

It is worthwhile to notice that as shown in Fig 23 the NTC VBE changes from 832 mV at 0 C)and linearly decreases to 648 mV at 125 C which gives about 184 mV variation. The PTAT IR2

changes from 75 µA at 0 C) and linearly increases to 110 µA at 125 C which gives about 35 µAvariation. TheR2 value used in this simulation is about 5.8KΩ. Hence the PTAT voltage variation,IR2 ·R2, turns to be 35∗5.8 = 203mV. Therefore we can further improve the temperature stabilityof the output voltage by tuning the R2 values to achieve such a PTAT voltage variation less than203 mV in order to compensate this 7.6 mV of the output reference voltage.

This Work [20]Technology (µm) 0.13 0.6

Vdd (V ) 2.5 4Vref (V ) 1.2582 ±3.8 mV 1.1421 ±2.85 mVT-Range 0− 125 C 0− 100 C

T-Coefficient 48.3 ppm/C 50 ppm/C

Table 3: Voltage Reference Performance Comparison.

We compare our voltage reference performance with one of the state-of-the art recent workpresented in [20] in Table 3. Although we achieved less than ±1 mV extra variation for outputvoltage reference, our temperature range is 25% wider than that of [20] and therefore our temper-ature coefficient is less than the reported result in [20].

Our reference voltage gives a 1.25 V, however for our SmartChip we want a reference voltageof 2.5 V that we need to implement in the next fabrication. The idea is the same as what weexplained and presented in Fig. 21. The modification to achieve double output voltage is to stackup two diode connected BJT to add their corresponding VBE as presented in [10].

2.4 Oscillator Implementation

Oscillator Block Diagram

BiasCircuitry

DDV

RingOscillator

DDV

+oV

−oV

biasV

Figure 25: scillator Block Diagram.

24

Our oscillator design consists of a core oscillator circuitry, and a bias circuit as shown in Fig 25.The bias circuit is our constant gm bias topology the same as the one we used for voltage referenceand amplifier before. In this section we discuss the implementation details of the oscillator core.

The oscillator is another main building block of our SmartChip. Since off-chip components,such as crystal and capacitors used in oscillator are hard to obtain for high temperature environ-ments, also we plan to design a system on chip for our high temperature application, we do not useany off-chip component for the oscillator. To implement an all-silicon oscillator we use a fully-differential three-stage ring oscillator since high quality inductors are hard to obtain for traditionalLC oscillator topology in CMOS process.3-Stage Differential Ring Oscillator

+OV− +

−+ −OV

DDV

PbiasV

NbiasV

− +

−+

DDV

PbiasV

NbiasV

− +

−+

DDV

PbiasV

NbiasV

Figure 26: Block Diagram of Three-Stage Fully-Differential Ring Oscillator.

Fig 26 shows the block diagram of our three-stage differential ring oscillator which consists ofthree identical inverters as delay cells [10]. Using a 1st-order linear model, the transfer function ofeach delay cell can be approximated as follows:

Vo

Vi

=A0

1 + ω/ω0

(21)

where A0 is the small-signal low frequency gain and ω0 is the dominant pole, the 3-dB band-width. To satisfy the oscillation criterion, Av must be at least 2. It oscillates at a frequency of:

fosc =

√3ω0

2π(22)

which means the ring oscillator frequency is the frequency with 60 phase shift per delay cellstage [10].

25

Oscillator Delay Cell; Inverter

DDV

1M 2M

7MNbiasV

+iV −iV

−oV +oVPbiasV

5M 6M3M

4M

LC LC

Figure 27: 1-Stage Delay Cell of the Ring Oscillator.

2.4.1 Oscillator Delay Cell Design

For our delay cell inverter, we used a typical fully-differential 1-stage OpAmp with additionaldiode-connected PMOS load at the output [21] as illustrated in Fig 27. This topology called sym-metric load design which obtain better noise performance than with single PMOS load, and it iseasier to achieve the necessary voltage gain presented in [22]. The oscillation frequency is propor-tional to 1

RoCo= gm3,4

CL/2, and the gain of each delay cell, inverter gain, is determined as follows:

Ainv = gm1,2Ro =gm1,2

gm3,4

(23)

2.4.2 Oscillator Simulation Results

In Fig 28 we demonstrate the output voltage of each delay cell in our three-stage ring oscillator.You can see that each delay cell introduces an extera phase shift to the signal which is related tothe value of CL. With CL in order of 10 pF the transient simulation shows that the ring oscillatorhas an oscillation frequency about 500 KHz.

Using our already introduced constant-gm-biasing circuitry shown in Fig. 9 to bias VNbias andVP bias of our oscillator delay cells shown in Fig 27, we got a frequency variation of about ±20%from room temperature up to 125 C. In this biasing circuitry, similar to what [4] did, we biasedthe NMOS tail current source, VNbias in Fig 27, using NMOS diode-connected biasing transistorM1 in Fig. 9 and similarly we biased the PMOS loads, VP bias in Fig 27, using PMOS diode-connected biasing transistor M8 in Fig. 9. We noticed that, however, if we bias both NMOS tailcurrent source and PMOS load of each delay cell with a same type of biasing transistor, let say M6

and M8 PMOS transistors for example, we get a better temperature stability over the temperature

26

Figure 28: 3-Stage Delay Oscillator Outputs.

range. This is due to the fact that both cells face kine of the same gate voltage change and theoutput signal shift a bit due to this offset. The new frequency variation decreased to ±10% overthe range of 25 − 125 C illusterated in Fig 29. As this transient simulation shows the oscilationfrequency is about 450 KHz at 25 C and it goes up to 550 KHz as temperature increases to 125 C.

This oscillator design is what we have fabricated which does not include any temperature com-pensation technique. Based on the state-of-art literature and patents for oscillator temperature com-pensation, there are an extra temperature compensator block which is usually rather complicatedcircuitry. For instance, [23] used an adjusting external DC voltage and a varactor to compensatetemperature variation for a crystal oscillator, in [24] a temperature compensation circuit includea control transistor which provides a voltage to the control terminals of the delay stages which isinversely proportional to the threshold voltage of the control transistor, [25] is based on a compli-cated compensator circuitry and an external precision resistor, this one [26] also has a complicatedcompensator circuitry using an adding/removing current source as a compensator, in [27] the au-thors control the PMOS gate voltage as the compensator using an extra bias generator circuitry,and finally [28] uses the bias circuit as a source of temperature compensation using a complicatedcircuitry.

In contrast to the mentioned above state-of-the-art work, we came up with a temperature com-pensation idea which is based on rather a simple structure. The idea is to use a varactor and ouralready existing bias circuit as a temperature compensator without any extra complicated compen-sator circuity. As we noticed on the bias circuit and oscillator simulations both the biasing voltageand output frequency go up duo to temperature increase. Hence if we put a varactor to the output

27

Figure 29: Oscillator Output vs Temperature.

of oscillator and control it using voltage from our biasing circuitry to increase the load capacitance,CL, we can decrease the output frequency and compensate the temperature variation, ideally backto 500 KHz even at 125 C. We are working on this idea for next fabrication run.

2.5 Additional Temperature Testing BlocksIn order to test and measure the temperature behavior of our designed SmarChip building blocks weput different structures of our circuit. For gm bias circuit, we fabricated our bias circuit consistingboth constant-gm and constant-IB approaches. For amplifier block, we fabricated one open-loopand one unity-gain structure. For voltage reference and oscillator blocks, we also fabricated themusing both constant-gm and constant-IB approaches as their bias circuit.

In addition to above SmartChip building blocks, we fabricated other useful circuitry to inves-tigate the behavior of our circuits and model our design more accurately in high temperature. Forinstance, we put an array of different resistors, different size switches, and different size invertersfor this purpose.

3 Conclusion and Future Work

3.1 OverviewWe proposed a feasible plan to build a SOC smart chip which is able to withstand high tempera-ture operation while maintaining the low power consumption requirement. The design of a high-

28

temperature, low-power, and low-voltage bias circuit, amplifier, voltage reference and oscillatorin 0.13 µm CMOS technology has been discussed. By minimizing the TC of the bias resistor inthe constant-gm biasing circuit of the amplifier, the temperature stability of the bias current is im-proved. Also our simulation results shows that our amplifier, and voltage reference design obtainperformance improvement in some degree of power efficiency and temperature stability over thetemperature range of 25-125 C. Based on the simulation results and previously reported resultson successful implementation of similar amplifier structure at high temperatures, it is expectedthat the amplifier can robustly operate at temperatures as high as 180 C (the maximum ambienttemperature inside a wood chip digester used for pulp production).

We presented our primary research results at the IEEE international workshop [29] in summer2008. Also the constant-gm biasing approach as well as the amplifier performance published inanother IEEE international conference [30] in summer 2009. Further research innovations will berequired at both improving our fabricated blocks and designing the remaining SmartChip buildingblocks to improve the overall system and power performance. We discuss our planned work and atime line for the remaining tasks in the following section. The intention of our research is eventu-ally to design, fabricate, and test a robust SOC sensor interface in bulk CMOS technology to verifythe design, making use of design and fabrication services offered by the Canadian MicroelectronicsCorporation.

3.2 Planned WorkFor the remaining tasks of implementing SmartChip as a SOC block, we consider and focus on thefollowing steps.

For the power management block of our system shown in Fig [SOCsys], we plan to regulate thebattery voltage on-chip as well as improve our 1.25 V voltage reference to a 2.5 V voltage referencein order to provide supply voltage out of the battery both for sensor and electronics. Furthermorefor our oscillator, we want to implement the proposed temperature compensation technique in 2.4to improve the temperature stability of our fabricated oscillator. The main remaining block is ADC.ADC design in general consists of designing a comparator, integrator and a sampling amplifierwhich could be a correlated double sampling switch capacitor amplifier [4]. Also if we have time,we focus on memory and logic control design as well. A non-volatile memory, flash memory forexample, is needed in our smart chip to record data. We have been addressed early studies offlash memories in high temperature environment [29], but it needs more research. Flash memories,however, need special fabrication process, hence for the prototype we have planed to create amemory structure in standard CMOS with single write and multiple-read capabilities.

The time wise progress for our achieved work as well as a time line for the remaining taskscan be summarized as follow. During the first year of the program, I have completed all of myrequired course work while I was studying the state-of-the-art literature. The outcome of myliterature reviews and one of my courses presented in [29]. In the second year, I started designingof some SmartChip building blocks such as bias circuit, Amplifier, Voltage reference and oscillatorand fabricated our first prototype chip in March 2009. Meanwhile I was writing some part of ourachievement and submitted the paper to an IEEE international conference. The paper published in[30].

We plan to test our first prototype chip on September 2009 which takes about a month. Basedon the measurement results of the chip we target to publish journal and/or conference paper. On

29

October 2009 working on my qualification exam. Then spending three to four months I fabricatedour second chip on February 2010 containing ADC block including comparator, integrator andcorrelated double sampling amplifier as well as the proposed temperature compensated oscillator.We start working on our test plan and PCB design for testing of chip for a month and working onthe design and fabrication of our entire system as a SmartChip. On September 2010 we measurethe second test chip and fabricate the whole system on November-December 2010. Then We workon publishing our measurement results and I will start writing my thesis before testing the finalchip on July-August 2011, and therefore, I plan to defend my thesis in August 2011. The abovetime line for completion of the research is listed in Table 4.

Timeline Work ProgressFirst year course work, literature review, first publication completedSecond year Des.& Fab. of Bias Crt., OpAmp, Vref , Osc. and second publication completedMay 2010 Testing plan for first chip and working on block simulations ongoingSep. 2009 Testing and measurement of the first fabricated prototype to be doneOct. 2009 publishing our measurement results, my qualification exam to be doneFeb. 2010 Fabricating 2nd chip; Comparator, Integrator, CD OpAmp, ADC, Osc. to be doneMar. 2010 Testing plan and working on entire system Des. and Fab. to be doneSep. 2010 Testing and measurement of the second fabricated prototype to be doneDec. 2010 Fabricating final entire system to be doneJan. 2011 Publication and thesis writing to be doneAug. 2011 Measurement of the final chip and thesis defense to be done

Table 4: Plan for completion of my research

References[1] T.-H. Chen and L. T. Clark and K. E. Holbert, “Memory design for high temperature radiation environments,”

IEEE International Reliability Physics Symposium, pp.107-114, April 27-May 1 2008.

[2] J. L. Prince and B. L. Draper and E. A. Rapp and J. N. Kronberg and L. T. Fitch, “Performance of DigitalIntegrated Circuit Technologies at Very High Temperatures,” IEEE Transactions on Components, Hybrids, andManufacturing Technology, vol. CHMT-3, no.4, pp. 571-579, Dec. 1980.

[3] X. Yu and S. L. Garverick, “Mixed-Signal, 275 C Instrumentation Amplifier in Bulk CMOS,” in Proc. IEEECustom Integrated Circuits Conference, pp. 641-644, Sep. 2005.

[4] X. Yu, High-Temperature Bulk CMOS Integrated Circuits for Data Acquisition, PhD Thesis, Case Western Re-serve University, 2006.

[5] P. C. de Jong and G. C. M. Meijer and A. H. M. van Roermund, “A 300 C dynamic feedback instrumentationamplifier,” IEEE Journal of Solid-State Circuits, vol. 33, no.12, pp. 1999-2009, Dec. 1998.

[6] J. Haslett and F. Trofimenkoff and I. Finvers and F. Sabouri and R. Smallwood, “High temperature electronicsusing silicon technology,” in Proc. IEEE International Solid-State Circuits Conference, pp. 402-403, 4081, Feb.1996.

[7] I. G. Finvers and J. Haslett and F. Trofimenkoff, “A high temperature precision amplifier,” IEEE Journal of Solid-State Circuits, vol. 30, no.2, pp. 120-127, Feb. 1995.

[8] C. Davis and I. Finvers, “A 14-bit high-temperature Σ∆ modulator in standard CMOS,” IEEE Journal of Solid-State Circuits, vol.38, no.6, pp. 976-986, June 2003.

30

[9] F. Shoucair, “Potential and problems of high-temperature electronics and CMOS integrated circuits (25-250 C)–An overview,” Microelectronics Journal, vol. 22, no. 2, pp. 39-53, April 1991.

[10] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill Book Company, 2001.

[11] F. P. McCluskey and R. Grzybowski and T. Podlesak, High Temperature Electronics, CRC Press, Boca Raton,1997.

[12] M. Willander and H. L. Hartnagel, High Temperature Electronics, Chapman & Hall, London, 1997.

[13] S. M. Sze,Physics of Semiconductor Devices, 2nd edition, New York: Wiley, 1981.

[14] F. S. Shoucair, “Scaling, subthreshold and leakage current matching characteristics in high temperature (25-250 C) VLSI CMOS devices,” IEEE Transactions on Components, Hydrid, Manufacting Technology, vol. 12,no., pp. 780-788, Dec. 1991.

[15] F. S. Shoucair, “Design considerations in high temperature analog CMOS integrated circuits,” IEEE Transactionson Components, Hydrid, Manufacting Technology, vol. CHMT-9, no.3, pp. 242-251, Sep. 1986.

[16] C. C. Enz and G. C. Temes, “Circuit techniques for reducing the effects of op-amp imperfections: autozeroing,correlated double sampling, and chopper stabilization,” Proceedings of the IEEE, vol. 84, no.11, pp. 1584-1614,Nov. 1996.

[17] K. Haug and G. C. Temes and K. Martin, “Improved offset-compensation schemes for SC circuits,” in Proc.IEEE International Symposium on Circuits and Systems, pp. 1054-1057, May 1984.

[18] J. C. Candy, “A Use of Limit Cycle Oscillations to Obtain Robust Analog-to-Digital Converters,” IEEE Trans-actions on Communications, vol. COM-22, no.3, pp. 298-305, March 1974.

[19] F. M. Klaassen and W. Hes,“On the temperature coefficient of the MOSFET threshold voltage,”Solid State Elec-tron, vol. 29, no.8, pp. 787-789, 1986.

[20] K. N. Leung and P. K. T. Mok and C. Y. Leung, “A 2-V 23-µA 5.3-ppm/C Curvature-Compensated CMOSBandgap Voltage Reference,” IEEE Journal of Solid-State Circuits, vol.38, no.3, pp. 561-564, March 2003.

[21] J. Maneatis and M. Horowitz, “Precise delay generation using coupled oscillators,” IEEE Journal of Solid-StateCircuits, vol. 28, no.12, pp. 1273-1282, December 1993.

[22] L. Dai and R. Harjani, “Comparison and analysis of phase noise in ring oscillators,” IEEE International Circuitsand Systems in Proceeding, vol. 5, pp. 77-80, 2000.

[23] “Temperature compensation circuit for a crystal oscillator and associated circuitry,” United States Patent,5777524, http://www.freepatentsonline.com/5777524.html.

[24] “Voltage and temperature compensated FET ring oscillator,” United States Patent, 4547749,http://www.freepatentsonline.com/4547749.htm.

[25] “Ring oscillator circuit having improved frequency stability with respect to tempera-ture, supply voltage, and semiconductor process variations,” United States Patent, 5072197,http://www.freepatentsonline.com/5072197.html.

[26] “Low-gain, range programmable, temperature compensated voltage controlled,” United States Patent,5317287,http://www.google.ca/patents?hl=enlr=vid=USPAT5317287id=EUZ8AAAAEBAJoi=fnddq=temperature +com-pensation+ring+oscillator+varactor.

[27] K. Sundaresan and P. E. Allen and F. Ayazi, “Process and temperature compensation in a 7-MHz CMOS clockoscillator,” IEEE Journal of Solid-State Circuits, vol.41, no.2, pp. 433-442, February 2006.

[28] V. C. de Beaupre and W. Rahajandraibe and L. Zaid and G. Bas, “A CMOS 2.45-GHz ring oscillator withtemperature compensation,” IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp.1-4, December 2005.

[29] N. Sadeghi and S. Mirabbasi and A. Ivanov and C. P. J. Bennington, “Flash Memory Testing Under High Tem-perature Variation,” IEEE International Mixed-Signal, Sensors, and Systems Test Workshop, June 2008.

[30] N. Sadeghi and S. Mirabbasi and C. P. J. Bennington, “A 2.5 V 0.13 µ m CMOS Amplifier for a High-Temperature Sensor System,” IEEE International NEWCAS-TAISA Conference, Accepted in Press, June 2009.

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