l.royer – calice manchester – sept. 2008 a 12-bit cyclic adc dedicated to the vfe electronics of...
DESCRIPTION
L.Royer – Calice Manchester – Sept Proposal: one ADC per channel Short analog sensitive wires from memory to ADC A digital Data Bus far from sensitive analog signals Only ADCs of triggered channels powered ON Conversions of channels done in parallel Integrity of analog signals saved Power saved Pedestal dispersion of ADC "added" to the dispersion of the analog part …. but calibrated With one-ADC-per-channel architecture: No "fast" ADC requiredTRANSCRIPT
L.Royer – Calice Meeting @ Manchester – Sept. 2008
A 12-bit cyclic ADC dedicated to the VFE electronics of Si-W Ecal
Laurent ROYER, Samuel MANENLPC Clermont-Ferrand
L.Royer – Calice Meeting @ Manchester – Sept. 2008
C
AMPLI. 1
10
100
Fast
Shaper
Shaper
Shaper
Shaper
Chargepre-amplifier
Discri.
ANALOG
SCA
MEMORY
ANALOG
DIGITAL
TO
ADC
10 -12 bits
channel n
TRIGGER
SCAchannel n+1
pre-amplified signal
filtered signal
ADC
10 -12 bits
2
Main requirements for the ADC:– Ultra low power:
2.5µW/ch (10% of the VFE power budget) Power pulsing needed
– Resolution: 10 bits if 3-gain shaping 12 bits if 2-gain shaping
– Time of conversion: time budget of 500 µs to convert all data of all triggered channels
– Die area: as small as possible… (0.225 mm2 per each channel of Skiroc
without ADC)
VFE electronics of Si-W Ecal
Analog electronics busy
1ms (.5%)
A/D conv..5ms (.25%)
DAQ.5ms (.25%)
IDLE MODE198ms (99%)
L.Royer – Calice Meeting @ Manchester – Sept. 2008
Proposal: one ADC per channel
Short analog sensitive wires from memory to ADC A digital Data Bus far from sensitive analog signals
Only ADCs of triggered channels powered ON
Conversions of channels done in parallel
Integrity of analog signals saved
Power saved
Pedestal dispersion of ADC "added" to the dispersion of the analog part …. but calibrated
With one-ADC-per-channel architecture:
preamp
shaper 10
analog memory
analog memory
shaper 1
12-bit ADC
preamp
shaper 10
analog memory
analog memory
shaper 1
12-bit ADC
preamp
shaper 10
analog memory
analog memory
shaper 1
12-bit ADC
preamp
shaper 10
analog memory
analog memory
shaper 1
12-bit ADC...
.32 channels ...
.
preamp
shaper 10
analog memory
analog memory
shaper 1
12-bit ADC
preamp
shaper 10
analog memory
analog memory
shaper 1
12-bit ADC
preamp
shaper 10
analog memory
analog memory
shaper 1
12-bit ADC
preamp
shaper 10
analog memory
analog memory
shaper 1
12-bit ADC
....
32 channels ....
Dig
ital D
ata
Bus
Digital electronics
64-channel VFE chip
No "fast" ADC required
L.Royer – Calice Meeting @ Manchester – Sept. 2008
InputGain Sub-ADC
DAC
b1
b2
4
Two candidates for the architecture of the ADC
Pipeline ADC
Cyclic ADC
L.Royer – Calice Meeting @ Manchester – Sept. 2008
Pipeline and Cyclic performance
5
Cyclic PipelineResolution 12 bits 12 bits
Time for one conversion 12 clock periods 1 clock period(1)
Power consumption (norm.) 1 12 down to 6(2)
Integrated power cons.(time * power cons.)
12 12 down to 6(2)
Area 1 12 down to 10(3)
1 after a latency of 12 clocks period for the first conversion2 if a power optimization on each stage is implemented3 if a capacitor size optimization per each stage is implemented
L.Royer – Calice Meeting @ Manchester – Sept. 2008
A 12-bit cyclic ADC (1)The 12-bit cyclic ADC prototype designed @ LPC Clermont:
Sent to fabrication in March 08, 10 chips delivered with delay in July Technology: 0.35 µm CMOS Austriamicrosystems ADC designed with the validated building blocks (Amplifier & Comparator) of
our 10-bit pipeline ADC (published in IEEE NS in June 08) but optimized for the 12-bit precision requirement
enhanced building blocks tested with a dedicated chip (July 07) 1.5 bit architecture (2 bits per cycle)
relaxed constraints on offsets of comparators External bits processing (deserializer & 1.5bit algorithm) Power pulsing system implemented
6
Layout of the chip
L.Royer – Calice Meeting @ Manchester – Sept. 2008
A 12-bit cyclic ADC (2) Performance of the cyclic ADC:
Improved architecture: calculation of two bitsduring one clock period Time of conversion: 7µs w/ 1MHz clock freq. 1 ampli. + 2*2 comp. + 2 capacitors arrays Consumption: 4 mW/3.5V Integrated cons. with power pulsing:
0.7 µW with analog memory depth of 5 events 2.2 µW with analog memory depth of 16 events
Area: 0.175 mm2
7
2 conversion phases with a single ampli.
C2
AMPLIFIER
C4
VREF1
bit1_H
bit1_L
VTH_H
VTH_L VREF2DAC
PHASE 1
Sampling
Amplification
clk+
VTH_H
VTH_L DACclk-
C2
AMPLIFIER
C4
VTH_H
VTH_L DAC
PHASE 2
Sampling
Amplification
clk+
bit2_H
bit2_L
VTH_H
VTH_LVREF1DACclk-VREF2
Optimized Cyclic
Pipeline
Resolution 12 bits 12 bits
Time for one conversion
12 7 clock periods
1 clock period(1)
Power consumption
1 1.1 12 down to 6(2)
Integrated power 12 7.7 12 down to 6(2)
Area 1 1.5 12 down to 10(3)
L.Royer – Calice Meeting @ Manchester – Sept. 2008
Very First results of measurement
1 MHz clock
C2
AMPLIFIER
C4
VREF1
bit1_H
bit1_L
VTH_H
VTH_L VREF2DAC
PHASE 1
Sampling
Amplification
clk+
VTH_H
VTH_L DACclk-
C2
AMPLIFIER
C4
VTH_H
VTH_L DAC
PHASE 2
Sampling
Amplification
clk+
bit2_H
bit2_L
VTH_H
VTH_LVREF1DACclk-VREF2
"Start conversion " signal
1 2 34
56
11
10
12
8
97
Oscillogram of the chip under test
L.Royer – Calice Meeting @ Manchester – Sept. 2008
Very First results of measurement
1 MHz clock
C2
AMPLIFIER
C4
VREF1
bit1_H
bit1_L
VTH_H
VTH_L VREF2DAC
PHASE 1
Sampling
Amplification
clk+
VTH_H
VTH_L DACclk-
C2
AMPLIFIER
C4
VTH_H
VTH_L DAC
PHASE 2
Sampling
Amplification
clk+
bit2_H
bit2_L
VTH_H
VTH_LVREF1DACclk-VREF2
"Start conversion " signal
1 2 34
56
11
10
12
8
97
Oscillogram of the chip under test
L.Royer – Calice Meeting @ Manchester – Sept. 2008
Measured Integral Non-Linearity (INL)
L.Royer – Calice Meeting @ Manchester – Sept. 2008
Both simulated and measured INL
L.Royer – Calice Meeting @ Manchester – Sept. 2008
Measured Differential Non-Linearity (DNL)
L.Royer – Calice Meeting @ Manchester – Sept. 2008
Noise measurement
Code fluctuation @ 1V
Standard deviation = 0.84 LSB (420µV)
L.Royer – Calice Meeting @ Manchester – Sept. 2008
Conclusion
A 12-bit cyclic ADC prototype, dedicated to Calice, is fabricated and
under test
First measured performance is in accordance with simulations
(speed, resolution, power cons., noise)
Next measurements have to evaluate:
Dispersion of the performance on the 10 chips produced
Dependence of performance with clock frequency
Performance of the Power pulsing (recovery time of the biasing)
Results will be presented during the next IEEE meeting in Dresden
14
L.Royer – Calice Meeting @ Manchester – Sept. 2008
preamp
shaper 10
analog memory
analog memory
shaper 1
preamp
shaper 10
analog memory
analog memory
shaper 1
preamp
shaper 10
analog memory
analog memory
shaper 1
preamp
shaper 10
analog memory
analog memory
shaper 1
....
n channels ....
Dig
ital D
ata
Bus
Digital electronics
64-channel VFE chip
12-bit ADC
MUX
analog
analog memory
analog memory
12-bit ADC
MUX
analog
analog memory
analog memory
analog memory
analog memory
analog memory
analog memory
n channels
One ADC per n channel