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LS2088A Security (SEC) Reference Manual Also supports LS2048A, LS2084A and LS2044A Document Number: LS2088ASECRM Rev. 0, 04/2018

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LS2088ASECRM, LS2088A Security (SEC) Reference Manual - Reference ManualAlso supports LS2048A, LS2084A and LS2044A
Document Number: LS2088ASECRM Rev. 0, 04/2018
LS2088A Security (SEC) Reference Manual, Rev. 0, 04/2018
2 NXP Semiconductors
Chapter 2 Feature summary
Chapter 3 SEC implementation
3.3 SEC Export-Controlled vs. non-Export-Controlled Versions.................................................................................... 92
4.1 Security Monitor (SecMon) security states.................................................................................................................95
4.1.1 The effect of security state on volatile keys...............................................................................................96
4.1.2 The effect of security state on non-volatile keys....................................................................................... 97
4.2 Keys available in different security modes.................................................................................................................97
4.2.1 Keys available in trusted mode.................................................................................................................. 97
4.2.3 Keys available in non-secure mode........................................................................................................... 98
Chapter 5 SEC hardware functional description
5.1 System Bus Interfaces.................................................................................................................................................102
5.1.1.3 DMA write-efficient transactions.......................................................................................... 103
5.1.1.4 DMA bursts that may read past the end of data structures.................................................... 104
5.1.2 Register interface (IP bus)..........................................................................................................................105
NXP Semiconductors 3
5.3.1.2 Managing the input rings....................................................................................................... 122
5.3.1.3 Managing the output rings..................................................................................................... 123
5.3.2.2 Building job descriptors for QI jobs...................................................................................... 129
5.3.2.4 Tracking the completion order of QI jobs..............................................................................130
5.3.2.5 Initializing the Queue Manager Interface.............................................................................. 130
5.3.2.6 Done/error notification for QI jobs........................................................................................ 131
5.3.3.1 Receiving frame descriptors from AIOP............................................................................... 133
4 NXP Semiconductors
5.3.3.5 Initializing the AIOP interface...............................................................................................136
5.5.1.1 Alignment blocks................................................................................................................... 147
6.1 Frame queues.............................................................................................................................................................. 151
6.1.1 Dequeue response...................................................................................................................................... 152
NXP Semiconductors 5
7.1 Job descriptors............................................................................................................................................................ 175
7.3.2.1 Error sharing.......................................................................................................................... 183
7.7.2 Command properties.................................................................................................................................. 197
7.7.4.3 Transferring meta data........................................................................................................... 202
6 NXP Semiconductors
7.12 ECPARAM command................................................................................................................................................ 237
7.13 STORE command....................................................................................................................................................... 241
7.18.2 PKHA OPERATION: Arithmetic Functions.............................................................................................293
7.19 SIGNATURE command............................................................................................................................................. 305
NXP Semiconductors 7
8.1 Conformance considerations.......................................................................................................................................333
8.2.4 Operation of the discrete-log key-pair generation function....................................................................... 335
8.3 Using the Diffie_Hellman function............................................................................................................................ 340
8.3.4 Outputs from the Diffie-Hellman function................................................................................................ 341
8.3.5 Operation of the Diffie-Hellman function................................................................................................. 341
8.4 Generating DSA and ECDSA signatures....................................................................................................................342
8.4.1 Inputs to the DSA and ECDSA signature generation function..................................................................343
8.4.2 Assumptions of the DSA and ECDSA signature generation function.......................................................343
LS2088A Security (SEC) Reference Manual, Rev. 0, 04/2018
8 NXP Semiconductors
8.4.4 Operation of the DSA and ECDSA signature generation function ...........................................................344
8.4.5 Notes associated with the DSA and ECDSA Signature Generation function............................................344
8.5 Verifying DSA and ECDSA signatures......................................................................................................................347
8.5.1 Inputs to the DSA and ECDSA signature verification function................................................................ 348
8.5.2 Assumptions of the DSA and ECDSA signature verification function..................................................... 348
8.5.3 Outputs from the DSA and ECDSA signature verification function......................................................... 348
8.5.4 Operation of the DSA and ECDSA signature verification function ......................................................... 348
8.5.5 Notes associated with the DSA and ECDSA Signature Verification function ......................................... 349
8.6 RSA Finalize Key Generation (RFKG)...................................................................................................................... 352
9.1.3.1 PDB format for IPsec ESP Transport (and Legacy Tunnel) encapsulation...........................367
9.1.3.2 Common PDB format descriptions for IPsec ESP Transport (and Legacy Tunnel)
decapsulation..........................................................................................................................370
9.1.3.3 Overriding ESP Transport (and legacy Tunnel) PDB content with the DECO Protocol
Override Register................................................................................................................... 373
9.1.3.5 Common PDB format descriptions for IPsec ESP Tunnel decapsulation............................. 377
9.1.3.6 Overriding ESP Tunnel PDB content with the DECO Protocol Override Register.............. 380
9.1.3.7 IPsec ESP encapsulation CBC-specific PDB segment format descriptions.......................... 382
9.1.3.8 IPsec ESP encapsulation AES-CTR-specific PDB segment format descriptions..................383
9.1.3.9 IPsec ESP encapsulation AES-CCM-specific PDB segment format descriptions................ 383
9.1.3.10 IPsec ESP encapsulation AES-GCM-specific PDB segment format descriptions................ 384
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NXP Semiconductors 9
9.1.4.1 Encapsulating the IP header in tunnel mode..........................................................................387
9.1.4.2 Encapsulating the IP header in transport mode......................................................................387
9.1.4.3 Process for IPsec ESP Transport (and Legacy Tunnel) encapsulation.................................. 388
9.1.5 IPsec ESP Cryptographic Encapsulation................................................................................................... 389
9.1.5.2 Process for IPsec encapsulation when using AES-CTR........................................................ 391
9.1.5.3 Process for IPsec encapsulation when using AES-CCM....................................................... 392
9.1.5.4 Process for IPsec encapsulation when using AES-GCM.......................................................394
9.1.6 IPsec ESP Transport (and Legacy Tunnel) decapsulation procedure overview........................................ 395
9.1.6.1 IPsec ESP Transport Mode outer IP header decapsulation procedure...................................397
9.1.6.2 IPsec ESP Transport (and Legacy Tunnel) outer IP header decapsulation procedure
(tunnel mode)......................................................................................................................... 397
9.1.7.2 Process for IPsec decapsulation when using AES-CTR........................................................ 400
9.1.7.3 Process for IPsec decapsulation when using AES-CCM....................................................... 401
9.1.7.4 Process for IPsec decapsulation when using AES-GCM.......................................................402
9.1.7.5 Use of SPI and the sequence number in decapsulation..........................................................403
9.1.7.6 Optional use of ESN in ESP decapsulation........................................................................... 404
9.1.7.8 ICV checking during IPsec ESP decapsulation..................................................................... 406
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10 NXP Semiconductors
9.1.8.2 Outer IP Header handling with UDP-encapsulated-ESP....................................................... 408
9.1.8.3 ESP Tunnel Outer IP Header manipulation........................................................................... 408
9.1.9 IPsec ESP tunnel decapsulation overview................................................................................................. 409
9.1.9.3 Manipulation of the Inner IP Header during ESP Tunnel decapsulation...............................411
9.1.9.4 Decapsulation Output Frame Length..................................................................................... 411
9.2 SSL/TLS/DTLS record encapsulation and decapsulation overview.......................................................................... 412
9.2.1 Programming and processing details common to all versions of SSL, TLS, and DTLS...........................413
9.2.1.1 PDB use and format for SSL, TLS, and DTLS encapsulation and decapsulation.................413
9.2.1.1.1 PDB for SSL, TLS, and DTLS when a Block Cipher is used.......................... 414
9.2.1.1.2 PDB for SSL, TLS, and DTLS when AES-Counter mode is used...................415
9.2.1.1.3 PDB for TLS and DTLS when AES-GCM is used...........................................416
9.2.1.1.4 PDB for TLS and DTLS when AES-CCM is used...........................................417
9.2.1.1.5 Programming the Options byte with the PDB for SSL, TLS and DTLS..........417
9.2.1.2 Overriding the PDB for SSL, TLS, and DTLS Encapsulation.............................................. 419
9.2.1.3 Computing the pre-encrypted record length during decapsulation........................................420
9.2.1.4 SSL, TLS, DTLS Decapsulation Output frame options.........................................................422
9.2.1.5 SSL / TLS / DTLS error codes...............................................................................................423
9.2.2 Process for SSL 3.0 and TLS 1.0 record encapsulation.............................................................................424
9.2.2.1 Differences between SSL 3.0 and TLS 1.0 (record encapsulation)....................................... 425
9.2.2.2 Processing SSL 3.0 and TLS 1.0 record encapsulation with block ciphers...........................425
9.2.3 Process for SSL 3.0 and TLS 1.0 record decapsulation.............................................................................427
9.2.3.1 SSL 3.0 and TLS 1.0 Record Decapsulation for block ciphers............................................. 427
9.2.3.2 Differences between SSL 3.0 and TLS 1.0 (record decapsulation)....................................... 428
9.2.4 Process for TLS 1.1 and TLS 1.2 record encapsulation.............................................................................429
9.2.4.1 Differences between TLS 1.0, TLS 1.1, and TLS 1.2 Record Encapsulation....................... 429
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NXP Semiconductors 11
Section number Title Page
9.2.4.2 Support for IV generation in TLS 1.1 and TLS 1.2 record encapsulation.............................430
9.2.4.3 Processing TLS 1.1 and TLS 1.2 record encapsulation with block ciphers (AES or DES).. 432
9.2.4.4 Processing TLS 1.1 and TLS 1.2 record encapsulation with stream ciphers.........................433
9.2.4.5 Processing TLS 1.1 and TLS 1.2 record encapsulation with AEAD ciphers........................ 434
9.2.5 Process for TLS 1.1 and TLS 1.2 record decapsulation.............................................................................435
9.2.5.1 Decapsulation of TLS 1.1 and TLS 1.2 records when a stream cipher is used......................436
9.2.5.2 Decapsulation of TLS 1.1 and TLS 1.2 records when a block cipher is used....................... 438
9.2.5.3 Decapsulation of TLS 1.2 records when an AEAD is used................................................... 439
9.2.6 Process for DTLS record encapsulation.....................................................................................................440
9.2.6.1 Differences between DTLS and TLS.....................................................................................441
9.2.6.2 Process of DTLS Record Encapsulation when using a Block Cipher................................... 441
9.2.6.3 Process of DTLS Record Encapsulation when using a Stream Cipher..................................443
9.2.6.4 DTLS 1.2 Record Encapsulation when using an AEAD Cipher........................................... 444
9.2.7 Process for DTLS record decapsulation.....................................................................................................445
9.2.7.1 Differences between DTLS and TLS.....................................................................................446
9.2.7.2 Process of DTLS Record Decapsulation when using a Block Cipher................................... 446
9.2.7.3 Process of DTLS Record Decapsulation when using a Stream Cipher................................. 448
9.2.7.4 DTLS 1.2 Record Decapsulation when using an AEAD Cipher........................................... 449
9.3 SRTP packet encapsulation and decapsulation...........................................................................................................451
9.3.1 Building the initial counter value (Counter IV)......................................................................................... 452
9.3.2 Building the AEAD Nonce........................................................................................................................ 452
9.3.3 Constructing the AESA context from the SRTP AEAD Nonce for AES-CCM mode..............................453
9.3.4 SRTP encapsulation................................................................................................................................... 454
12 NXP Semiconductors
9.4.1 Process for 802.1AE MACsec encapsulation............................................................................................ 462
9.4.3.2 Additional notes for GMAC support (decapsulation)............................................................470
9.4.4 MACsec decapsulation PDB format descriptions......................................................................................470
9.5 IEEE 802.11 -2012 WPA2 MPDU encapsulation and decapsulation........................................................................ 471
9.5.1 Processing Common to WPA2 Encapsulation and Decapsulation............................................................ 472
9.5.1.1 Constructing the AAD for WPA2 encapsulation and decapsulation..................................... 472
9.5.1.2 Constructing the CCMP Nonce for WPA2 encapsulation and decapsulation....................... 473
9.5.1.3 Constructing the AESA context for WPA2 CCMP encapsulation and decapsulation.......... 473
9.5.2 Process for WPA2 encapsulation...............................................................................................................474
9.5.2.2 WPA2 Payload Encapsulation............................................................................................... 476
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NXP Semiconductors 13
9.6.3 WiMax encapsulation error conditions...................................................................................................... 486
9.6.4.1 Transforming the GMH (WiMAX decapsulation).................................................................488
9.6.4.2 Automatic key switching (WiMAX decapsulation)...............................................................489
9.6.5 IEEE 802.16 WiMAX decapsulation PDB format descriptions................................................................ 489
9.6.6 WiMAX decapsulation error conditions.................................................................................................... 490
9.8.1 3G double-CRC encapsulation process......................................................................................................494
9.8.1.1 Calculating the 7-bit CRC of the PDU header for encapsulation.......................................... 494
9.8.1.2 Calculating the 11-bit CRC of the PDU header for encapsulation........................................ 495
9.8.1.3 Calculating the 16-bit payload CRC for encapsulation......................................................... 496
9.8.2 3G double-CRC encapsulation PDB format descriptions..........................................................................496
9.8.3 3G double-CRC decapsulation process......................................................................................................496
9.8.3.1 Calculating the 7-bit CRC of the PDU header for decapsulation.......................................... 497
9.8.3.2 Calculating the 11-bit CRC of the PDU header for decapsulation........................................ 497
9.8.3.3 Calculating the 16-bit payload CRC for decapsulation......................................................... 498
9.8.4 3G double-CRC decapsulation PDB format descriptions..........................................................................498
9.9 3G RLC PDU Encapsulation and Decapsulation overview........................................................................................499
9.9.1 3G RLC PDU encapsulation overview...................................................................................................... 499
9.9.7 Overriding the PDB for 3G RLC PDU encapsulation and decapsulation................................................. 504
9.10 LTE PDCP PDU encapsulation and decapsulation overview.....................................................................................505
9.10.1 LTE PDCP PDU IV generation................................................................................................................. 506
14 NXP Semiconductors
9.10.6 LTE PDCP shared descriptor PDB format descriptions............................................................................ 515
Chapter 10 Key agreement functions
10.1 IKEv2 PRF overview..................................................................................................................................................517
10.1.1 Using IKE PRF to generate SKEYSEED.................................................................................................. 518
10.1.2 Using IKE PRF+ to generate keying material for the IKEv2 SA.............................................................. 518
10.1.3 Using IKE PRF+ to generate Child SA key material.................................................................................519
10.1.4 Restrictions on programming control blocks............................................................................................. 519
10.1.5 IKE PRF PDB format descriptions............................................................................................................ 520
10.2.3 SSL 3.0 PRF PDB format descriptions......................................................................................................527
10.2.4 TLS 1.0/TLS 1.1/DTLS PRF overview..................................................................................................... 530
10.2.5.1 How TLS uses PRF material..................................................................................................533
10.2.5.2 Concatenating input material into one input string (TLS 1.0/1.1/DTLS)..............................534
10.2.6 TLS 1.0, TLS 1.1, DTLS PRF PDB format descriptions...........................................................................535
10.2.7 TLS 1.2 PRF overview...............................................................................................................................538
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NXP Semiconductors 15
10.2.8.2 How TLS uses PRF material (TLS 1.2).................................................................................540
10.2.9 TLS 1.2 PRF PDB format descriptions......................................................................................................541
10.3 Implementation of the derived key protocol...............................................................................................................543
10.3.1 Using DKP with HMAC keys....................................................................................................................544
10.3.2 Implementation of the Blob Protocol.........................................................................................................545
Chapter 11 Cryptographic hardware accelerators (CHAs)
11.1 Public-key hardware accelerator (PKHA) functionality.............................................................................................548
11.1.1 Modular math.............................................................................................................................................549
11.1.4 Elliptic-Curve Math................................................................................................................................... 551
11.1.4.1 ECC_MOD: Point math on a standard curve over a prime field (Fp)................................... 552
11.1.4.2 ECC_F2M: Point math on a standard curve over a binary field (F2m).................................553
11.1.5 PKHA Mode Register................................................................................................................................ 553
11.1.6 PKHA functions.........................................................................................................................................554
11.1.6.2 Clear Memory (CLEAR_MEMORY) function..................................................................... 556
11.1.6.3.4 Integer Modular Multiplication (MOD_MUL).................................................559
11.1.6.3.6 Integer Modular Multiplication with Montgomery Inputs and Outputs
(MOD_MUL_IM_OM) Function..................................................................... 560
11.1.6.3.8 Integer Modular Exponentiation, Montgomery Input (MOD_EXP_IM and
MOD_EXP_IM_TEQ) Function...................................................................... 562
16 NXP Semiconductors
11.1.6.3.10 Integer Modular Square (MOD_SQR and MOD_SQR_TEQ).........................563
11.1.6.3.11 Integer Modular Square, Montgomery inputs (MOD_SQR_IM and
MOD_SQR_IM_TEQ)..................................................................................... 564
(MOD_SQR_IM_OM and MOD_SQR_IM_OM_TEQ)................................. 564
11.1.6.3.14 Integer Modular Cube, Montgomery input (MOD_CUBE_IM and
MOD_CUBE_IM_TEQ)...................................................................................566
(MOD_CUBE_IM_OM and MOD_CUBE_IM_OM_TEQ)............................566
11.1.6.3.20 Miller_Rabin Primality Test (PRIME_TEST)..................................................569
11.1.6.3.23 Evaluate A (EVALUATE) function................................................................. 571
11.1.6.3.26 Binary Polynomial (F2m) Modular Multiplication with Montgomery Inputs
(F2M_MUL_IM) Function............................................................................... 573
and Outputs (F2M_MUL_IM_OM) Function.................................................. 573
F2M_EXP_TEQ).............................................................................................. 574
(F2M_SML_EXP)............................................................................................ 575
F2M_SQR_TEQ)..............................................................................................576
NXP Semiconductors 17
(F2M_SQR_IM and F2M_SQR_IM_TEQ)..................................................... 576
11.1.6.3.32 Binary Polynomial (F2m) Modular Square, Montgomery Input and Output
(F2M_SQR_IM_OM and F2M_SQR_IM_OM_TEQ).....................................577
F2M_CUBE_TEQ)...........................................................................................578
(F2M_CUBE_IM and F2M_CUBE_IM_TEQ)................................................579
11.1.6.3.35 Binary Polynomial (F2m) Modular Cube, Montgomery Input and Output
(F2M_CUBE_IM_OM and F2M_CUBE_IM_OM_TEQ)...............................579
11.1.6.3.38 Binary Polynomial (F2m) R2 Mod N (F2M_R2) Function..............................581
11.1.6.3.39 Binary Polynomial (F2m) Greatest Common Divisor (F2M_GCD) Function.582
11.1.6.4 Elliptic Curve Functions........................................................................................................ 582
11.1.6.4.1 ECC Fp Point Add, Affine Coordinates (ECC_MOD_ADD) Function...........582
11.1.6.4.2 ECC Fp Point Add, Affine Coordinates, R2 Mod N Input
(ECC_MOD_ADD_R2) Function.................................................................... 583
11.1.6.4.4 ECC Fp Point Multiply, Affine Coordinates (ECC_MOD_MUL and
ECC_MOD_MUL_TEQ) Function.................................................................. 584
11.1.6.4.5 ECC Fp Point Multiply, R2 Mod N Input, Affine Coordinates
(ECC_MOD_MUL_R2 and ECC_MOD_MUL_R2_TEQ) Function..............586
11.1.6.4.6 ECC Fp Check Point (ECC_MOD_CHECK_POINT) Function..................... 587
11.1.6.4.7 ECC Fp Check Point, R2 Mod N Input, Affine Coordinates
(ECC_MOD_CHECK_POINT_R2) Function..................................................588
11.1.6.4.8 ECC F2m Point Add, Affine Coordinates (ECC_F2M_ADD) Function......... 589
11.1.6.4.9 ECC F2m Point Add, Affine Coordinates, R2 Mod N Input
(ECC_F2M_ADD_R2) Function......................................................................589
11.1.6.4.11 ECC F2m Point Multiply, Affine Coordinates (ECC_F2M_MUL and
ECC_F2M_MUL_TEQ) Function....................................................................591
18 NXP Semiconductors
Section number Title Page
11.1.6.4.12 ECC F2m Point Multiply, R2 Mod N Input, Affine Coordinates
(ECC_F2M_MUL_R2 and ECC_F2M_MUL_R2_TEQ) Function.................592
11.1.6.4.14 ECC F2m Check Point, R2 (ECC_F2M_CHECK_POINT_R2) Function.......594
11.1.6.4.15 ECM Modular Multiplication (ECM_MOD_MUL_X and
ECM_MOD_MUL_X_TEQ) Function............................................................ 595
11.1.6.4.16 ECM Fp Point Multiply, R2 Mod N Input, Affine Coordinates
(ECM_MOD_MUL_X_R2 and ECM_MOD_MUL_X_R2_TEQ) Function.. 596
11.1.6.4.17 ECT Modular Multiplication (ECT_MOD_MUL and
ECT_MOD_MUL_TEQ) Function.................................................................. 597
11.1.6.4.18 ECT Fp Point Multiply, R2 Mod N Input, Affine Coordinates
(ECT_MOD_MUL_R2 and ECT_MOD_MUL_R2_TEQ) Function.............. 599
11.1.6.4.19 ECT Fp Point Add, Affine Coordinates (ECT_MOD_ADD) Function........... 600
11.1.6.4.20 ECT Fp Point Add, Affine Coordinates, R2 Mod N Input
(ECT_MOD_ADD_R2) Function.................................................................... 600
11.1.6.4.22 ECT Fp Check Point, R2 (ECT_MOD_CHECK_POINT_R2) Function.........602
11.1.6.4.23 Copy memory, N-Size and Source-Size (COPY_NSZ and COPY_SSZ)........ 603
11.1.6.4.24 Right Shift A (R_SHIFT) function................................................................... 604
11.1.6.4.25 Compare A B (COMPARE) function...............................................................604
11.1.6.4.26 Evaluate A (EVALUATE) function................................................................. 605
11.2 Kasumi f8 and f9 hardware accelerator(KFHA) functionality................................................................................... 625
11.2.2 KFHA use of the Context Register............................................................................................................ 626
11.2.3 KFHA use of the Key Register.................................................................................................................. 627
NXP Semiconductors 19
11.3.3 DESA use of the Key Size Register...........................................................................................................629
11.3.4 DESA use of the Data Size Register..........................................................................................................629
11.3.5 DESA Context Register............................................................................................................................. 630
11.4 Cyclic-redundancy check accelerator (CRCA) functionality..................................................................................... 630
11.4.3 CRCA Key Register...................................................................................................................................633
11.5 Random-number generator (RNG) functionality........................................................................................................634
11.5.2.1 RNG state handles..................................................................................................................635
11.5.6 RNG use of the Data Size Register............................................................................................................639
11.6 SNOW 3G f8 accelerator functionality.......................................................................................................................639
11.6.1 Differences between SNOW 3G f8 and SNOW 3G f9..............................................................................639
11.6.2 SNOW 3G f8 use of the Mode Register.................................................................................................... 640
11.6.3 SNOW 3G f8 use of the Context Register................................................................................................. 641
11.6.4 SNOW 3G f8 use of the Data Size Register.............................................................................................. 641
11.6.5 SNOW 3G f8 use of the Key Register....................................................................................................... 642
11.6.6 SNOW 3G f8 use of the Key Size Register............................................................................................... 642
LS2088A Security (SEC) Reference Manual, Rev. 0, 04/2018
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11.7.1 SNOW 3G f9 use of the Mode Register.................................................................................................... 643
11.7.2 SNOW 3G f9 use of the Context Register................................................................................................. 644
11.7.3 SNOW 3G f9 use of the Data Size Register.............................................................................................. 645
11.7.4 SNOW 3G f9 use of the Key Register....................................................................................................... 645
11.7.5 SNOW 3G f9 use of the Key Size Register............................................................................................... 646
11.7.6 SNOW 3G f9 use of ICV check.................................................................................................................646
11.8 Message digest hardware accelerator (MDHA) functionality.................................................................................... 646
11.8.1 MDHA use of the Mode Register.............................................................................................................. 647
11.8.2.1 Using the MDHA Key Register with normal keys................................................................ 648
11.8.2.2 Using the MDHA Key Register with IPAD/OPAD "split keys"........................................... 648
11.8.2.2.1 Definition and function of IPAD/OPAD split keys.......................................... 649
11.8.2.2.2 Process flow of using the Key Register with split keys....................................649
11.8.2.2.3 Using padding with the split key type to align with storage.............................649
11.8.2.2.4 Length of a split key......................................................................................... 649
11.8.2.2.6 Loading/storing a split key with a FIFO STORE command.............................650
11.8.2.2.7 Sizes of split keys..............................................................................................650
11.8.2.3 MDHA use of the Key Size Register..................................................................................... 651
11.8.3 MDHA use of the Data Size Register........................................................................................................ 651
11.8.5 Save and restore operations in MDHA context data..................................................................................652
11.9 AES accelerator (AESA) functionality.......................................................................................................................652
11.9.2 AESA as both Class 1 and Class 2 CHA................................................................................................... 653
11.9.3 AESA modes of operation......................................................................................................................... 654
11.9.4 AESA use of registers................................................................................................................................ 655
NXP Semiconductors 21
11.9.6.2 AES ECB mode use of the Context Register.........................................................................657
11.9.6.3 AES ECB Mode use of the Data Size Register .....................................................................657
11.9.6.4 AES ECB Mode use of the Key Register.............................................................................. 657
11.9.6.5 AES ECB Mode use of the Key Size Register.......................................................................657
11.9.7 AES CBC, OFB, CFB128 modes.............................................................................................................. 658
11.9.7.1 AES CBC, OFB, and CFB128 modes use of the Mode Register.......................................... 658
11.9.7.2 AES CBC, OFB, and CFB128 modes use of the Context Register....................................... 659
11.9.7.3 AES CBC, OFB, and CFB128 modes use of the Data Size Register.................................... 659
11.9.7.4 AES CBC, OFB, and CFB128 modes use of the Key Register............................................. 660
11.9.7.5 AES CBC, OFB, and CFB128 modes use of the Key Size Register..................................... 660
11.9.8 AES CTR mode......................................................................................................................................... 660
11.9.8.2 AES CTR mode use of the Context Register.........................................................................661
11.9.8.3 AES CTR mode use of the Data Size Register...................................................................... 661
11.9.8.4 AES CTR mode use of the Key Register...............................................................................661
11.9.8.5 AES CTR mode use of the Key Size Register....................................................................... 662
11.9.9 AES XTS mode..........................................................................................................................................662
11.9.9.3 AES XTS mode use of the Data Size Register...................................................................... 663
11.9.9.4 AES XTS mode use of the Key Register............................................................................... 663
11.9.9.5 AES XTS mode use of the Key Size Register....................................................................... 664
11.9.10 AES XCBC-MAC and CMAC modes.......................................................................................................664
11.9.10.1 AES XCBC-MAC and CMAC modes use of the Mode Register..........................................664
11.9.10.2 AES XCBC-MAC and CMAC Modes use of the Context Register......................................666
11.9.10.3 AES XCBC-MAC and CMAC modes use of the Class 1 ICV Size Register....................... 666
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Section number Title Page
11.9.10.4 AES XCBC-MAC and CMAC modes use of the Data Size Register................................... 667
11.9.10.5 AES XCBC-MAC and CMAC modes use of the Key Register............................................ 667
11.9.10.6 AES XCBC-MAC and CMAC modes use of the Key Size Register.................................... 667
11.9.10.7 ICV checking in AES XCBC-MAC and CMAC modes....................................................... 667
11.9.11 AESA CCM mode..................................................................................................................................... 668
11.9.11.1 Generation encryption............................................................................................................668
11.9.11.4 AES CCM mode use of the Context Register........................................................................670
11.9.11.5 AES CCM mode use of the Data Size Register..................................................................... 671
11.9.11.6 AES CCM mode use of the Key Register..............................................................................671
11.9.11.7 AES CCM mode use of the Key Size Register......................................................................671
11.9.11.8 AES CCM mode use of the ICV check..................................................................................672
11.9.12 AES GCM mode........................................................................................................................................ 672
11.9.12.7 AES GCM Mode use of the Data Size Register.................................................................... 675
11.9.12.8 AES GCM mode use of the Class 1 IV Size Register........................................................... 676
11.9.12.9 AES GCM mode use of the AAD Size Register....................................................................676
11.9.12.10 AES GCM mode use of the Class 1 ICV Size Register.........................................................676
11.9.12.11 AES GCM mode use of the Key Register..............................................................................676
11.9.12.12 AES GCM mode use of the Key Size Register......................................................................676
11.9.12.13 AES GCM mode use of the ICV check................................................................................. 677
11.9.13 AESA optimization modes.........................................................................................................................677
LS2088A Security (SEC) Reference Manual, Rev. 0, 04/2018
NXP Semiconductors 23
11.9.13.4 Authentication-only data........................................................................................................678
11.9.13.7 AES optimization modes use of the Data Size Register........................................................ 683
11.9.13.8 AES optimization modes use of the AAD Size Register....................................................... 684
11.9.13.9 AES optimization modes use of the Class 1 ICV Size Register............................................ 684
11.9.13.10 AES optimization modes use of the Class 1 Key Register.................................................... 685
11.9.13.11 AES optimization modes use of the Class 2 Key Register.................................................... 685
11.9.13.12 AES optimization modes use of the Class 1 Key Size Register............................................ 685
11.9.13.13 AES optimization modes use of the Class 2 Key Size Register............................................ 686
11.9.13.14 AES optimization modes use of the ICV check.....................................................................686
11.9.13.15 AES optimization modes error conditions............................................................................. 686
11.10 ZUC encryption accelerator (ZUCE) functionality.................................................................................................... 688
11.10.2 ZUCE use of the Mode Register................................................................................................................ 689
11.10.4 ZUCE use of the Data Size Register..........................................................................................................690
11.10.5 ZUCE use of the Key Register...................................................................................................................690
11.10.6 ZUCE use of the Key Size Register ..........................................................................................................691
11.11 ZUC authentication accelerator (ZUCA) functionality.............................................................................................. 691
11.11.2 ZUCA use of the Context Register............................................................................................................ 692
Chapter 12
24 NXP Semiconductors
12.1.4 RTIC use of command, configuration, and status registers....................................................................... 698
12.1.5 Initializing RTIC........................................................................................................................................ 699
12.2 SEC virtualization and security domain identifiers (SDIDs)......................................................................................700
12.2.1 Virtualization............................................................................................................................................. 700
12.3.2 Black keys and JDKEK/TDKEK...............................................................................................................702
12.3.3 Trusted descriptors and TDSK...................................................................................................................702
12.4.3 Loading red keys........................................................................................................................................704
12.4.6 Encapsulating and decapsulating black keys............................................................................................. 705
12.5 Trusted descriptors......................................................................................................................................................708
NXP Semiconductors 25
12.5.5 Configuring the system to create trusted descriptors properly.................................................................. 710
12.5.6 Creating trusted descriptors....................................................................................................................... 710
12.5.6.2 Trusted-descriptor execution considerations......................................................................... 711
12.6.5.2.3 Enforcing blob content type..............................................................................718
12.6.6 Blob encapsulation.....................................................................................................................................719
12.6.7 Blob decapsulation.....................................................................................................................................720
12.7 Critical security parameters........................................................................................................................................ 721
12.8 Manufacturing-protection chip-authentication process.............................................................................................. 722
12.8.1.1 Providing data to the MPPrivK-generation function............................................................. 724
12.8.1.2 Providing data to the MPPubK-generation function..............................................................724
12.8.1.3 Providing data to the MPSign function..................................................................................724
12.8.1.4 Role of the ROM-resident secure boot firmware...................................................................724
12.8.2 MPPrivK-generation function....................................................................................................................725
26 NXP Semiconductors
Section number Title Page
12.8.2.1 Differences between the MPPrivK-generation function and the DL KEY PAIR GEN
function.................................................................................................................................. 725
12.8.2.3 Protocol data block (PDB) for the MPPrivK-generation function.........................................726
12.8.3 MPPubK-generation function.................................................................................................................... 727
12.8.3.1 Differences between the MPPubK-generation function and the DL KEY PAIR GEN
function.................................................................................................................................. 727
12.8.3.3 Protocol data block (PDB) for the MPPubK-generation function......................................... 728
12.8.3.4 Running the MPPubK generation function at the OEM's facility..........................................729
12.8.4 MPSign function........................................................................................................................................ 730
12.8.4.2 Protocol data block (PDB) MPSign function.........................................................................731
Chapter 13 SEC service error detection, recovery (reset), and reconfiguration
13.1 Software SEC Reset....................................................................................................................................................733
13.2.1 Job ring user services................................................................................................................................. 734
13.2.2.3 Ring user (re-)assignment procedure..................................................................................... 738
13.3.1 QI user services..........................................................................................................................................739
NXP Semiconductors 27
13.3.2.4 Single QI user SEC access termination procedure.................................................................742
13.3.2.5 Single QI user access (re-)enable procedure..........................................................................742
13.3.2.6 Global QI user access controls...............................................................................................742
13.3.2.7 Queue and ICID flush procedures and options...................................................................... 743
13.4.1 Single AI task services...............................................................................................................................744
13.6.1 Global and DECO user services.................................................................................................................748
13.6.2 Global SEC and DECO management services.......................................................................................... 748
28 NXP Semiconductors
14.4 Job Ring a ICID Register - most significant half (JR0ICID_MS - JR3ICID_MS).................................................... 831
14.4.1 Offset..........................................................................................................................................................831
14.4.2 Function..................................................................................................................................................... 831
14.4.3 Diagram......................................................................................................................................................832
14.4.4 Fields..........................................................................................................................................................832
14.5 Job Ring a ICID Register - least significant half (JR0ICID_LS - JR3ICID_LS).......................................................833
14.5.1 Offset..........................................................................................................................................................833
14.5.2 Function..................................................................................................................................................... 833
14.5.3 Diagram......................................................................................................................................................834
14.5.4 Fields..........................................................................................................................................................834
14.6.1 Offset..........................................................................................................................................................835
14.6.2 Function..................................................................................................................................................... 835
14.6.3 Diagram......................................................................................................................................................835
14.6.4 Fields..........................................................................................................................................................836
NXP Semiconductors 29
14.8.1 Offset..........................................................................................................................................................838
14.8.2 Function..................................................................................................................................................... 838
14.8.3 Diagram......................................................................................................................................................838
14.8.4 Fields..........................................................................................................................................................838
14.9 RTIC ICID Register for Block a - most significant half (RTICAICID_MS - RTICDICID_MS)..............................840
14.9.1 Offset..........................................................................................................................................................840
14.9.2 Function..................................................................................................................................................... 840
14.9.3 Diagram......................................................................................................................................................840
14.9.4 Fields..........................................................................................................................................................840
14.10 RTIC ICID Register for Block a - least significant half (RTICAICID_LS - RTICDICID_LS)................................ 841
14.10.1 Offset..........................................................................................................................................................841
14.10.2 Function..................................................................................................................................................... 841
14.10.3 Diagram......................................................................................................................................................841
14.10.4 Fields..........................................................................................................................................................842
30 NXP Semiconductors
14.14.1 Offset..........................................................................................................................................................847
14.14.2 Function..................................................................................................................................................... 847
14.14.3 Diagram......................................................................................................................................................848
14.14.4 Fields..........................................................................................................................................................848
14.15.1 Offset..........................................................................................................................................................848
14.15.2 Function..................................................................................................................................................... 848
14.15.3 Diagram......................................................................................................................................................849
14.15.4 Fields..........................................................................................................................................................849
NXP Semiconductors 31
32 NXP Semiconductors
14.25.1 Offset..........................................................................................................................................................864
14.25.2 Function..................................................................................................................................................... 865
14.25.3 Diagram......................................................................................................................................................865
14.25.4 Fields..........................................................................................................................................................865
14.26.1 Offset..........................................................................................................................................................866
14.26.2 Function..................................................................................................................................................... 867
14.26.3 Diagram......................................................................................................................................................867
14.26.4 Fields..........................................................................................................................................................868
14.27.1 Offset..........................................................................................................................................................869
14.27.2 Function..................................................................................................................................................... 869
14.27.3 Diagram......................................................................................................................................................870
14.27.4 Fields..........................................................................................................................................................870
14.28.1 Offset..........................................................................................................................................................870
14.28.2 Function..................................................................................................................................................... 871
14.28.3 Diagram......................................................................................................................................................871
14.28.4 Fields..........................................................................................................................................................872
14.29.1 Offset..........................................................................................................................................................873
14.29.2 Function..................................................................................................................................................... 873
14.29.3 Diagram......................................................................................................................................................874
14.29.4 Fields..........................................................................................................................................................874
14.30.1 Offset..........................................................................................................................................................874
14.30.2 Function..................................................................................................................................................... 875
NXP Semiconductors 33
14.33.1 Offset..........................................................................................................................................................877
14.33.2 Function..................................................................................................................................................... 878
14.33.3 Diagram......................................................................................................................................................878
14.33.4 Fields..........................................................................................................................................................879
14.34.1 Offset..........................................................................................................................................................879
14.34.2 Function..................................................................................................................................................... 879
14.34.3 Diagram......................................................................................................................................................880
14.34.4 Fields..........................................................................................................................................................880
14.35.1 Offset..........................................................................................................................................................881
14.35.2 Function..................................................................................................................................................... 881
14.35.3 Diagram......................................................................................................................................................881
14.35.4 Fields..........................................................................................................................................................881
14.36.1 Offset..........................................................................................................................................................882
34 NXP Semiconductors
14.42.1 Offset..........................................................................................................................................................890
NXP Semiconductors 35
14.43.1 Offset..........................................................................................................................................................892
14.43.2 Function..................................................................................................................................................... 893
14.43.3 Diagram......................................................................................................................................................893
14.43.4 Fields..........................................................................................................................................................894
14.44.1 Offset..........................................................................................................................................................895
14.44.2 Function..................................................................................................................................................... 895
14.44.3 Diagram......................................................................................................................................................896
14.44.4 Fields..........................................................................................................................................................896
14.45.1 Offset..........................................................................................................................................................896
14.45.2 Function..................................................................................................................................................... 897
14.45.3 Diagram......................................................................................................................................................897
14.45.4 Fields..........................................................................................................................................................898
14.46.1 Offset..........................................................................................................................................................898
14.46.2 Function..................................................................................................................................................... 898
14.46.3 Diagram......................................................................................................................................................899
14.46.4 Fields..........................................................................................................................................................899
14.47.1 Offset..........................................................................................................................................................899
14.47.2 Function..................................................................................................................................................... 900
14.47.3 Diagram......................................................................................................................................................900
14.47.4 Fields..........................................................................................................................................................901
LS2088A Security (SEC) Reference Manual, Rev. 0, 04/2018
36 NXP Semiconductors
14.49.1 Offset..........................................................................................................................................................903
14.49.2 Function..................................................................................................................................................... 904
14.49.3 Diagram......................................................................................................................................................904
14.49.4 Fields..........................................................................................................................................................905
14.50.1 Offset..........................................................................................................................................................905
14.50.2 Function..................................................................................................................................................... 905
14.50.3 Diagram......................................................................................................................................................906
14.50.4 Fields..........................................................................................................................................................906
14.51.1 Offset..........................................................................................................................................................906
14.51.2 Function..................................................................................................................................................... 906
14.51.3 Diagram......................................................................................................................................................907
14.51.4 Fields..........................................................................................................................................................907
NXP Semiconductors 37
14.55.1 Offset..........................................................................................................................................................912
14.55.2 Function..................................................................................................................................................... 912
14.55.3 Diagram......................................................................................................................................................913
14.55.4 Fields..........................................................................................................................................................913
14.58.1 Offset..........................................................................................................................................................916
14.58.2 Function..................................................................................................................................................... 916
14.58.3 Diagram......................................................................................................................................................916
14.58.4 Fields..........................................................................................................................................................916
14.59.1 Offset..........................................................................................................................................................917
14.59.2 Function..................................................................................................................................................... 917
14.59.3 Diagram......................................................................................................................................................917
38 NXP Semiconductors
14.60.1 Offset..........................................................................................................................................................918
14.60.2 Function..................................................................................................................................................... 918
14.60.3 Diagram......................................................................................................................................................919
14.60.4 Fields..........................................................................................................................................................919
14.61.1 Offset..........................................................................................................................................................919
14.61.2 Function..................................................................................................................................................... 920
14.61.3 Diagram......................................................................................................................................................920
14.61.4 Fields..........................................................................................................................................................920
14.62.1 Offset..........................................................................................................................................................921
14.62.2 Function..................................................................................................................................................... 921
14.62.3 Diagram......................................................................................................................................................921
14.62.4 Fields..........................................................................................................................................................921
14.63.1 Offset..........................................................................................................................................................922
14.63.2 Function..................................................................................................................................................... 922
14.63.3 Diagram......................................................................................................................................................922
14.63.4 Fields..........................................................................................................................................................923
14.64 RNG TRNG Statistical Check Run Length 1 Count Register (RTSCR1C)............................................................... 923
14.64.1 Offset..........................................................................................................................................................923
14.64.2 Function..................................................................................................................................................... 923
14.64.3 Diagram......................................................................................................................................................924
14.64.4 Fields..........................................................................................................................................................924
14.65 RNG TRNG Statistical Check Run Length 1 Limit Register (RTSCR1L)................................................................ 925
14.65.1 Offset..........................................................................................................................................................925
14.65.2 Function..................................................................................................................................................... 925
NXP Semiconductors 39
14.66 RNG TRNG Statistical Check Run Length 2 Count Register (RTSCR2C)............................................................... 926
14.66.1 Offset..........................................................................................................................................................926
14.66.2 Function..................................................................................................................................................... 927
14.66.3 Diagram......................................................................................................................................................927
14.66.4 Fields..........................................................................................................................................................927
14.67 RNG TRNG Statistical Check Run Length 2 Limit Register (RTSCR2L)................................................................ 928
14.67.1 Offset..........................................................................................................................................................928
14.67.2 Function..................................................................................................................................................... 928
14.67.3 Diagram......................................................................................................................................................928
14.67.4 Fields..........................................................................................................................................................929
14.68 RNG TRNG Statistical Check Run Length 3 Count Register (RTSCR3C)............................................................... 929
14.68.1 Offset..........................................................................................................................................................929
14.68.2 Function..................................................................................................................................................... 930
14.68.3 Diagram......................................................................................................................................................930
14.68.4 Fields..........................................................................................................................................................930
14.69 RNG TRNG Statistical Check Run Length 3 Limit Register (RTSCR3L)................................................................ 931
14.69.1 Offset..........................................................................................................................................................931
14.69.2 Function..................................................................................................................................................... 931
14.69.3 Diagram......................................................................................................................................................931
14.69.4 Fields..........................................................................................................................................................932
14.70 RNG TRNG Statistical Check Run Length 4 Count Register (RTSCR4C)............................................................... 932
14.70.1 Offset..........................................................................................................................................................932
14.70.2 Function..................................................................................................................................................... 932
14.70.3 Diagram......................................................................................................................................................933
14.70.4 Fields..........................................................................................................................................................933
14.71 RNG TRNG Statistical Check Run Length 4 Limit Register (RTSCR4L)................................................................ 933
14.71.1 Offset..........................................................................................................................................................934
40 NXP Semiconductors
14.72 RNG TRNG Statistical Check Run Length 5 Count Register (RTSCR5C)............................................................... 935
14.72.1 Offset..........................................................................................................................................................935
14.72.2 Function..................................................................................................................................................... 935
14.72.3 Diagram......................................................................................................................................................935
14.72.4 Fields..........................................................................................................................................................936
14.73 RNG TRNG Statistical Check Run Length 5 Limit Register (RTSCR5L)................................................................ 936
14.73.1 Offset..........................................................................................................................................................936
14.73.2 Function..................................................................................................................................................... 936
14.73.3 Diagram......................................................................................................................................................937
14.73.4 Fields..........................................................................................................................................................937
14.74 RNG TRNG Statistical Check Run Length 6+ Count Register (RTSCR6PC)...........................................................938
14.74.1 Offset..........................................................................................................................................................938
14.74.2 Function..................................................................................................................................................... 938
14.74.3 Diagram......................................................................................................................................................938
14.74.4 Fields..........................................................................................................................................................938
14.75 RNG TRNG Statistical Check Run Length 6+ Limit Register (RTSCR6PL)............................................................939
14.75.1 Offset..........................................................................................................................................................939
14.75.2 Function..................................................................................................................................................... 939
14.75.3 Diagram......................................................................................................................................................939
14.75.4 Fields..........................................................................................................................................................940
NXP Semiconductors 41
14.77.1 Offset..........................................................................................................................................................943
14.77.2 Function..................................................................................................................................................... 943
14.77.3 Diagram......................................................................................................................................................943
14.77.4 Fields..........................................................................................................................................................944
14.78 RNG TRNG Statistical Check Poker Count 1 and 0 Register (RTPKRCNT10)....................................................... 944
14.78.1 Offset..........................................................................................................................................................944
14.78.2 Function..................................................................................................................................................... 944
14.78.3 Diagram......................................................................................................................................................944
14.78.4 Fields..........................................................................................................................................................945
14.79 RNG TRNG Statistical Check Poker Count 3 and 2 Register (RTPKRCNT32)....................................................... 945
14.79.1 Offset..........................................................................................................................................................945
14.79.2 Function..................................................................................................................................................... 945
14.79.3 Diagram......................................................................................................................................................946
14.79.4 Fields..........................................................................................................................................................946
14.80 RNG TRNG Statistical Check Poker Count 5 and 4 Register (RTPKRCNT54)....................................................... 946
14.80.1 Offset..........................................................................................................................................................946
14.80.2 Function..................................................................................................................................................... 947
14.80.3 Diagram......................................................................................................................................................947
14.80.4 Fields..........................................................................................................................................................947
14.81 RNG TRNG Statistical Check Poker Count 7 and 6 Register (RTPKRCNT76)....................................................... 947
14.81.1 Offset..........................................................................................................................................................948
14.81.2 Function..................................................................................................................................................... 948
14.81.3 Diagram......................................................................................................................................................948
14.81.4 Fields..........................................................................................................................................................948
14.82 RNG TRNG Statistical Check Poker Count 9 and 8 Register (RTPKRCNT98)....................................................... 949
14.82.1 Offset..........................................................................................................................................................949
14.82.2 Function..................................................................................................................................................... 949
14.82.3 Diagram......................................................................................................................................................949
14