LTC1705

1

DESCRIPTIO

U

FEATURES

APPLICATIO SU

TYPICAL APPLICATIO

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The LTC®1705 is a complete power supply controller forIntel Mobile Pentium processors. It includes two switch-ing regulator controllers, each designed to drive a pair ofN-channel MOSFETs in a voltage mode feedback, syn-chronous buck configuration, to provide the core and I/Osupplies. The core controller includes a 5-bit DAC thatconforms to the Intel Mobile VID specification. The IC alsoincludes a low dropout linear regulator (LDO) that deliversup to 150mA of output current to provide the CLK supply.The LTC1705 uses a constant-frequency 550kHz PWMarchitecture, minimizing external component size andcost, as well as optimizing load transient performance. Itprovides better than 1.25% DC accuracy at its core output,and 2% at I/0 and CLK outputs. The high performancefeedback loops allow the circuit to keep total outputregulation within ±5% under all transient conditions. Anopen-drain PGOOD flag indicates that all three outputs arewithin ±10% of their regulated values. A shutdown circuitdisables all three outputs if the RUN/SS pin is pulled toground. In this mode, the LTC1705 supply current dropsto below 100µA.

Complete Power Supply Controller for IntelMobile Pentium® Processors

Intel Mobile Pentium Core, I/O, Clock Supplies Multiple Logic Supply Generator , LTC and LT are registered trademarks of Linear Technology Corporation.

Three Regulated Outputs: Core, I/O and CLK in OnePackage

Integrated Intel Mobile 5-Bit VID DAC No External Current Sense Resistors All N-Channel External MOSFET Architecture 550kHz Switching Frequency Minimizes External

Component Size and Cost Integrated 150mA LDO Linear Regulator Excellent DC Accuracy: 1.25% for Core, 2% for I/O

and CLK Supplies PGOOD Flag Monitors All Three Outputs High Efficiency Over Wide Load Current Range Low Shutdown Current: < 100µA Switchers Run Out-of-Phase to Minimize CIN Small 28-Pin Narrow SSOP Package

Dual 550kHz SynchronousSwitching Regulator Controller with

5-Bit VID and 150mA LDO

Pentium is a registered trademark of Intel Corporation.

Intel Mobile Pentium VRM Supply

SWC

BGC

IMAXC

6

4

8

SENSEC13

RIMAXC, 27k

COUTC180µF4V×6

LC0.68µH

QBCA

QBIO

QBCB

PVCC PGOOD

LTC1705

VID4:05-BIT VID

VCCTGC

5

2 22 19

BOOSTC3

+ COUTIO100µF

10V×2

+

CIN330µF

10V×3

1µF

VIN5V

VOUTC0.9V TO 2V

15A

+

QTCB

QTIO

CCPC1µF

DCPCMBR

0520LT1QTCA

RIMAXI0, 16k

LIO3µH

VOUTIO1.5V3A

VOUTCLK2.5V150mA

FBC11

R311.8k

R21, 11kCOMPC

10

RPGOOD5k

CCPIO1µF

DCPIOMBR0520LT1

10Ω 10µF

C311800pF

1µF

CVOUTCLK10µF10V

CVINCLK10µF10V

1µF

1705 TA01

+

C111800pF

C21330pF

C22100pF

1µF

C122200pF

RB210k1%

RUN/SS9

PGND7

CSS0.1µF

10kSHUTDOWN

CIN: KEMET T510X337K010ASCOUTC: PANASONIC EEFUE0G181RCOUTIO: AVX TPS0107M010R0065LC: SUMIDA CEP125-4712-T007LIO: SUMIDA CDRH6D28-3R0QTCA, QTCB, QBCA, QBCB: FAIRCHILD FDS6670AQTIO, QBIO: 1/2 FAIRCHILD NDS8926

VINCLK3.3V+

GND12

14–18

SWIO

BGIO

IMAXIO

25

28

1

COMPIO21

TGIO26

BOOSTIO27

FBIO20

VINCLK24

VOUTCLK23

R22, 11kR12

8.87k1%

+

LTC1705

2

Supply VoltageVCC, PVCC, VINCLK .................................................. 6VBOOSTC, BOOSTIO ............................................. 12VBOOSTC – SWC, BOOSTIO – SWIO....................... 6V

Input VoltageSWC, SWIO ................................................ –1V to 6VSENSEC, FBC, FBIO, VIDn ....... –0.3V to (VCC + 0.3V)PGOOD, RUN/SS,IMAXC, IMAXIO .................................. –0.3V to (VCC + 0.3V)

Peak Output Current <10µsTGC, BGC .............................................................. 5ATGIO, BGIO ....................................................... 1.25A

Operating Temperature Range (Note 2) .. –40°C to 85°CStorage Temperature Range ................. –65°C to 150°CLead Temperature (Soldering, 10 sec).................. 300°C

ORDER PARTNUMBER

TJMAX = 125°C, θJA = 80°C/W

Consult LTC Marketing for parts specified with wider operating temperature ranges.

LTC1705EGN

ABSOLUTE AXI U RATI GS

W WW U

PACKAGE/ORDER I FOR ATIOU UW

ELECTRICAL CHARACTERISTICSThe denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.VCC = PVCC = BOOST = 5V, VINCLK = 3.3V unless otherwise specified. (Note 3)

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3

4

5

6

7

8

9

10

11

12

13

14

TOP VIEW

GN PACKAGE28-LEAD PLASTIC SSOP

28

27

26

25

24

23

22

21

20

19

18

17

16

15

IMAXIO

PVCC

BOOSTC

BGC

TGC

SWC

PGND

IMAXC

RUN/SS

COMPC

FBC

GND

SENSEC

VID0

BGIO

BOOSTIO

TGIO

SWIO

VINCLK

VOUTCLK

PGOOD

COMPIO

FBIO

VCC

VID4

VID3

VID2

VID1

(Note 1)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VCC VCC Supply Voltage 3.15 5 5.5 V

PVCC PVCC Supply Voltage (Note 4) 3.15 5 5.5 V

BVCC BOOST Pin Voltage VBOOST – VSW (Note 4) 3.15 5 5.5 V

VINCLK VINCLK Supply Voltage 3 3.3 5.5 V

IVCC VCC Supply Current Test Circuit 1 4.5 8 mARUN/SS = 0V 40 100 µA

IPVCC PVCC Supply Current VSENSEC = VFBIO = 0V, No Load at Drivers (Note 5) 2 6 mARUN/SS = 0V (Note 6) 1 50 µA

IBOOST IBOOSTC + IBOOSTIO VSENSEC = VFBIO = 0V, No Load at Drivers (Note 5) 2 6 mARUN/SS = 0V (Note 6) 1 50 µA

IVINCLK VINCLK Supply Current IVOUTCLK = 0mA 1 1.5 mARUN/SS = 0V 4 30 µA

VSHDN RUN/SS Shutdown Threshold VRUN/SS ↑ (Rising Edge) 0.2 0.5 V

ISS RUN/SS Source Current RUN/SS = 0V –3 µA

Core, I/O Supply Control Loops

VSENSEC Output Voltage Accuracy Programmed from 0.9V to 2V –1.25 1.25 %

VFBC Core Feedback Voltage (Note 10) 0.800 V

VFBIO I/O Feedback Voltage 0.784 0.800 0.816 V

dVFB Feedback Voltage Line Regulation VCC = 3.3V to 5.5V ±0.01 ±0.1 %/V

dVOUT Output Voltage Load Regulation (Note 7) –0.2 –0.1 %

IFBIO I/O Feedback Input Current ±1 µA

LTC1705

3

ELECTRICAL CHARACTERISTICSThe denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.VCC = PVCC = BOOST = 5V, VINCLK = 3.3V unless otherwise specified. (Note 3)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

AFB Feedback Amplifier DC Gain 74 85 dB

GBW Feedback Amplifier Gain Bandwidth Product f = 100kHz (Note 7) 20 MHz

ICOMP Feedback Amplifier Output Sink/Source Current ±3 ±10 mA

VPGOOD Negative Power Good Threshold Relative to Nominal Output Voltage –15 –10 –6 %Positive Power Good Threshold 6 10 15 %

AILIM Current Limit Amplifier DC Gain 40 60 dB

IIMAX IMAX Source Current VIMAXC = VIMAXIO = 0V –12 –10 –8 µA

Core, I/O Supply Switching Characteristics

fOSC Oscillator Frequency Test Circuit 1 460 550 650 kHz

ΦOSC Core and I/O Oscillator Phase Difference (Note 7) 180 DEG

DCMAX Maximum Duty Cycle 87 90 93 %

tNOV Driver Nonoverlap Test Circuit 1, 50% to 50% 10 25 120 ns

tr, tf Driver Rise/Fall Time Test Circuit 1, 10% to 90% 15 100 ns

Clock Supply Output

VOUTCLK CLK Output Voltage IVOUTCLK = 0mA 2.45 2.50 2.55 V

dVOUTCLK Output Voltage Line Regulation VINCLK = 3.0V to 5.5V ±0.02 ±0.1 %/V

Output Voltage Load Regulation IVOUTCLK = 0mA to 150mA –0.1 –0.05 %

ILMCLK CLK Output Short-Circuit Current IVOUTCLK = 0V –240 –150 mA

VDROPOUT CLK Output Dropout Voltage IVOUTCLK = 150mA, dVOUTCLK = –1% (Note 8) 0.3 0.5 V

VPGOOD Negative VOUTCLK Power Good Threshold Relative to VOUTCLK –15 –10 –6 %Positive VOUTCLK Power Good Threshold Relative to VOUTCLK 6 10 15 %

VID Inputs

R1 Resistance Across SENSEC and FBC 10 kΩRVID VID Input Pull-Up Resistance (Note 9) 30 kΩVVID VID Input Threshold 0.4 1.6 V

PGOOD

IPGOOD VPGOOD Sink Current Power Good 10 µAPower Bad 10 mA

VOLPG PGOOD Output Low Voltage IPGOOD = 1mA 0.03 0.1 V

TPGOOD VPGOOD Falling Edge Delay 2 4 8 µsVPGOOD Rising Edge Delay 10 20 40 µsVPBAD Pulse VID Code Change 10 20 40 µs

Note 1: Absolute Maximum Ratings are those values beyond which the lifeof a device may be impaired.Note 2: The LTC1705 is guaranteed to meet performance specificationsfrom 0°C to 70°C. Specifications over the –40°C to 85°C operatingtemperature range are assured by design, characterization and correlationwith statistical process controls.Note 3: All currents into device pins are positive; all currents out of devicepins are negative. All voltages are referenced to ground unless otherwisespecified.Note 4: PVCC and BVCC (VBOOST – VSW) must be greater than VGS(ON) ofthe external MOSFETs to ensure proper operation.Note 5: Supply current in normal operation is dominated by the currentneeded to charge and discharge the capacitance of the external MOSFET

gates. This current varies with supply voltage and the choice of externalMOSFETs.Note 6: Supply current in shutdown is dominated by external MOSFETleakage and may be significantly higher than the quiescent current drawnby the LTC1705, especially at elevated temperature.Note 7: Guaranteed by design, not subject to test.Note 8: Dropout voltage is the minimum input-to-output voltagedifferential required to maintain regulation at the specified output current.In dropout, the output voltage will be equal to VINCLK – VDROPOUT.Note 9: Each internal pull-up resistor attached to the VID inputs has aseries diode connected to VCC to allow input voltages higher than the VCCsupply without damage or clamping. (See Block Diagram.)Note 10: The core feedback voltage accuracy is guaranteed by the VSENSEoutput voltage accuracy test.

LTC1705

4

TEMPERATURE (°C)–50 –25 0 25 50 75 100 125

V SEN

SEC

(V)

1705 G01

1.315

1.310

1.305

1.300

1.295

1.290

1.285

VCC = 5VVOUT = 1.3V

VCC (V)3 3.5 4 4.5 5 5.5 6

∆VSE

NSEC

(mV)

1705 G02

1.30

1.04

0.78

0.52

0.26

0

–0.26

–0.52

–0.78

–1.04

–1.30

∆VSENSE (%

)

0.10

0.08

0.06

0.04

0.02

0

–0.02

–0.04

–0.06

–0.08

–0.10

TA = 25°C

ILOAD (A)0 3 6 9 12 15

∆VSE

NSEC

(mV)

1705 G03

0.8

0

–0.8

–1.6

–2.4

–3.2

∆VSENSE (%

)0.05

0

–0.05

–0.10

–0.15

–0.20

TA = 25°CVOUT = 1.6V

ILOAD (A)0 3 6 9 12 15

EFFI

CIEN

CY (%

)

1705 G04

100

90

80

70

60

50

VIN = 5V, TA = 25°C, I/O DISABLEDQTC = QBC = 2× FDS6670A

VOUT = 2V

VOUT = 1.6V

VOUT = 0.9V

TEMPERATURE (°C)–50 –25 0 25 50 75 100 125

V FBI

O (V

)

1705 G05

0.810

0.806

0.802

0.798

0.794

0.790

VCC = 5V

VCC (V)3 3.5 4 4.5 5 5.5 6

∆VFB

IO (m

V)

1705 G06

0.80

0.64

0.48

0.32

0.16

0

–0.16

–0.32

–0.48

–0.64

–0.80

∆VFBIO (%

)

0.10

0.08

0.06

0.04

0.02

0

–0.02

–0.04

–0.06

–0.08

–0.10

TA = 25°C

TYPICAL PERFOR A CE CHARACTERISTICS

UW

VSENSEC vs Temperature VSENSEC Line Regulation

VSENSEC Load Regulation Core Supply Efficiency

VFBIO vs Temperature VFBIO Line Regulation

LTC1705

5

ILOAD (A)0 0.5 1 1.5 2 2.5

EFFI

CIEN

CY (%

)

1705 G07

100

90

80

70

60

50

VIN = 5V, VOUT = 1.5V, TA = 25°C, CORE DISABLED, QTIO = QBIO = NDS8926

TEMPERATURE (°C)–50 –25 0 25 50 75 100 125

CURR

ENT

LIM

IT T

HRES

HOLD

(A)

1705 G09

24

22

20

18

16

14

12

10

VIN = 5V, VOUT = 1.6V, ∆VOUT = –1%,RIMAXC = 24.9k, QTC = QBC = 2× FDS6670A

LOAD CURRENT (A)0 4 8 12 16 20

V OUT

C (V

)

1705 G10

2.0

1.5

1.0

0.5

0

TA = 25°C, VIN = 5V, VOUT = 1.6V,QBC = 2× FDS6670A, RIMAXC = 24.9k,CRUNSS = 0.01µF

TEMPERATURE (°C)–50 –25 0 25 50 75 100 125

V OUT

CLK

(V)

1705 G11

2.55

2.54

2.53

2.52

2.51

2.50

2.49

2.48

2.47

2.46

2.45

VINCLK = 3.3V

VINCLK (V)3 3.5 4 4.5 5 5.5 6

∆VOU

TCLK

(mV)

1705 G12

2.5

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

∆VOUTCLK (%

)

0.10

0.08

0.06

0.04

0.02

0

–0.02

–0.04

–0.06

–0.08

–0.10

TA = 25°C

∆VOU

TCLK

(mV)

1705 G13

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

∆VOUTCLK (%

)

0.02

0

–0.02

–0.04

–0.06

–0.08

–0.10

IOUTCLK (mA)–150 –125 –100 –75 –50 –25 0

TA = 25°C

TEMPERATURE (°C)–50 –25 0 25 50 75 100 125

V DRO

POUT

(mV)

1705 G14

500

450

400

350

300

250

200

150

100

IOUTCLK = –150mA

TEMPERATURE (°C)–50 –25 0 25 50 75 100 125

ILM

CLK

(mA)

1705 G15

–150

–190

–230

–270

–310

–350

VINCLK = 3.3V

TYPICAL PERFOR A CE CHARACTERISTICS

UW

I/O Supply Efficiency VOUTC 0A To 10A Load StepCurrent Limit Threshold vsTemperature

0A TO 10ALOAD

5A/DIV

VOUT = 1.6VAC 50mV/

DIV

5ms/DIV 1705 G08

VOUTC vs Load Current VOUTCLK vs Temperature VOUTCLK Line Regulation

VOUTCLK Load RegulationVOUTCLK Dropout Voltage vsTemperature

VOUTCLK Short-Circuit Current vsTemperature

LTC1705

6

f OSC

(kHz

)

1705 G20

650

610

570

530

490

450

VCC (V)3 3.5 4 4.5 5 5.5 6

TA = 25°C

TEMPERATURE (°C)–50 –25 0 25 50 75 100 125

I IMAX

(µA)

1705 G21

–8.0

–8.5

–9.0

–9.5

–10.0

–10.5

–11.0

–11.5

–12.0

VCC = 5V

I IMAX

(µA)

1705 G22

–8.0

–8.5

–9.0

–9.5

–10.0

–10.5

–11.0

–11.5

–12.0

TA = 25°C

VCC (V)3 3.5 4 4.5 5 5.5 6

TEMPERATURE (°C)–50 –25 0 25 50 75 100 125

VID

INPU

T TH

RESH

OLD

(V)

1705 G23

1.6

1.4

1.2

1.0

0.8

0.6

0.4

VCC = 5V

VID

INPU

T TH

RESH

OLD

(V)

1705 G24

1.6

1.4

1.2

1.0

0.8

0.6

0.4

VCC (V)3 3.5 4 4.5 5 5.5 6

TA = 25°C

TEMPERATURE (°C)–50 –25 0 25 50 75 100 125

SUPP

LY C

URRE

NT (m

A)

1705 G25

6.0

4.5

3.0

1.5

0

VCC = PVCC = BVCC = 5V, VINCLK = 3.3V,TGC, BGC, TGIO, BGIO FLOAT

IVCC

IPVCC, IBOOST

IVINCLK

TYPICAL PERFOR A CE CHARACTERISTICS

UW

fOSC vs VCC IIMAX vs Temperature IIMAX vs VCC

VID Input Threshold vsTemperature VID Input Threshold vs VCC Supply Current vs Temperature

ILM

CLK

(mA)

1705 G16

–150

–190

–230

–270

–310

–350

VINCLK (V)3 3.5 4 4.5 5 5.5 6

TA = 25°C

TEMPERATURE (°C)–50 –25 0 25 50 75 100 125

f OSC

(kHz

)

1705 G19

650

630

610

590

570

550

530

510

490

470

450

VCC = 5V

VOUTCLK Short-Circuit Current vsVINCLK

VOUTCLK 10mA To 150mA LoadStep fOSC vs Temperature

VOUTCLKAC 5mV/DIV

10mA TO150mA LOAD

100mA/DIV

2ms/DIV 1705 G18.tif

LTC1705

7

IMAXIO (Pin 1): I/O Supply Current Limit Set. The IMAXIO pinsets the current limit comparator threshold for the I/Ocontroller. If the voltage drop across the bottom MOSFET,QBIO, exceeds the magnitude of the voltage at IMAXIO, theI/O controller enters current limit. The IMAXIO pin has aninternal 10µA current source pull-up, allowing the currentthreshold to be set with a single external resistor to PGND.Kelvin connect this current setting resistor to the source ofQBIO. Refer to the Current Limit Programming section formore information on choosing the value of RIMAX.

PVCC (Pin 2): Driver Power Supply Input. PVCC providespower to the BGC and BGIO output drivers. PVCC must beconnected to a voltage high enough to fully turn on theexternal MOSFETs QBC and QBIO. PVCC should generallybe connected directly to VIN, the main system 5V supply.PVCC requires at least a 10µF bypass capacitor directly toPGND.

BOOSTC (Pin 3): Core Controller Top Gate Driver Supply.The BOOSTC pin supplies power to the floating TGC driver.Bypass BOOSTC to SWC with a 1µF capacitor. An externalschottky diode from VIN to BOOSTC creates a completefloating charge-pumped supply at BOOSTC. No otherexternal supplies are required.

PI FU CTIO S

UUU

BGC (Pin 4): Core Supply Bottom Gate Drive. The BGC pindrives the gate of the bottom N-channel synchronousswitch MOSFET, QBC. BGC is designed to typically driveup to 10,000pF of gate capacitance. If RUN/SS goes low,BGC goes low, turning off QBC.

TGC (Pin 5): Core Supply Top Gate Drive. The TGC pindrives the gate of the top N-channel MOSFET, QTC. TheTGC driver draws power from the BOOSTC pin and returnsit to the SWC pin, providing true floating drive to QTC. TGCis designed to typically drive up to 10,000pF of gatecapacitance. If RUN/SS goes low, TGC goes low, turningoff QTC.

SWC (Pin 6): Core Supply Switching Node. Connect SWCto the switching node of the core converter. The TGC driverground returns to SWC, providing floating gate drive to thetop N-channel MOSFET switch, QTC. The voltage at SWCis compared to IMAXC by the current limit comparator whilethe bottom MOSFET, QBC, is on.

PGND (Pin 7): Power Ground. The BGC and BGIO driversreturn to this pin. Connect PGND to a high-current groundnode in close proximity to the sources of external MOSFETsQBC and QBIO, and the VIN and VOUT bypass capacitors.

IMAXC (Pin 8): Core Supply Current Limit Set. See IMAXIO.

TG, BG LOAD (pF)0 2000 4000 6000 8000 10000

I/O I P

VCC,

I BOO

ST (m

A)

1705 G26

12

10

8

6

4

2

0

CORE IPVCC , IBOOST (mA)

36

30

24

18

12

6

0TA = 25°C, PVCC = BOOST = 5V

COREDRIVERSSUPPLYCURRENT WITH I/O DISABLED

I/O DRIVERSSUPPLY CURRENT WITH CORE DISABLED

TG, BG LOAD (pF)0 2000 4000 6000 8000 10000

t r, t

f (ns

)

1705 G27

60

50

40

30

20

10

0

TA = 25°C, PVCC = BOOST = 5V

COREDRIVERS

I/O DRIVERS

TEMPERATURE (°C)–50 –25 0 25 50 75 100 125

V SHD

N (V

)

1705 G28

0.80

0.68

0.56

0.44

0.32

0.20

VCC = 5VMEASURED AT RUN/SS

IPVCC, IBOOST vs Driver LoadDrivers Rise and Fall Time vsLoad VSHDN vs Temperature

TYPICAL PERFOR A CE CHARACTERISTICS

UW

LTC1705

8

RUN/SS (Pin 9): SoftStart. Pulling RUN/SS to GND exter-nally shuts down the LTC1705 and turns off all the externalMOSFET switches. The quiescent supply current dropsbelow 100µA. A capacitor from RUN/SS to GND controlsthe turn on time and rate of rise of the core and I/O outputvoltages at power up. An internal 3µA current source pull-up at RUN/SS sets the turn-on time at approximately300ms/µF.

COMPC (Pin 10): Core Controller Loop Compensation.The COMPC pin is connected directly to the output of theCore controller’s error amplifier and the input of the PWMcomparator. Use an RC network between the COMPC pinand the FBC pin to compensate the feedback loop foroptimum transient response.

FBC (Pin 11): Core Controller Feedback Input. Connect theloop compensation network for the core controller to FBC.FBC internally connects to the VID resistor network to setthe Core output voltage.

GND (Pin 12): Signal Ground. All internal low powercircuitry returns to the GND pin. Connect to a low imped-ance ground, separated from the PGND node. All feed-back, compensation and softstart connections shouldreturn to GND. GND and PGND should connect only at asingle point, near the PGND pin and the negative plate ofthe VIN bypass capacitor.

SENSEC (Pin 13): Core Controller Output Sense. Connectto VOUTC.

VID0 to VID4 (Pins 14 to 18): VID Programming Inputs.These are logic inputs that set the output voltage at theCore supply to a preprogrammed value (see Table 1). VID4is the MSB, VID0 is the LSB. The codes selected by the VIDinputs correspond to the Intel Mobile VID specification.Any VID code transition forces PGOOD to go low for 20µs.Each VID pin includes an on-chip 30k pull-up resistor inseries with a diode (see Block Diagram).

VCC (Pin 19): Power Supply Input. All internal circuitsexcept the output drivers are powered from this pin.Connect VCC to a low-noise 5V supply and bypass the pinto GND with at least a 10µF capacitor in close proximity tothe LTC1705.

PI FU CTIO S

UUU

FBIO (Pin 20): I/O Controller Feedback Input. ConnectFBIO through a resistor divider network to VOUTIO to set theoutput voltage. Also, connect the loop compensationnetwork for the I/O controller to FBIO.

COMPIO (Pin 21): I/O Controller Loop Compensation. SeeCOMPC.

PGOOD (Pin 22): Power Good. PGOOD is an open-drainlogic output. PGOOD pulls low if any of the three supplyoutputs are out of regulation (see Electrical Characteris-tics table for Core, I/O and CLK thresholds). An externalpull-up resistor is required at PGOOD to allow it to swingpositive.

VOUTCLK (Pin 23): Clock Supply Output. VOUTCLK is theoutput node of the internal linear clock supply regulator.VOUTCLK provides up to 150mA at the 2.5V output to powerthe CPU CLK supply. Bypass VOUTCLK with at least a 2.2µFcapacitor to GND (refer to the VCLK Linear Regulatorsection). If RUN/SS goes low, the VOUTCLK regulator shutsdown.

VINCLK (Pin 24): Clock Supply Input. VINCLK is the inputterminal to the internal linear CLK supply regulator. Con-nect VINCLK to a 3.3V supply to maximize efficiency. VINCLKcan be connected to the 5V supply, but the efficiency of theVOUTCLK regulator is reduced. Bypass VINCLK with a 10µFcapacitor to GND.

SWIO (Pin 25): I/O Controller Switching Node. See SWC.

TGIO (Pin 26): I/O Controller Top Gate Drive. See TGC.TGIO is designed to typically drive up to 2,000pF of gatecapacitance.

BOOSTIO (Pin 27): I/O Controller Top Gate Driver Power.See BOOSTC.

BGIO (Pin 28): I/O Controller Bottom Gate Drive. See BGC.BGIO is designed to typically drive up to 2,000pF of gatecapacitance.

LTC1705

9

BLOCK DIAGRA

W

IOSO

FT-

STAR

T

IODR

IVER

LOGI

C

ILM

IO

10µA

PWRG

DDE

LAY

OSC

550k

Hz

0.72

V

0.88

V

0.8V

0.76

V0.

84V

PVCC

1.08

V1.

2V

1.32

V

CORE

SOFT

-ST

ART

BAND

GAP

REFE

RENC

E

CORE

DRIV

ERLO

GIC

0.72

V

0.88

V

V CC

0.76

V0.

84V

PVCC

0.8V

R BR1 10k

10k

30k

MPG

POW

ER D

OWN

ENTI

RE C

HIP

PWRBAD IO

PWRBAD COREPWRBAD CLK

0.5V

30k

TO IN

TERN

ALCI

RCUI

TRY

30k

30k

30k

10µA

FBC

MIN

IOM

AXIO

MAX

CM

INC

FBIO

PPGI

O

NPGI

O

PPGC

LK

NPGC

LKAM

P

PPGC

NPGC

SCM

P

PWM

CPW

MIO

ILM

C

I MAX

C

BOOS

TC

PGOO

DRU

N/SS

TGC

SWC

BGC

COM

PC FBC

SENS

EC

I MAX

IO

BOOS

TIO

TGIO

SWIO

BGIO

COM

PIO

FBIO

V INC

LK

V OUT

CLK

1705

BD

PVCC

PGND

VID0

VID1

VID2

VID3

VID4

GND

V CC

3µA

219

922

1 27 26 25 28 20 21 24 23

127

1817

1615

14

13111046538

–+

+–

+–

LTC1705

10

Table 1. VID Inputs and Corresponding Core Output VoltagesCODE VID4 VID3 VID2 VID1 VID0 VOUTC

00000 Gnd Gnd Gnd Gnd Gnd 2.00V

00001 Gnd Gnd Gnd Gnd Float 1.95V

00010 Gnd Gnd Gnd Float Gnd 1.90V

00011 Gnd Gnd Gnd Float Float 1.85V

00100 Gnd Gnd Float Gnd Gnd 1.80V

00101 Gnd Gnd Float Gnd Float 1.75V

00110 Gnd Gnd Float Float Gnd 1.70V

00111 Gnd Gnd Float Float Float 1.65V

01000 Gnd Float Gnd Gnd Gnd 1.60V

01001 Gnd Float Gnd Gnd Float 1.55V

01010 Gnd Float Gnd Float Gnd 1.50V

01011 Gnd Float Gnd Float Float 1.45V

01100 Gnd Float Float Gnd Gnd 1.40V

01101 Gnd Float Float Gnd Float 1.35V

01110 Gnd Float Float Float Gnd 1.30V

01111* Gnd Float Float Float Float 1.25V

VID PROGRA I G CODESWUW

10000 Float Gnd Gnd Gnd Gnd 1.275V

10001 Float Gnd Gnd Gnd Float 1.250V

10010 Float Gnd Gnd Float Gnd 1.225V

10011 Float Gnd Gnd Float Float 1.200V

10100 Float Gnd Float Gnd Gnd 1.175V

10101 Float Gnd Float Gnd Float 1.150V

10110 Float Gnd Float Float Gnd 1.125V

10111 Float Gnd Float Float Float 1.100V

11000 Float Float Gnd Gnd Gnd 1.075V

11001 Float Float Gnd Gnd Float 1.050V

11010 Float Float Gnd Float Gnd 1.025V

11011 Float Float Gnd Float Float 1.000V

11100 Float Float Float Gnd Gnd 0.975V

11101 Float Float Float Gnd Float 0.950V

11110 Float Float Float Float Gnd 0.925V

11111* Float Float Float Float Float 0.900V

*01111 and 11111 are defined by Intel to signify “no CPU.” The LTC1705generates the output voltages shown if these codes are selected.

CODE VID4 VID3 VID2 VID1 VID0 VOUTC

BGC

IMAXC

COMPC

FBCVFBC

VCC PVCC

LTC1705

SWC PGND GND SWIO

VINCLK

SENSEC

BOOSTC

TGC

1705 TC

VIDO:4

RUN/SSRUN/SS

BGIO

IMAXIO

COMPIO

FBIO VFBIO

VOUTCLK

BOOSTIO

IVINCLK IBOOSTIOIBOOSTC IPVCCIVCC

5V

TGIO

PGOOD

VOUTCLK

2k2k

0.1µF100µF+

10µF+

1000pF 1000pF2000pF2000pF

fOSCIOfOSCC

Test Circuit 1

TEST CIRCUIT

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The LTC1705 includes two, step-down (buck), voltagemode feedback switching regulator controllers and a lowdropout linear regulator. The three outputs are designed topower the core, I/O and CLK supplies of an Intel MobilePentium system. Each switching regulator controller em-ploys a synchronous switching architecture with twoexternal N-channel MOSFETs per channel. The chip oper-ates from a low voltage input supply (6V maximum) andprovides high power, high efficiency, precisely regulatedoutput voltages. Several features make the LTC1705 par-ticularly suited for microprocessor supply regulation.Output regulation at the core supply is extremely tight,with initial accuracy and DC line and load regulation betterthan 1.25%. Total regulation including transient responseis inside of 3.5% with a properly designed circuit. The550kHz switching frequency and the high speed internalfeedback amplifiers allow the use of physically small, lowvalue external components without compromising perfor-mance. An onboard 5-bit DAC sets the core output voltage,consistent with the Intel Mobile VID specification (Table 1).

The 800mV internal reference allows regulated outputvoltages as low as 800mV without external level shiftingamplifiers. The linear regulator controls an internal P-channel MOSFET that can provide more than 150mA ofcurrent at an output voltage of 2.5V. A power good(PGOOD) flag goes high when all the three outputs are inregulation.

2-Step Conversion

“2-step” architectures use a primary regulator to convertthe input power source (batteries or AC line voltage) to anintermediate supply voltage, often 5V. This intermediatevoltage is then converted to the low voltage, high currentsupplies required by the system using a secondary regula-tor, such as the LTC1705. 2-step conversion eliminates theneed for a single converter to convert a high input voltageto a very low output voltage, often an awkward designchallenge. It also fits naturally into systems that continue touse the 5V supply to power portions of their circuitry or haveexcess 5V capacity available as newer circuit designs shiftthe current load to lower voltage supplies.

Each regulator in a typical 2-step system maintains arelatively low step-down ratio (5:1 or less), running at high

efficiency while maintaining reasonable duty cycle. Incontrast, a regulator converting in a single step from a highinput voltage to a 1.xV output must operate at a verynarrow duty cycle, mandating trade-offs in external com-ponent values while compromising efficiency and tran-sient response. The efficiency loss can exceed that of a2-step solution. Further complicating the calculation is thefact that many systems draw a significant fraction of theirtotal power off the intermediate 5V supply, bypassing thelow voltage supply. 2-step solutions using the LTC1705usually match or exceed the total system efficiency ofsingle-step solutions and provide the additional benefitsof improved transient response, reduced PCB area andsimplified power trace routing.

2-step regulation can also buy advantages in thermalmanagement. Power dissipation in the LTC1705 portionof a 2-step circuit is lower than it would be in a typical1-step converter, even in cases where the 1-step converterhas higher total efficiency than the 2-step system. In atypical microprocessor core supply regulator, for ex-ample, the regulator is usually located directly next to theCPU. In a 1-step design, all of the power dissipated by thecore regulator is located next to the already hot CPU,aggravating thermal management. In a 2-step LTC1705design, a significant percentage of the power lost in thecore regulation system happens in the 5V supply, which isusually located away from the CPU. The power lost to heatin the LTC1705 section of the system is relatively low,minimizing the added heat near the CPU.

Fast Transient Response

The LTC1705 core and I/O supplies use fast 20MHz GBWop amps as error amplifiers. This allows the compensationnetwork to be designed with several poles and zeros in amore flexible configuration than with typical gm feedbackamplifiers. The high bandwidth of the amplifier, coupledwith the high 550kHz switching frequency and the lowvalues of the external inductor and output capacitor, allowvery high loop cross-over frequencies. Additionally, atypical LTC1705 circuit uses an inductor value on theorder of 1µH, allowing very fast di/dt slew rates. The resultis superior transient response compared with conven-tional solutions.

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High Efficiency

The LTC1705 core and I/O supplies use a synchronousstep-down (buck) architecture, with two external N-chan-nel MOSFETs per output. A floating topside driver and asimple external charge pump provide full gate drive toeach upper MOSFET. The voltage mode feedback loopsand MOSFET VDS current limit sensing circuits remove theneed for external current sense resistors, eliminatingexternal components and the corresponding power lossesin the high current paths. Properly designed circuits usinglow gate charge MOSFETs are capable of efficienciesexceeding 90% over a wide range of output voltages andload currents.

VID Programming

The LTC1705 includes an onboard feedback network thatprograms the core output voltage in accordance with theIntel Mobile VID specification (Table 1). This networkincludes a 10k resistor connected between SENSEC andFBC and a variable value resistor connected between FBCand GND, with the value set by the digital code present atthe VID4:0 pins. Connect SENSEC to VOUTC to allow thenetwork to monitor the output voltage. No additionalfeedback components are required to set the output volt-age of the core controller, although loop compensationcomponents are still required. Each VIDn pin includes aninternal 30k pull-up resistor, allowing it to float high if leftunconnected. The pull-up resistors connect to VCC throughdiodes (see Block Diagram), allowing the VIDn pins to bepulled above VCC without damage.

Note that codes 01111 and 11111, defined by Intel toindicate “no CPU present, ” do generate output voltages atVOUTC (1.25V and 0.9V, respectively). Also, note that theI/O and CLK outputs on the LTC1705 are not connected tothe VID circuitry and work independently from the corecontroller.

Linear Regulator and Thermal Shutdown

The LTC1705 CLK output is an easy to use monolithic LDO.The VINCLK pin powers the regulator and an internalP-channel MOS transistor provides the output current atthe 2.5V output. An external 10µF capacitor frequency

compensates the linear regulator feedback loop. The CLKoutput is short-circuit protected and the built-in thermalshutdown circuit turns off all three regulator outputsshould the LTC1705 junction temperature exceed 155°C.

SWITCHING ARCHITECTURE DETAILS

The LTC1705 dual switching regulator controller includestwo independent regulator channels. The two switchingregulator controllers and their corresponding externalcomponents act independently of each other with theexception of the common input bypass capacitor. TheRUN/SS and PGOOD pins also affect both channels. In thefollowing discussions, when a pin is referred to withoutmentioning which side is involved, that discussion appliesequally to both sides.

Switching Architecture

Each half of the LTC1705 is designed to operate as asynchronous buck converter (Figure 1). Each channelincludes two high power MOSFET gate drivers to controlexternal N-channel MOSFETs QT and QB. The core drivershave 0.5Ω output impedances and can carry well over anamp of continuous current with peak currents up to 5A toslew large MOSFET gates quickly. The I/O drivers have 2Ωoutput impedances. The external MOSFETs are connectedwith the drain of QT attached to the input supply and thesource of QT at the switching node SW. QB is the synchro-nous rectifier with its drain at SW and its source at PGND.SW is connected to one end of the inductor, with the otherend connected to VOUT. The output capacitor is connectedfrom VOUT to PGND.

When a switching cycle begins, QB is turned off and QT isturned on. SW rises almost immediately to VIN and theinductor current begins to increase. When the PWM pulsefinishes, QT turns off and one nonoverlap interval later, QBturns on. Now SW drops to PGND and the inductor currentdecreases. The cycle repeats with the next tick of themaster clock. The percentage of time spent in each modeis controlled by the duty cycle of the PWM signal, which inturn is controlled by the feedback amplifier. The masterclock runs at a 550kHz rate and turns QT on once every1.8µs. In a typical application with a 5V input and a 1.5V

LTC1705

13

output, the duty cycle will be set at 1.5/5 • 100% or 30%by the feedback loop. This will give roughly a 540ns on-time for QT and a 1.26µs on-time for QB.

This constant frequency operation brings with it a coupleof benefits. Inductor and capacitor values can be chosenwith a precise operating frequency in mind and the feed-back loop components can be similarly tightly specified.Noise generated by the circuit will always be in a knownfrequency band with the 550kHz frequency designed toleave the 455kHz IF band free of interference. Subharmonicoscillation and slope compensation, common headacheswith constant frequency current mode switchers, areabsent in voltage mode designs like the LTC1705.

During the time that QT is on, its source (the SW pin) is atVIN. VIN is also the power supply for the LTC1705. How-ever, QT requires VIN+VGS(ON) at its gate to achieve mini-mum RON. This presents a problem for the LTC1705—itneeds to generate a gate drive signal at TG higher than itshighest supply voltage. To accomplish this, the TG driverruns from floating supplies, with its negative supplyattached to SW and its power supply at BOOST. Thisallows it to slew up and down with the source of QT. In

combination with a simple external charge pump (Figure2), this allows the LTC1705 to completely enhance thegate of QT without requiring an additional, higher supplyvoltage.

The two channels of the LTC1705 run from a commonclock, with the phasing chosen to be 180° from the coreside to the I/O side. This has the effect of doubling thefrequency of the switching pulses seen by the inputbypass capacitor, lowering the RMS current seen by thecapacitor and reducing the value required.

Feedback Amplifier

Each side of the LTC1705 senses the output voltage atVOUT with an internal feedback op amp (see Block Dia-gram). This is a real op amp with a low impedance output,85dB open-loop gain and 20MHz gain bandwidth product.The positive input is connected internally to an 800mVreference, while the negative input is connected to the FBpin. The output is connected to COMP, which is in turnconnected to the soft-start circuitry and from there to thePWM generator.

Unlike many regulators that use a resistor divider con-nected to a high impedance feedback input, the LTC1705is designed to use an inverting summing amplifier topol-ogy with the FB pin configured as a virtual ground. Thisallows flexibility in choosing pole and zero locations notavailable with simple gm configurations. In particular, itallows the use of “Type 3” compensation, which providesa phase boost at the LC pole frequency and significantlyimproves loop phase margin (see Figure 3). Note that thecore side of the LTC1705 includes R1 and RB internally aspart of the VID DAC circuitry.

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TG

SW

BGPGND

LTC1705

QTCIN

QB

L

+

COUT

1705 F01

VOUT

VIN

+

TG CCP

DCPBOOST

SW

BG

PGND

PVCCLTC1705

QT

CIN

QB

L

+

COUT

1705 F02

VOUT

VIN

+

–

+FB

0.8V

R1FBVOUT

LTC1705

COMP

1705 F03

R3C3

C2

RB

R2C1

Figure 2. Floating TG Driver Supply

Figure 1. Synchronous Buck Architecture

Figure 3. "Type 3" Feedback Loop (I/O Channel)

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MIN/MAX Comparators

Two additional feedback loops keep an eye on the mainfeedback amplifier and step in if the feedback node moves±5% from its nominal 800mV value. The MAX comparator(see Block Diagram) activates if FB rises more than 5%above 800mV. It immediately turns the top MOSFET (QT)off and the bottom MOSFET (QB) on and keeps them thatway until FB falls back within 5% of its nominal value. Thispulls the output down as fast as possible, preventingdamage to the (often expensive) load. If FB rises becausethe output is shorted to a higher supply, QB will stay onuntil the short goes away, the higher supply current limitsor QB dies trying to save the load. This behavior providesmaximum protection against overvoltage fault at the out-put, while allowing the circuit to resume normal operationwhen the fault is removed.

The MIN comparator (see Block Diagram) trips if FB ismore than 5% below 800mV and immediately forces theswitch duty cycle to 90% to bring the output voltage backinto range. It releases when FB is within the 5% window.MIN is disabled when the soft-start or current limit circuitsare active—the only two times that the output shouldlegitimately be below its regulated value.

Notice that the FB pin is the virtual ground node of thefeedback amplifier. A typical compensation network doesnot include local DC feedback around the amplifier, so thatthe DC level at FB will be an accurate replica of the outputvoltage, divided down by R1 and RB (Figure 3). However, thecompensation capacitors will tend to attenuate AC signalsat FB, especially with low bandwidth Type 1 feedback loops.This can create a situation where the MIN, MAX and PGOODcomparators do not respond immediately to shifts in theoutput voltage, if they monitor the output at FB. With VIDcode switching on the fly, this problem is aggravated.

To overcome this, a second resistor divider is used (seeBlock Diagram) to provide the MIN, MAX and PGOODcomparators with an accurate replica of the output voltage.This ensures that the comparators react rapidly to codechanges. For the I/O channel, the output voltage is indepen-dent of VID codes and therefore the change in VOUT isminimized. Maximizing I/O feedback loop bandwidth willminimize these delays and allow MIN and MAX to operateproperly. See the Feedback Loop/Compensation section.

PGOOD Flag

The LTC1705 incorporates a power good pin (PGOOD).PGOOD is an open-drain output and requires an externalpull-up resistor. If all three regulators are typically within±10% of their nominal value, transistor MPG shuts off (seeBlock Diagram) and PGOOD is pulled high by the externalpull-up resistor. If any of the three outputs is more than10% outside the nominal value for more than 4µs, PGOODpulls low, indicating that an output is out of regulation. ForPGOOD to pull high, all three outputs must be in regulationfor more than 20µs. PGOOD remains active during softstart and current limit. On power up, PGOOD pulls low. Assoon as the RUN/SS pin rises above the shutdown thresh-old, the three pair of power good comparators take overand control the transistor MPG directly. The 4µs and 20µsdelay ensure that short output transient glitches, that aresuccessfully “caught” by the power good comparators,don’t cause momentary glitches at the PGOOD pin.

For the core channel, if there is a VID code change, theinternal DAC responds by switching its output voltageimmediately. However, the switching power supply outputslew rate is limited by the output filter. If the VID code stepchange is small, the power good comparator might notregister any transition. To acknowledge the code transi-tion command , the LTC1705 forces PGOOD to pull low for20µs once there is a VID code change. After this shortinterval, the power good comparators decide the PGOODstatus.

Shutdown/Soft-Start

The RUN/SS pin performs two functions: if pulled toground, it shuts down the LTC1705 and it acts as aconventional soft-start pin, enforcing a maximum dutycycle limit proportional to the voltage at RUN/SS. Aninternal 3µA current source pull-up is connected to theRUN/SS pin, allowing a soft-start ramp to be generatedwith a single external capacitor to ground. The 3µA currentsource is active even if the LTC1705 is shut down, ensur-ing the device will start when any external pull-down atRUN/SS is released. In shutdown, the LTC1705 entersmicropower sleep mode and quiescent current dropstypically below 50µA.

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The RUN/SS pin shuts down the LTC1705 if it falls below0.5V (Figure 4). Between 0.5V and about 1V, the LTC1705wakes up and the duty cycle is kept to a miminum. As thepotential at RUN/SS increases, the duty cycle increaseslinearly between 1V and 2V, reaching its final value of 90%when RUN/SS is above 2V. Somewhere before this point,the feedback amplifier will assume control of the loop andthe output will come into regulation. When RUN/SS risesto 1V below VCC , the MIN feedback comparator is enabledand the LTC1705 is in full operation.

includes a trimmed 10µA pull-up, enabling the user to setthe voltage at IMAX with a single resistor, RIMAX, to ground.The LTC1705 compares the two inputs and begins limitingthe output current when the magnitude of the negativevoltage at the SW pin is greater than the voltage at IMAX .When the load current increases abruptly, the voltagefeedback loop forces the duty cycle to increase rapidly andthe on-time of QB will be small momentarily. The RDS(ON)of QB must be low enough to ensure that the SW node ispulled low within the QB on-time for proper currentsensing.

The current limit detector is connected to an internal gmamplifier that pulls a current from the RUN/SS pin propor-tional to the difference in voltage magnitudes between theSW and IMAX pins. The maximum value of this current is250µA (typically). It begins to discharge the soft-startcapacitor at RUN/SS, reducing the duty cycle and control-ling the output voltage until the current drops below thelimit. The soft-start capacitor needs to move a fair amountbefore it has any effect on the duty cycle, adding a delayuntil the current limit takes effect (Figure 4). This allowsthe LTC1705 to experience brief overload conditions with-out affecting the output voltage regulation. The delay alsoacts as a pole in the current limit loop to enhance loopstability. While the soft-start capacitor is being discharged,the top MOSFET must withstand the high power dissipa-tion due to the high current especially if the regulator ispowered by a high current supply. Larger overloads causethe soft-start capacitor to pull down quickly, protecting theoutput components from damage. The current limit gmamplifier includes a clamp to prevent it from pulling RUN/SS below 0.5V and shutting off the LTC1705.

Power MOSFET RDS(ON) varies from MOSFET to MOSFET,limiting the accuracy obtainable from the LTC1705 currentlimit loop. Additionally, ringing on the SW node due toparasitics can add to the apparent current, causing theloop to engage early. The LTC1705 current limit is de-signed primarily as a disaster prevention, “no blow up”circuit and is not useful as a precision current regulator. Itshould typically be set around 50% above the maximumexpected normal output current to prevent componenttolerances from encroaching on the normal current range.See the Current Limit Programming section for advice onchoosing a valve for RIMAX .

Figure 4. Soft-Start Operation in Start Up and Current Limit

0V

VOUT

5V

4V

2V

1V0.5V

MINIMUM DUTY CYCLE

0V

1705 F04

POWER-DOWN MODELTC1705 ENABLE

MIN COMPARATORENABLE

RUN/SS CONTROLS DUTY CYCLE

COMP CONTROLS DUTY CYCLE

START UP NORMALOPERATION

CURRENTLIMIT

Current Limit

The LTC1705 includes an onboard current limit circuit thatlimits the maximum output current to a user-programmedlevel. It works by sensing the voltage drop across QBduring the time that QB is on and comparing that voltageto a user-programmed voltage at IMAX. Since QB looks likea low value resistor during its on-time, the voltage dropacross it is proportional to the current flowing in it. In abuck converter, the average current in the inductor is equalto the output current. This current also flows through QBduring its on-time. Thus, by watching the voltage acrossQB, the LTC1705 can monitor the output current.

Any time QB is on and the current flowing to the output isreasonably large, the SW node at the drain of QB will besomewhat negative with respect to PGND. The LTC1705senses this voltage, inverts it and compares the sensedvoltage with a positive voltage at the IMAX pin. The IMAX pin

LTC1705

16

EXTERNAL COMPONENT SELECTION

Power MOSFETs

Getting peak efficiency out of the LTC1705 depends stronglyon the external MOSFETs used. The LTC1705 requires atleast two external MOSFETs per side—more if one ormore of the MOSFETs are paralleled to lower on-resis-tance. To work efficiently, these MOSFETs must exhibitlow RDS(ON) at 5V VGS to minimize resistive power losswhile they are conducting current. They must also havelow gate charge to minimize transition losses duringswitching. On the other hand, voltage breakdown require-ments in a typical LTC1705 circuit are pretty tame: the 6Vmaximum input voltage limits the VDS and VGS the MOSFETscan see to safe levels for most devices.

Low RDS(ON)

RDS(ON) calculations are pretty straightforward. RDS(ON) isthe resistance from the drain to the source of theMOSFETwhen the gate is fully on. Many MOSFETs haveRDS(ON) specified at 4.5V gate drive—this is the rightnumber to use in LTC1705 circuits running from a 5Vsupply. As current flows through this resistance while theMOSFET is on, it generates I2R watts of heat, where I is thecurrent flowing (usually equal to the output current) and Ris the MOSFET RDS(ON) . This heat is only generated whenthe MOSFET is on. When it is off, the current is zero and thepower lost is also zero (and the other MOSFET is busylosing power).

This lost power does two things: it subtracts from thepower available at the output, costing efficiency, and itmakes the MOSFET hotter—both bad things. The effect isworst at maximum load when the current in the MOSFETsand thus the power lost are at a maximum. LoweringRDS(ON) improves heavy load efficiency at the expense ofadditional gate charge (usually) and more cost (usually).Proper choice of MOSFET RDS(ON) becomes a trade-offbetween tolerable efficiency loss, power dissipation andcost. Note that while the lost power has a significant effecton system efficiency, it only adds up to a watt or two in atypical LTC1705 circuit, allowing the use of small, surfacemount MOSFETs without heat sinks.

Gate Charge

Gate charge is amount of charge (essentially, the numberof electrons) that the LTC1705 needs to put into the gateof an external MOSFET to turn it on. The easiest way tovisualize gate charge is to think of it as a capacitance fromthe gate pin of the MOSFET to SW (for QT) or to PGND (forQB). This capacitance is composed of MOSFET channelcharge, actual parasitic drain-source capacitance andMiller-multiplied gate-drain capacitance, but can be ap-proximated as a single capacitance from gate to source.Regardless of where the charge is going, the fact remainsthat it all has to come out of PVCC to turn the MOSFET gateon and when the MOSFET is turned back off, that chargeall ends up at ground. In the meanwhile, it travels throughthe LTC1705’s gate drivers, heating them up. More powerlost!

In this case, the power is lost in little bite-sized chunks, onechunk per switch per cycle, with the size of the chunk setby the gate charge of the MOSFET. Every time the MOSFETswitches, another chunk is lost. Clearly, the faster theclock runs, the more important gate charge becomes as aloss term. Old-fashioned switchers that ran at 20kHz couldpretty much ignore gate charge as a loss term; in the550kHz LTC1705, gate charge loss can be a significantefficiency penalty. Gate charge loss can be the dominantloss term at medium load currents, especially with largeMOSFETs. Gate charge loss is also the primary cause ofpower dissipation in the LTC1705 itself.

TG Charge Pump

There’s another nuance of MOSFET drive that the LTC1705needs to get around. The LTC1705 is designed to useN-channel MOSFETs for both QT and QB, primarily be-cause N-channel MOSFETs generally cost less and havelower RDS(ON) than similar P-channel MOSFETs. TurningQB on is simple since the source of QB is attached toPGND; the LTC1705 just switches the BG pin betweenPGND and PVCC . Driving QT is another matter. The sourceof QT is connected to SW which rises to PVCC when QT ison. To keep QT on, the LTC1705 must get TG one MOSFETVGS(ON) above PVCC . It does this by utilizing a floatingdriver with the negative lead of the driver attached to SW(the source of QT) and the PVCC lead of the driver coming

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LTC1705

17

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out separately at BOOST. An external 1µF capacitor (CCP)connected between SW and BOOST (Figure 2) suppliespower to BOOST when SW is high and recharges itselfthrough DCP when SW is low. This simple charge pumpkeeps the TG driver alive even as it swings well abovePVCC. The value of the bootstrap capacitor CCP needs tobe at least 100 times that of the total “effective” gatecapacitance of the topside MOSFET(s). For very largeexternal MOSFETs (or multiple MOSFETs in parallel), CCPmay need to be increased beyond the 1µF value.

Input Supply

The BiCMOS process that allows the LTC1705 to includelarge MOSFET drivers on-chip also limits the maximuminput voltage to 6V. This limits the practical maximuminput supply to a loosely regulated 5V rail. The LTC1705operates properly with input supplies down to about 3.3V,so a typical 3.3V supply can also be used if the externalMOSFETs are appropriately chosen (see the PowerMOSFETs section).

At the same time, the input supply needs to supply severalamps of current without excessive voltage drop. The inputsupply must have regulation adequate to prevent suddenload changes from causing the LTC1705 input voltage todip. In typical applications where the LTC1705 is generat-ing a secondary low voltage logic supply, all of these inputconditions are met by the main system logic supply whenfortified with an input bypass capacitor.

Input Bypass Capacitor

A typical LTC1705 circuit running from a 5V logic supplymight provide 1.6V at 15A at its core output. 5V to 1.6Vimplies a duty cycle of 32%, which means QTC is on 32%of each switching cycle. During QTC’s on-time, the currentdrawn from the input equals the load current and during therest of the cycle, the current drawn from the input is nearzero. This 0A to 15A, 32% duty cycle pulse train adds up to7ARMS at the input. At 550kHz, switching cycles last about1.8µs—most system logic supplies have no hope of regu-lating output current with that kind of speed. A local inputbypass capacitor is required to make up the difference andprevent the input supply from dropping drastically whenQTC kicks on. This capacitor is usually chosen for RMSripple current capability and ESR as well as value. The

LTC1705 I/O channel typically operates at a much smalleroutput current, hence the input bypass capacitor in anLTC1705 circuit should be chosen primarily to meet thecore output requirement.

Consider our 15A example. The input bypass capacitorgets exercised in three ways: its ESR must be low enoughto keep the initial drop as QT turns on within a reasonablevalue (100mV or so); its RMS current capability must beadequate to withstand the 7ARMS ripple current at theinput and the capacitance must be large enough to main-tain the input voltage until the input supply can make upthe difference. Generally, a capacitor that meets the firsttwo parameters will have far more capacitance than isrequired to keep capacitance-based droop under control.In our example, we need 0.006Ω ESR to keep the inputdrop under 100mV with a 15A current step and 7ARMSripple current capacity to avoid overheating the capacitor.These requirements can be met with multiple low ESRtantalum or electrolytic capacitors in parallel or with alarge monolithic ceramic capacitor.

Tantalum capacitors are a popular choice as input capaci-tors for LTC1705 applications, but they deserve a specialcaution here. Generic tantalum capacitors have a destruc-tive failure mechanism if they are subjected to large RMScurrents (like those seen at the input of a LTC1705). Atsome random time after they are turned on, they can blowup for no apparent reason. The capacitor manufacturersare aware of this and sell special “surge tested” tantalumcapacitors specifically designed for use with switchingregulators. When choosing a tantalum input capacitor,make sure that it is rated to carry the RMS current that theLTC1705 will draw. If the data sheet doesn’t give an RMScurrent rating, chances are the capacitor isn’t surge tested.Don’t use it!

Output Bypass Capacitor

The output bypass capacitor has quite different require-ments from the input capacitor. The ripple current at theoutput of a buck regulator like the LTC1705 is much lowerthan at the input, due to the fact that the inductor currentis constantly flowing at the output. The primary concern atthe output is capacitor ESR. Fast load current transitionsat the output appear as voltage across the ESR of the

LTC1705

18

output bypass capacitor until the feedback loop in theLTC1705 can change the inductor current to match thenew load current value. This ESR step at the output is oftenthe single largest budget item in the load regulationcalculation. As an example, our hypothetical 1.6V, 15Aswitcher with a 0.006Ω ESR output capacitor wouldexperience a 90mV step at the output with a 0A to 15A loadstep—a 5.6% output change!

Usually the solution is to parallel several capacitors at theoutput. For example, to keep the transient response in sideof 3.5% with the previous design, we’d need an outputESR better than 0.004Ω. This can be met with six 0.025Ω,180µF special polymer capacitors in parallel.

Inductor

The inductor in a typical LTC1705 circuit is chosen prima-rily for value and saturation current. The inductor valuesets the ripple current, which is commonly chosen be-tween 20% to 40% of the anticipated full load current.Ripple current is set by:

It V

LRIPPLEON QB OUT= ( )( )

In our 1.6V, 15A example, we’d set the ripple to 20% of15A or 3A and the inductor value would be:

Lt V

Is VA

H

with tV

VkHz s

ON QB OUT

RIPPLE

ON QB

= = µ = µ

= −

= µ

( )

( )

( ) ( . )( . ).

./ .

1 2 1 63

0 67

11 65

550 1 2

The inductor must not saturate at the expected peakcurrent. In this case, if the current limit was set to 22.5A,the inductor should be rated to withstand 22.5A + (0.5 •IRIPPLE) or 24A without saturating.

FEEDBACK LOOP/COMPENSATION

Feedback Loop Types

In a typical LTC1705 circuit, the feedback loop consists ofthe modulator, the external inductor, the output capacitor

and the feedback amplifier with its compensation network.All of these components affect loop behavior and must beaccounted for in the loop compensation. The modulatorconsists of the internal PWM generator, the output MOSFETdrivers and the external MOSFETs themselves. From afeedback loop point of view, it looks like a linear voltagetransfer function from COMP to SW and has a gain roughlyequal to the input voltage. It has fairly benign AC behaviorat typical loop compensation frequencies with significantphase shift appearing at half the switching frequency.

The external inductor/output capacitor combination makesa more significant contribution to loop behavior. Thesecomponents cause a second order LC roll off at the output,with the attendant 180° phase shift. This rolloff is whatfilters the PWM waveform, resulting in the desired DCoutput voltage, but the phase shift complicates the loopcompensation if the gain is still higher than unity at thepole frequency. Eventually (usually well above the LC polefrequency), the reactance of the output capacitor willapproach its ESR and the rolloff due to the capacitor willstop, leaving 6dB/octave and 90° of phase shift (Figure 5).

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GAIN

(dB)

1705 F05

AV

0

PHASE

–6dB/OCT

–12dB/OCT

GAIN

PHASE (DEG)

FREQ

–90

–180

–270

–360

Figure 5. Transfer Function of Buck Modulator

So far, the AC response of the loop is pretty well out of theuser’s control. The modulator is a fundamental piece of theLTC1705 design and the external L and C are usuallychosen based on the regulation and load current require-ments without considering the AC loop response. Thefeedback amplifier, on the other hand, gives us a handlewith which to adjust the AC response. The goal is to have180° phase shift at DC (so the loop regulates) and some-thing less than 360° phase shift at the point that the loop

LTC1705

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gain falls to 0dB. The simplest strategy is to set up thefeedback amplifier as an inverting integrator, with the 0dBfrequency lower than the LC pole (Figure 6). This “Type 1”configuration is stable but transient response is less thanexceptional if the LC pole is at a low frequency.

Figure 7 shows an improved “Type 2” circuit that uses anadditional pole-zero pair to temporarily remove 90° ofphase shift. This allows the loop to remain stable with 90°more phase shift in the LC section, provided the loopreaches 0dB gain near the center of the phase “bump.”Type 2 loops work well in systems where the ESR zero inthe LC roll-off happens close to the LC pole, limiting thetotal phase shift due to the LC. The additional phasecompensation in the feedback amplifier allows the 0dBpoint to be at or above the LC pole frequency, improvingloop bandwidth substantially over a simple Type 1 loop. Ithas limited ability to compensate for LC combinationswhere low capacitor ESR keeps the phase shift near 180°for an extended frequency range. LTC1705 circuits usingconventional switching grade electrolytic output capaci-tors can often get acceptable phase margin with Type 2compensation.

GAIN

(dB)

1705 F07

0

PHASE

–6dB/OCT

–6dB/OCTGAIN

PHASE (DEG)

FREQ

–90

–180

–270

–360

RB

VREF

R1

R2

FB

C2

IN

OUT

+

–

C1

GAIN

(dB)

1705 F08

0

PHASE

–6dB/OCT

+6dB/OCT –6dB/OCTGAIN

PHASE (DEG)

FREQ

–90

–180

–270

–360

RB

VREF

R1

R2

FB

C2IN

OUT

+

–

C1C3

R3

GAIN

(dB)

1705 F06

0

PHASE

–6dB/OCT

GAIN

PHASE (DEG)

FREQ

–90

–180

–270

–360

RB

R1FB

C1IN

OUT

+

–

VREF

Figure 6. Type 1 Schematic and Transfer Function

Figure 7. Type 2 Schematic and Transfer Function

Figure 8. Type 3 Schematic and Transfer Function

“Type 3” loops (Figure 8) use two poles and two zeros toobtain a 180° phase boost in the middle of the frequencyband. A properly designed Type 3 circuit can maintainacceptable loop stability even when low output capacitorESR causes the LC section to approach 180° phase shiftwell above the initial LC roll-off. As with a Type 2 circuit,the loop should cross through 0dB in the middle of thephase bump to maximize phase margin. Many LTC1705circuits using low ESR tantalum or OS-CON output capaci-tors need Type 3 compensation to obtain acceptable phasemargin with a high bandwidth feedback loop.

Feedback Component Selection

Selecting the R and C values for a typical Type 2 or Type 3loop is a nontrivial task. The applications shown in thisdata sheet show typical values, optimized for the powercomponents shown. They should give acceptable perfor-mance with similar power components, but can be way offif even one major power component is changed signifi-cantly. Applications that require optimized transient re-sponse will need to recalculate the compensation valuesspecifically for the circuit in question. The underlyingmathematics are complex, but the component values canbe calculated in a straightforward manner if we know thegain and phase of the modulator at the crossover fre-quency.

Modulator gain and phase can be measured directly froma breadboard or can be simulated if the appropriateparasitic values are known. Measurement will give moreaccurate results, but simulation can often get close enoughto give a working system. To measure the modulator gainand phase directly, wire up a breadboard with an LTC1705

LTC1705

20

and the actual MOSFETs, inductor and input and outputcapacitors that the final design will use. This breadboardshould use appropriate construction techniques for highspeed analog circuitry: bypass capacitors located close tothe LTC1705, no long wires connecting components,appropriately sized ground returns, etc. Wire the feedbackamplifier as a simple Type 1 loop, with a 10k resistor fromVOUT to FB and a 0.1µF feedback capacitor from COMP toFB. Choose the bias resistor (RB) as required to set thedesired output voltage. Disconnect RB from ground andconnect it to a signal generator or to the source output ofa network analyzer (Figure 9) to inject a test signal into theloop. Measure the gain and phase from the COMP pin tothe output node at the positive terminal of the outputcapacitor. Make sure the analyzer’s input is AC coupled sothat the DC voltages present at both the COMP and VOUTnodes don’t corrupt the measurements or damage theanalyzer.

*1705 modulator gain/phase*2000 Linear Technology*this file written to run with PSpice 8.0*may require modifications for otherSPICE simulators

*MOSFETsrfet mod sw 0.02 ;MOSFET rdson

*inductorlext sw out1 1u ;inductor valuerl out1 out 0.005 ;inductor series R

*output capcout out out2 1000u ;capacitor valueresr out2 0 0.01 ;capacitor ESR

*1705 internalsemod mod 0 comp 0 5 ;3.3 for 3.3V supplyvstim comp 0 0 ac 1 ;ac stimulus.ac dec 100 1k 1meg.probe.end

With the gain/phase plot in hand, a loop crossover fre-quency can be chosen. Usually the curves look somethinglike Figure 5. Choose the crossover frequency in the risingor flat parts of the phase curve, beyond the external LCpoles. Frequencies between 10kHz and 50kHz usuallywork well. Note the gain (GAIN, in dB) and phase (PHASE,in degrees) at this point. The desired feedback amplifiergain will be -GAIN to make the loop gain at 0dB at thisfrequency. Now calculate the needed phase boost, assum-ing 60° as a target phase margin:

BOOST = – (PHASE + 30°)

If the required BOOST is less than 60°, a Type 2 loop canbe used successfully, saving two external components.BOOST values greater than 60° usually require Type 3loops for satisfactory performance.

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Figure 9. Modulator Gain/Phase Measurement Set Up

BOOST1µF

0.1µF

MBR0530T

TG

SW

BG

PGND

PVCC

GND

VCC

10Ω

AC SOURCEFROM

ANALYZER

LTC1705

10µF

QB

L

+

COUT

1705 F09

VOUT TOANALYZER

VCOMP TOANALYZER

RB

5V

+RUN/SS NC

QT

FB

COMP

10k

If breadboard measurement is not practical, a SPICEsimulation can be used to generate approximate gain/phase curves. Plug the expected capacitor, inductor andMOSFET values into the following SPICE deck and gener-ate an AC plot of V(VOUT )/V(COMP) in dB and phase ofVOUT in degrees. Refer to your SPICE manual for details ofhow to generate this plot.

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Finally, choose a convenient resistor value for R1 (10k isusually a good value). Now calculate the remaining values:

(K is a constant used in the calculations)

f = chosen crossover frequency

G = 10(GAIN/20) (this converts GAIN in dB to G inabsolute gain)

TYPE 2 Loop:

K TanBOOST

CfGKR

C C K

RKfC

RV R

V VB

REF

OUT REF

= + °

=

= −( )=

=−

245

21

2 11 2 1

22 1

1

2π

π( )

TYPE 3 Loop:

K TanBOOST

CfGR

C C K

RKfC

RR

K

Cf KR

RV R

V VB

REF

OUT REF

= + °

=

= −( )=

=−

=

=−

24

45

21

2 11 2 1

22 1

311

31

2 31

π

π

π( )

CURRENT LIMIT PROGRAMMING

Programming current limit on the LTC1705 is straight-forward. The IMAX pin sets the current limit by setting themaximum allowable voltage drop across QB (the bottomMOSFET) before the current limit circuit engages. Thevoltage across QB is set by its on-resistance and thecurrent flowing in the inductor, which is the same as theoutput current. The LTC1705 current limit circuit invertsthe negative voltage across QB before comparing it withthe voltage at IMAX, allowing the current limit to be set witha positive voltage.

To set the current limit, calculate the expected voltagedrop across QB at the maximum desired current:

VPROG = (ILIMIT) (RDS(ON))

ILIMIT should be chosen to be quite a bit higher than theexpected operating current, to allow for MOSFET RDS(ON)changes with temperature. Setting ILIMIT to 150% of themaximum normal operating current is usually safe and willadequately protect the power components if they arechosen properly. Note that the ringing on the switch nodecan cause error for the current limit threshold. This factorwill change depending on the layout and the componentsused. VPROG is then programmed at the IMAX pin using theinternal 10µA pull-up and an external resistor:

RIMAX = VPROG/10µA

The resulting value of RIMAX should be checked in anactual circuit to ensure that the current circuit kicks in asexpected. MOSFET RDS(ON) specs are like horsepowerratings in automobiles and should be taken with a grain ofsalt. Circuits that use very low values for RIMAX (<10k)should be checked carefully, since small changes in RIMAXcan cause large ILIMIT changes when the switch noderinging makes up a large percentage of the total VPROGvalue. If VPROG is set too low, the LTC1705 may fail to startup.

LTC1705

22

Accuracy Trade-Offs

The VDS sensing scheme used in the LTC1705 is notparticularly accurate, primarily due to uncertainty in theRDS(ON) from MOSFET to MOSFET. A second error termarises from the ringing present at the SW pin, whichcauses the VDS to look larger than (ILOAD)(RDS(ON)) at thebeginning of QB’s on-time. These inaccuracies do notprevent the LTC1705 current limit circuit from protectingitself and the load from damaging overcurrent conditions,but they do prevent the user from setting the current limitto a tight tolerance if more than one copy of the circuit isbeing built. The 50% factor in the current setting equationabove reflects the margin necessary to ensure that thecircuit will stay out of current limit at the maximum normalload, even with a hot MOSFET that is running quite a bithigher than its RDS(ON) spec.

VCLK LINEAR REGULATOR

The LTC1705 monolithic LDO linear regulator is easy touse. Input and output supply bypass capacitors are theonly two external components required for this LDO. TheVINCLK pin powers up the regulator and an internal P-channelMOS transistor sources at least 150mA of current at afixed output voltage of 2.5V. This device is short-circuitprotected and includes thermal shutdown to turn off allthree regulator outputs should the junction temperatureexceed about 155°C.

The circuit design in the LTC1705 requires the use of anoutput capacitor as part of the frequency compensation. Aminimum output capacitor of 2.2µF and ESR larger than100mΩ is recommended to prevent oscillations. Largervalues of output capacitance decrease the peak deviationsand provide improved transient response for large loadcurrent changes. Many different types of capacitors areavailable and have widely varying characteristics. Thesecapacitors differ in capacitor tolerance (sometimes rang-ing up to ±100%), equivalent series resistance, equivalentseries inductance and capacitance temperature coeffi-cient. In a typical operating condition, a 10µF solid tanta-lum at the VOUTCLK pin ensures stability. The AVXTPSD106M035R0300 or equivalent works well in thisapplication.

OPTIMIZING PERFORMANCE

2-Step Conversion

The LTC1705 is ideally suited for use in 2-step conversionsystems. 2-step systems use a primary regulator to con-vert the input power source (batteries or AC line voltage)to an intermediate supply voltage, often 5V. The LTC1705then converts the intermediate voltage to the lower volt-age, high current supplies required by the system. Com-pared to a 1-step converter that converts a high inputvoltage directly to a very low output voltage, the 2-stepconverter exhibits superior transient response, smallercomponent size and equivalent efficiency. Thermal man-agement and layout complexity are also improved with a2-step approach.

A typical notebook computer supply might use a 4-cell Li-Ion battery pack as an input supply with a 15V nominalterminal voltage. The logic circuits require 5V/3A and3.3V/5A to power system board logic and 2.5V/0.15A,1.5V/2A and 1.3V/15A to power the CPU. A typical 2-stepconversion system would use a step-down switcher (per-haps an LTC1628 or two LTC1625s) to convert 15V to 5Vand another to convert 15V to 3.3V (Figure 10). The 3.3Vinput supply can power the 1.3V output at the LTC1705core channel and the 2.5V LDO. The 5V input supply canpower the 1.5V I/O channel. The corresponding 1-stepsystem would use four similar step-down switchers plusan LDO, each switcher using 15V as the input supply andgenerating one of the four output voltages.

Clearly, the 5V and 3.3V sections of the two schemes areequivalent. The 2-step system draws additional powerfrom the 5V and 3.3V outputs, but the regulation tech-niques and trade-offs at these outputs are similar. Thedifference lies in the way the 1.5V and 1.3V supplies aregenerated. For example, the 2-step system converts 3.3Vto 1.3V with a 39% duty cycle. During the QT on-time, thevoltage across the inductor is 2V and during the QB on-time, the voltage is 1.3V, giving roughly symmetricaltransient response to positive and negative load steps. The2V maximum voltage across the inductor allows the use ofa small 0.47µH inductor while keeping ripple current to 3A(20% of the 15A maximum load). By contrast, the 1-step

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converter is converting 15V to 1.3V, requiring just a 9%duty cycle. Inductor voltages are now 13.7V when QT is onand 1.3V when QB is on, giving vastly different di/dt valuesand correspondingly skewed transient response with posi-tive and negative current steps. The narrow 9% duty cycleusually requires a lower switching frequency, which inturn requires a higher value inductor and larger outputcapacitor. Parasitic losses due to the large voltage swingat the source of QT cost efficiency, eliminating any advan-tage the 1-step conversion might have had.

Note that power dissipation in the LTC1705 portion of a2-step circuit is lower than it would be in a typical 1-stepconverter, even in cases where the 1-step converter hashigher total efficiency than the 2-step system. In a typicalmicroprocessor core supply regulator, for example, theregulator is usually located right next to the CPU. In a1-step design, all of the power dissipated by the core

regulator is right there next to the hot CPU, aggravatingthermal management. In a 2-step LTC1705 design, asignificant percentage of the power lost in the core regu-lation system happens in the 5V or 3.3V supply, which isusually away from the CPU. The power lost to heat in theLTC1705 section of the system is relatively low, minimiz-ing the heat near the CPU.

Additionally, with a 1-step converter, the high input batteryvoltage requires the MOSFET to operate at high voltagelevels. This imposes stringent requirements on theMOSFETs selection. Most of the MOSFETs that meet thehigh voltage and high current requirements are expensiveand bulky. This makes for an awkward power supplydesign, especially in portable applications. The high inputvoltage also necessitates higher gate drive, which aggra-vate switching losses.

Figure 10. 2-Step Conversion Block Diagram

2-STEP CONVERSION OFFERS• BETTER TRANSIENT RESPONSE• SMALLER COMPONENT SIZE• BETTER THERMAL MANAGEMENT• LOWER VOLTAGE REQUIREMENT FOR MOSFETS• SMALLER SWITCHING LOSS• EQUIVALENT EFFICIENCY

LTC1628*

5V/3A LOGIC SUPPLY

1.5V/2A CPU I/O SUPPLY

1.3V/15A CPU CORE SUPPLY

3.3V/5A LOGIC SUPPLY

2.5V/0.15A CPU CLOCK SUPPLY

*OR TWO LTC1625s

I/O

CORE

LTC1705CPU SUPPLY CONTROLLER

LDO

1705 F10

LTC1705

24

2-Step Efficiency Calculation

Calculating the efficiency of a 2-step converter systeminvolves some subtleties. Simply multiplying the effi-ciency of the primary 5V or 3.3V supply by the efficiencyof the 1.5V or 1.3V supply under estimates the actualefficiency, since a significant fraction of the total power isdrawn from the 3.3V and 5V rails in a typical system. Thecorrect way to calculate system efficiency is to calculatethe power lost in each stage of the converter and divide thetotal output power from all outputs by the sum of theoutput power plus the power lost:

EfficiencyTotal Output Power

Total Output Power Total Output Lost

=

+( )100%

In our example 2-step system, the total output power is:

Total Output Power =

15W + 16.5W + 0.375W + 3W + 19.5W = 54.375W

(corresponding to 5V, 3.3V, 2.5V, 1.5V and1.3V output voltages)

Assuming the LTC1705 provides 90% efficiency at thecore and I/O channels, and 75% efficiency at the LDO, theadditional loads on the 5V and 3.3V supplies are:

1.3V: 19.5W/90% =21.67W ⇒ 6.6A from 3.3V

1.5V: 3W/90% =3.3W ⇒ 0.66A from 5V

2.5V: 0.375W/75% =0.5W ⇒ 0.152A from 3.3V

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If the 5V and 3.3V supplies are each 94% efficient, thepower lost in each supply is:

1.3V: 21.67W – 19.5W = 2.17W

1.5V: 3.3W – 3W = 0.3W

2.5V: 0.5W – 0.375W = 0.125W

3.3V: 16.5W + 3.3V(6.6A + 0.152A) = 38.78W Load(38.78W/94%) – 38.78W = 2.48W Lost

5V: 15W + 5V(0.66A) = 18.3W Load(18.3W/94%) – 18.3W = 1.17W Lost

Total Loss = 6.25W

Total System Efficiency =54.375W/(54.375W + 6.25W) = 89.7%

Maximizing High Load Current Efficiency

Efficiency at high load currents is primarily controlled bythe resistance of the components in the power path (QT,QB, LEXT ) and power lost in the gate drive circuits due toMOSFET gate charge. Maximizing efficiency in this regionof operation is as simple as minimizing these terms.

The behavior of the load over time affects the efficiencystrategy. Parasitic resistances in the MOSFETs and theinductor set the maximum output current the circuit cansupply without burning up. A typical efficiency curveshows that peak efficiency occurs near 30% of this maxi-mum current. If the load current will vary around theefficiency peak and will spend relatively little time at themaximum load, choosing components so that the averageload is at the efficiency peak is a good idea. This puts themaximum load well beyond the efficiency peak, but usu-ally gives the greatest system efficiency over time, whichtranslates to the longest run time in a battery-poweredsystem. If the load is expected to be relatively constant atthe maximum level, the components should be chosen sothat this load lands at the peak efficiency point, well belowthe maximum possible output of the converter.

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25

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REGULATION OVER COMPONENT TOLERANCE/TEMPERATURE

DC Regulation Accuracy

The LTC1705 initial DC output accuracy depends mainlyon internal reference accuracy, op amp offset and internalor external resistor accuracy. Two LTC1705 specs comeinto play: VSENSEC voltage and feedback voltage line regu-lation. The VSENSEC voltage spec is within ±1.25% for allVID codes over the full temperature range, which encom-passes reference accuracy, error amplifier offset and theinput resistor divider mismatch. The feedback voltage lineregulation spec adds an additional 0.1%/V term thataccounts for change in reference output with change ininput supply voltage. With a 5V supply, the errors contrib-uted by the LTC1705 itself add up to less than 1.5% DCerror at the output.

At the I/O side, the output voltage setting resistors (R1 andRB in Figure 3) are the other major contributor to DC error.At a typical 1.xV output voltage, the resistors are ofroughly the same value, which tends to halve their errorterms, improving accuracy. Still, using 1% resistors forR1 and RB will add 1% to the total output error budget.Using 0.1% resistors in just those two positions can nearlyhalve the DC output error for very little additional cost.

Load Regulation

Load regulation is affected by feedback amplifier gain andexternal ground drops in the feedback path. A full-rangeload step might require a 10% duty cycle change to keepthe output constant, requiring the COMP pin to moveabout 100mV. With amplifier gain at 85dB, this adds up toonly a 10µV shift at FB, negligible compared to the refer-ence accuracy terms.

External ground drops aren’t so negligible. The LTC1705can sense the positive end of the output voltage byattaching the feedback resistor directly at the load, but itcannot do the same with the ground lead. Just 0.001Ω ofresistance in the ground lead at 15A load will cause a 15mVerror in the output voltage—as much as all the other DCerrors put together. Proper layout becomes essential to

achieving optimum load regulation from the LTC1705. Aproperly laid out LTC1705 circuit should move not morethan one to two millivolts at the output from zero to fullload.

Transient Response

Transient response is the other half of the regulationequation. The LTC1705 can keep the DC output voltageconstant to within 1% when averaged over hundreds ofcycles. Over just a few cycles, however, the externalcomponents conspire to limit the speed that the outputcan move. Consider our typical 5V to 1.5V circuit, sub-jected to a 1A to 5A load transient. Initially, the loop is inregulation and the DC current in the output capacitor iszero. Suddenly, an extra 4A start flowing out of the outputcapacitor while the inductor is still supplying only 1A. Thissudden change will generate a (4A)(RESR )voltage step atthe output; with a typical 0.015Ω output capacitor ESR,this is a 60mV or 4% (for a 1.5V output voltage) step at theoutput!

Very quickly, the feedback loop will realize that somethinghas changed and will move at the bandwidth allowed bythe external compensation network towards a new dutycycle. If the bandwidth is set to 50kHz, the COMP pin willget to 60% of the way to 90% duty cycle in 3µs. Now theinductor is seeing 3.5V across itself for a large portion ofthe cycle and its current will increase from 1A at a rate setby di/dt = V/L. If the inductor value is 0.5µH, the peak di/dtwill be 3.5V/0.5µH or 7A/µs. Sometime in the next fewmicro-seconds after the switch cycle begins, the inductorcurrent will have risen to the 5A level of the load currentand the output voltage will stop dropping. At this point, theinductor current will rise somewhat above the level of theoutput current to replenish the charge lost from the outputcapacitor during the load transient. During the next coupleof cycles, the MIN comparator may trip on and off,preventing the output from falling below its -5% thresholduntil the time constant of the compensation loop runs outand the main feedback amplifier regains control. With aproperly compensated loop, the entire recovery time willbe inside of 10µs.

LTC1705

26

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Figure 11. Transient Load Generator

Most loads care only about the maximum deviation fromideal, which occurs somewhere in the first two cycles afterthe load step hits. During this time, the output capacitordoes all the work until the inductor and control loop regaincontrol. The initial drop (or rise if the load steps down) isentirely controlled by the ESR of the capacitor and amountsto most of the total voltage drop. To minimize this drop,reduce the ESR as much as possible by choosing low ESRcapacitors and/or paralleling multiple capacitors at theoutput. The capacitance value accounts for the rest of thevoltage drop until the inductor current rises. With mostoutput capacitors, several devices paralleled to get theESR down will have so much capacitance that this dropterm is negligible. Ceramic capacitors are an exception; asmall ceramic capacitor can have suitably low ESR withrelatively small values of capacitance, making this seconddrop term significant.

Optimizing Loop Compensation

Loop compensation has a fundamental impact on tran-sient recovery time, the time it takes the LTC1705 torecover after the output voltage has dropped due to outputcapacitor ESR. Optimizing loop compensation entailsmaintaining the highest possible loop bandwidth whileensuring loop stability. The feedback component selectionsection describes in detail the techniques used to designan optimized Type 3 feedback loop, appropriate for mostLTC1705 systems.

Measurement Techniques

Measuring transient response presents a challenge in tworespects: obtaining an accurate measurement and gener-ating a suitable transient to use to test the circuit. Outputmeasurements should be taken with a scope probe di-rectly across the output capacitor. Proper high frequencyprobing techniques should be used. In particular, don’tuse the 6" ground lead that comes with the probe! Use anadapter that fits on the tip of the probe and has a shortground clip to ensure that inductance in the ground path

LTC1705 VOUT

IRFZ44 OREQUIVALENT

RLOAD

50Ω0V TO 10V100Hz, 5%

DUTY CYCLE

LOCATE CLOSE TO THE OUTPUT1705 F11

PULSEGENERATOR

doesn’t cause a bigger spike than the transient signalbeing measured. Conveniently, the typical probe tip groundclip is spaced just right to span the leads of a typical outputcapacitor.

Now that we know how to measure the signal, we need tohave something to measure. The ideal situation is to usethe actual load for the test and switch it on and off whilewatching the output. If this isn’t convenient, a current stepgenerator is needed. This generator needs to be able toturn on and off in nanoseconds to simulate a typicalswitching logic load, so stray inductance and long clipleads between the LTC1705 and the transient generatormust be minimized.

Figure 11 shows an example of a simple transient genera-tor. Be sure to use a noninductive resistor as the loadelement—many power resistors use an inductive spiralpattern and are not suitable for use here. A simple solutionis to take ten 1/4W film resistors and wire them in parallelto get the desired value. This gives a noninductive resistiveload which can dissipate 2.5W continuously or 50W ifpulsed with a 5% duty cycle, enough for most LTC1705circuits. Solder the MOSFET and the resistor(s) as close tothe output of the LTC1705 circuit as possible and set upthe signal generator to pulse at a 100Hz rate with a 5% dutycycle. This pulses the LTC1705 with 500µs transients10msapart, adequate for viewing the entire transient recoverytime for both positive and negative transitions while keep-ing the load resistor cool.

LTC1705

27

PACKAGE DESCRIPTIO

U

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

GN Package28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

0.386 – 0.393*(9.804 – 9.982)

GN28 (SSOP) 1098

* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASHSHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEADFLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

1 2 3 4 5 6 7 8 9 10 11 12

0.229 – 0.244(5.817 – 6.198)

0.150 – 0.157**(3.810 – 3.988)

202122232425262728 19 18 17

13 14

1615

0.016 – 0.050(0.406 – 1.270)

0.015 ± 0.004(0.38 ± 0.10)

× 45°

0° – 8° TYP0.0075 – 0.0098(0.191 – 0.249)

0.053 – 0.069(1.351 – 1.748)

0.008 – 0.012(0.203 – 0.305)

0.004 – 0.009(0.102 – 0.249)

0.0250(0.635)

BSC

0.033(0.838)

REF

LTC1705

28 Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 FAX: (408) 434-0507 www.linear.com LINEAR TECHNOLOGY CORPORATION 2001

1705fa LT/TP 0801 1.5K REV A • PRINTED IN USA

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ITH1

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