M.Tech DEGREE I SEMSTER EXAMINATION IN ELECTRONICS

(SIGNAL PROCESSING) – MODEL PAPER – 2011

SP102 – ADVANCED DIGITAL SYSTEM DESIGN

1. A. (a) Briefly explain about bus oriented structures. (3)

(b) Design and implement a Binary to Excess-3 circuit (3)

(c) Draw the CMOS realization of AOI and OAI gates. (4)

OR

B. (a) Design and implement a Grey code driven 7 segment display circuitry. (6)

(b) Draw the circuit of tri-state buffer and explain its working. (4)

2. A. (a) Design and implement a Moore machine which detects non-overlapping sequence

1001. (6)

(b) Explain the steps used for designing a ‘clocked synchronous state machine’. (4)

OR

B. (a) Explain the difference between Mealy and Moore machines using suitable examples

(5)

(b) Briefly explain the various state reduction methods. (5)

3. A. (a) Compare the features of FPGA’s and CPLD. (5)

(b) Realize a half adder using PLA. (5)

OR

B. (a) Explain the functional block diagram of XILINX FPGA. (6)

(b) Briefly explain about PLA minimization with an example. (4)

4. A. (a) Explain about hazard free design using a suitable example. (6)

(b) Explain the various aspects of an SM chart. (4)

OR

B. (a) Find a race-free assignment for the state machine given in the following table and draw

the augmented state table.

Present

state

Next state

y1y2

00 01 11 10

A A A D D

B B A B C

C A C D C

D D C D D

(6)

(b) How to determine the next state and output equations for a state machine by tracing link

paths on its SM chart? (4)

5. A. (a) State and explain Shannon’s Expansion theorem. (5)

(b) Briefly explain about Threshold logic. (5)

OR

B. (a) Apply CRMT method to the following functions:

F(a, b, c, d) = ∑m (1,4,7,11,13,14) (5)

(b) Briefly explain about Consensus Theorem and Reed Muller Expansion. (5)