madeo - a cad tool for reconfigurable hardware
TRANSCRIPT
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Loïc Lagadec
Lab-STICC Architectures&Systèmes
Université de Bretagne Occidentale, BREST
Madeo: a CAD Tool for
Reconfigurable Hardware
L. Lagadec - Lab-STICC CNRS UMR 3192 -
Université de Bretagne Occidentale
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Our OO Expert's world
We are all familiar with
Code refactoring
Code reuse
Agile development
Ability to postpone design choices
Fast development
Portability through Virtual Machines2
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Out =
i1 + i2
What about real Machines?
Micro processors
Co-processors
Dedicated instructions set
Dynamic instructions set ?
Reconfigurable hardware is an option for that
i1i2
out
m P
Circuit
Target 3
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Reconfigurable Architectures (RA)
Circuits
Customizable
Partial reconfiguration
Dynamic reconfiguration
Performances (in between HW and SW)
Flexibility (in between SW and HW)
“Low” Cost 4
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Targets
FPGAs (several vendors, eg. Xilinx)
Complexity issue
Application IP composition
Reconfigurable Datapath (e.g. XPP)
eFPGAs (M2000, Mentra, ...)
Rsocs (e.g Morpheus project) : RA IP composition
complexity
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Requires efficient tools
Programming these circuits is a complex task
Tools are linked to a target (low reuse)
Application description “fails” to exploit flexibility
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My talk adresses
Applying OO methodology to reconfigurable hardware
Adapt to new RA “retargetable compiler”
Produce Circuits from HL code
10 years experience report
Results + Lessons learned
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Origin: Compatibility issues
Need to conform to
standards tools/formats
vendor's private (unstable) formats
While preserving a stable API
Solution: Build up a framework
Model : Reconfigurable Architecture (RA)
Tools : Editing/Programming RA
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Tools for HL Code to circuit mapping
Our contribution
Floorplaning
HL Code
RTL Code
Place & Route
Validation
Bitstream generation
Execution control
SOFT
HARD
Covers more architectures: model's improvements
Covers control structures and libraries
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First architecture
XC6200 from Xilinx
Configuration as RAM
Very exiting (late 90s)
Export
Program &Manage execution
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Dedicated Tool
A circuit is an object
Registers = instance variables
IOs = accessors
Mmap: configuration main memory
Fine resource allocation
Step by Step execution control
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Improvements
Coverage
Learning by doing (reverse is costly)
Model re-design
Wire vs Channel
Directional vs Bi directional resources
Hierarchical composition
...
Model instanciation (DSL)
Design Space Exploration (DSE)
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Results
Architectures
Commercial architecture (VIRTEX) with back end vendor's tools control
Reconfigurable datapaths (STMicro)
Generic parameterized architectures (DSE)
Architecture research oriented support (fast prototyping)
Two issues
Compiance to standard
High Level layer15
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Snaphots
Interfacing the vendor API
BitStreamstructure
(e.g K.I.T)
System Use
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ST as application spec
Goal: Fully exploit RA adaptability
How: AST from Vw code
Typing
Compilation steps (standard + specific)
+ RTL (application) generation
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Tool Snapshot
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Example:Small FP multiplier
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Example:Small FP multiplier
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Example:Changing optimization policy
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Example: Changing target RA
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Pro/Cons
Domain oriented tailoring (ex. Galois field based typing) for free
Logic based simulator hence SW/HW sharing API
Complexity bounded
Restricted to simple control structures (ifTrue:, ...) and loop unrolling
Still relies on third parties logic minimizers 23
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Complexity issue
Well known design patterns
Soft macros (tiling, ...)
Compositions (divide and conquer)
Designing architectures (control structures through structural patterns)
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Model/Interchange issues
Standart compliance (e.g. EDIF)
Exchange issues:
Ensure portability
Prevent semantic losses
Allow cross-blocks optimizations
Meta modeling: Platypus (A. Plantec)
STEP/EXPRESS
Visitors (encoding/decoding, repository, rules checking)
+ Visitors (Domain specific e.g. Scheduling)25
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Flow
Platypus tool
CDFG design
CDFG EXPRESS
model
Tool X
Tool YHLL CDFG API (Java)
CDFG instances(STEP files)
CDFG Checker
Madeo+ synthesis tool
CDFG Use
Target 3
Specific Assembly code
Target 2
C like code
Target 1
EDIF
Target architecture description
HLL CDFG API (Smalltalk)
ENTITY HierarchicalNode SUBTYPE OF (Node);
localVariables : LIST OFAbstractData;
subOperators : LIST [1 : ?] OF Node;
END_ENTITY;
ENTITY AccumulatorNode SUBTYPE OF(HierarchicalNode);
init : AbstractData; --”AccumulatorNode.init” the initial value we start accumulating from.
toBeAccumulated: AbstractData;
DERIVE
cumulatedArguments : LIST OFAbstractData := subOperators [ SIZEOF (subOperators)].outputs;
WHERE
toBeAccumulatedSource: SIZEOF ( cumulatedArguments )=1;
typeCompat: cumulatedArguments[1].type = init.type;
END_ENTITY;
APPLICATION
APPLICATION
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Validation
Key issue
Requires standard tools (Again !)
But we want also Sunit capabilities
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Combine both
Use external tools as characterization tests for your own tools
Once yours are validated, use them
Multi level simulation (System, Architecture, Circuit)
Add probes/break points
Keep the double link between HL code and circuit
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Conclusion
Model target (FPGA, eFPGA, ...)
Generate application-code
HL code hardware execution
Open to third parties
Used in several projects (RNTL, PRIR, FP6, ...)
Benefits from OO
Provides OO-like
Nice candidate to RA based VM implementation tool29
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Lessons learned
Split layers into separate tools with different names
Use Meta Modeling (cost killer)
Evolution
Interchange
Documentation
Export code and always target your partner's reference language (your partner is your client)
You may like UGI, partners like command line mode (seaside 's fine for remote access and easy demo)
Don't show partners you work faster than they do
Keeping your cooking tips secrets is not a problem 30
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On going tasks
Platypus + STEP/EXPRESS for FPGA modeling
DSL generation (ExternalLanguageParser -> SmaCC
-> gen. smaCC)
Probe synthesis (hardware = speed up)
Nano devices (e.g. NASICs from Umass)
Virtualize FPGAs
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