mahesh wagh intel corporation member, pcie protocol workgroup

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PCI Express* 2.0 Platform Implementations Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

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Page 1: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

PCI Express* 2.0Platform ImplementationsMahesh WaghIntel CorporationMember, PCIe Protocol Workgroup

Page 2: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

Today’s Topics

PCIe* Architecture Overview

PCIe 2.0 Update

Future of PCIe Architecture

Call to Action

Page 3: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

Signaling bump to 5GFLR, completion TO, etc

Address Translation Services (ATS)

Device sharing for Single/Multi-Root (SR/MR)

Performance/power-optimized interface to host

Protocol and SW extensions

New Extensions

IOV

PCIe 2.0

Today’s Focus

PCIe Architecture Overview

Page 4: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

PCIe 2.0 Update

5GT/s Speed IncreaseLink Speed Management

Link Bandwidth Notification MechanismFunction Level Reset (FLR)Access Control Services (ACS)Completion Timeout Control

Retracted: Trusted Configuration Space (TCS)

Page 5: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

PCIe 2.0 (5G)

Tight budgets remove all guard bands!

All interconnect components specified for enhanced interoperability

PCIe 1.0a: Transmitter

PCIe 1.1: PCIe 1.0a + Reference Clock

PCIe 2.0: PCIe 1.1 + Channel + Receiver

CEM specification provides electrical interoperability for system board/add-in card

Channel

Transmitter ReceiverPLL PLLTx

pinsRx

pins

Coupling caps

ReferenceClock

100MHz

Page 6: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

PCIe 2.0 LTSSM ExtensionsExtensions Explanation Benefits

Speed Negotiation Capability to upgrade or downgrade link speed

RAS (improved link uptime), dynamic link speed optimization, power savings (25%+)

Compliance Speed Programmable as well as in-band mechanism to select compliance pattern speed

Flexibility to perform compliance testing at multiple speeds with low cost

Electrical Idle Entry and Exit

Protocol changes to facilitate circuit design

Enhanced robustness, yield, power savings, ease of design (TTM)

Link Width Up-configure

Capability to increase the link width up to the initial trained link width

Power savings

Compliance Entry/Exit

Device Configuration despite link failures

High availability, enhanced robustness

Page 7: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

Link Speed Management

Default: Trains to the greatest common speed

Software can set an upper bound on the speed

Hardware can limit speed for link reliability

Hardware is permitted to change the speed autonomously

E.g.: Power management

Software can disable

New mechanism supporting software control for entering/exiting Compliance Mode

Page 8: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

Link Speed Controls

Link Capability registerMaximum Link Speed

field renamed to Supported Link Speeds

Link Status registerLink Speed field

renamed to Current Link Speed

(New) Link Control 2 register

Hardware Autonomous Speed Disable bit

Enter Compliance bitTarget Link Speed field

Page 9: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

Bandwidth Notification

Mechanism for PCIe-aware software to be notified when link bandwidth changes

E.g.: Link retrains to a lower bandwidth due to reliability problemE.g.: Hardware-autonomous link retraining

Logically coupled with Link Speed ManagementRequired for all Root Ports and downstream Switch Ports that support wider than x1 and/or multiple link speeds

Page 10: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

BW Notification MechanismLink Capability register

Link Bandwidth Notification Capability bit

Link Control registerLink Autonomous

Bandwidth Interrupt Enable bit

Link Bandwidth Management Interrupt

Enable bitHardware Autonomous

Width Disable bitLink Status register

Link Autonomous Bandwidth Status bit

Link Bandwidth Management Status bit

Page 11: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

Function Level Reset

New type of reset

Existing resets may (but not required to) reset function internalsFLR definition requires function internal reset

SW initiated function-specific reset

RESET “FAMILY TREE”

FLRConventional

Cold / Warm(PERST#)

HotS.B.R.

Page 12: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

FLR Details

Endpoints onlyAll types: Legacy, native, integrated

Register interface simple

Implementation and effects potentially complex

Resets internal function-specific state

Not all architected registers are reset

Hardware initialized (HwInit), BIOS set, etc

F0 F1 F2PCIe EPs

FLR

Page 13: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

Access Control Services

For downstream ports and multi-function devices

New Extended Capability and Status/Mask/Severity bits in AER

Source validation Downstream ports range check Requester ID BusNum in upstream Request TLPs

Peer-to-peer controlsDetermine whether to forward directly, block, or redirect peer-to-peer requests to the RC for access validation

ACS considered for functionality defined by the Address Translation Services (ATS) specification

Page 14: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

Completion Timeout

Required: Architected Disable Bit

“Turns off” timeout

Not to be used in normal operation

Optional: Completion Timeout Programmability

Devices indicate supported ranges from the four bins defined

Two selectable ranges for each bin

4s to 64s

250ms to 4s

10ms to 250ms

50us to 10ms

Page 15: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

Future Of PCI Express Architecture

Page 16: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

Factors Driving PCIe FutureMulti-Everything!

CPUs, multi-core, operating systems

Device virtualization and sharing

Multiple graphics cards

Higher Performance

Next generation graphics, storage, networking, and fabrics

Emerging applications: Math, visualization, content processing, etc

Need for more connectivity: Flexible interconnect width/speed

Lower power

Technology Advances

Si process

High volume manufacturing

Materials

PCIe is the interconnect of choice

Page 17: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

OS+LIB/APIs

OS Bus Driver, Cfg, PM, RAS

Link

Applications SW

Device Driver

Math

Visualization

Content Proc.

Signaling Speed Upgrade

Power State Management

BW, Latency and Efficiency

Synch. and Data Exchange

Protocol

Physical

General IO

Communication

OS

PCI SW Model

Device I/F

Apps

PCIe

PCIe Architecture Evolution

Page 18: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

Call To Action

Innovate and differentiate your products with PCI Express 2.0 industry specification

Contribute to the evolution of PCI Express architecture

Visit www.pcisig.com for PCI Express specification updates

Page 19: Mahesh Wagh Intel Corporation Member, PCIe Protocol Workgroup

Additional Resources

Web Resources: www.pcisig.com

Related Sessions SYS-T311 – PCI I/O Virtualization Standards – Implementation