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Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development [email protected] 5/9/2017

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Page 1: Making RISC-V IP easy to play with & evaluate · Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development jack@sifive.com 5/9/2017

Making RISC-V IP easy to play with &evaluateJackKangVPProduct&[email protected]/9/2017

Page 2: Making RISC-V IP easy to play with & evaluate · Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development jack@sifive.com 5/9/2017

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SiFive Product Offerings: CPU IP & SoCsCommon hardware platform, Standard software, Customized features

CPU Core IP

©2017SiFive.AllRightsReserved.

ARM Cortex-M Series Replacement• 32-bit CPU• Replaces M0, M0+, M3,

M4, M23, M33• 2x Perf/Watt• Custom Extensions

ARM Cortex-A Series Replacement• 32-bit and 64-bit CPUs• Replaces A5, A7, A32,

A35, A8, A9, A53 • 2x Perf/Watt• Custom Extensions

SiFive Freedom SoCs

High performance, 64-bit multi-core SoCs• Datacenter Accelerators• Storage / SSD Controllers• Networking / Baseband

Low cost, 32-bit microcontrollers• Edge Computing (AI)• Embedded• Smart IOT• Wearables

Page 3: Making RISC-V IP easy to play with & evaluate · Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development jack@sifive.com 5/9/2017

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The Current IP Industry…

• Difficult to get information

• Even harder to get actual RTL before purchasing

• Negotiations can take 6-12+ months

• License agreements can be 100+ pages

© 2017SiFive.AllRightsReserved.

Page 4: Making RISC-V IP easy to play with & evaluate · Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development jack@sifive.com 5/9/2017

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Changing the IP Business Model – Coreplex IP

© 2017SiFive.AllRightsReserved.

Detailed informationDatasheetPower, Perf, Area

FreeNo NDANo Registration

www.sifive.com

FPGA BitstreamEvaluation RTLFreedom Studio

Free Evaluation License

Configure OnlineTransparent Pricing

7-page license agreementNo Royalty

Page 5: Making RISC-V IP easy to play with & evaluate · Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development jack@sifive.com 5/9/2017

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Documentation

© 2017SiFive.AllRightsReserved.

Page 6: Making RISC-V IP easy to play with & evaluate · Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development jack@sifive.com 5/9/2017

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Power, Performance, Area

© 2017SiFive.AllRightsReserved.

Page 7: Making RISC-V IP easy to play with & evaluate · Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development jack@sifive.com 5/9/2017

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Tools

© 2017SiFive.AllRightsReserved.

Page 8: Making RISC-V IP easy to play with & evaluate · Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development jack@sifive.com 5/9/2017

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Tools

© 2017SiFive.AllRightsReserved.

Page 9: Making RISC-V IP easy to play with & evaluate · Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development jack@sifive.com 5/9/2017

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Evaluate – FPGA Bitstreams

© 2017SiFive.AllRightsReserved.

• Prebuilt FPGA Bitstreams• Low cost $99 FPGA Dev Kit• Fast! ~65MHz

Evaluate code size, tools, CPU performance

Page 10: Making RISC-V IP easy to play with & evaluate · Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development jack@sifive.com 5/9/2017

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Evaluate – Verilog RTL

© 2017SiFive.AllRightsReserved.

• Free, Instant Access• Fully functional, synthesizable, Verilog RTL• Synthesize into your SOC• Simulate in your environment• Determine your PPA for your process node

• Evaluation License automatically sent electronically• Countersign electronically• Instant access in your Developer Dashboard

Page 11: Making RISC-V IP easy to play with & evaluate · Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development jack@sifive.com 5/9/2017

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Configure and Buy – Online

© 2017SiFive.AllRightsReserved.

Page 12: Making RISC-V IP easy to play with & evaluate · Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development jack@sifive.com 5/9/2017

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Configure and Buy - Mobile

© 2017SiFive.AllRightsReserved.

Page 13: Making RISC-V IP easy to play with & evaluate · Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development jack@sifive.com 5/9/2017

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SiFive Coreplex IP OverviewDirect replacement for alternative options

CPU Core IP

©2017SiFive.AllRightsReserved.

ARM Cortex-M Series Replacement• 32-bit CPU• Replaces M0, M0+, M3, M4, M23, M33• 2x Perf/Watt• Custom Extensions

ARM Cortex-A Series Replacement• 32-bit and 64-bit CPUs• Replaces A5, A7, A32, A35, A8, A9, A53• 2x Perf/Watt• Custom Extensions

Page 14: Making RISC-V IP easy to play with & evaluate · Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development jack@sifive.com 5/9/2017

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E31 Coreplex32-bit RISC-V. High performance embedded processing

© 2017SiFive.AllRightsReserved.

• Higher performance than Cortex M3 and Cortex M4• 1.61 DMIPs/MHz vs 1.25 DMIPs/MHz• Up to 1.5GHz in 28nm

• Very competitive area:• 0.026 mm2 (core only) in 28nm

• Smart IOT, Wearables, Embedded Microcontrollers

Page 15: Making RISC-V IP easy to play with & evaluate · Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development jack@sifive.com 5/9/2017

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E51 Coreplex64-bit Embedded Processor. 32-bit price, power, and area.

© 2017SiFive.AllRightsReserved.

• Only commercial available 64-bit embedded core• Higher performance• Up to 1.5GHz in 28nm

• Small Area• 0.046 mm2 (core only) in 28nm

• Host/System cores inside 64-bit SoCs• SSD Controllers, Networking

Page 16: Making RISC-V IP easy to play with & evaluate · Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development jack@sifive.com 5/9/2017

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Partners

• SiFive Coreplex IP available from other design partners

© 2017SiFive.AllRightsReserved.

Page 17: Making RISC-V IP easy to play with & evaluate · Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development jack@sifive.com 5/9/2017

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Conclusion

• Visit www.sifive.com• Get instant access to Coreplex IP

© 2017SiFive.AllRightsReserved.

Page 18: Making RISC-V IP easy to play with & evaluate · Making RISC-V IP easy to play with & evaluate Jack Kang VP Product & Business Development jack@sifive.com 5/9/2017

18 18


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Scenario Analytics - Jack & Bobbi Conrad's Homepage€¦ · Scenario Analytics Analyzing Jury Verdicts to Evaluate Legal Case Outcomes Jack G. Conrad Thomson Reuters Research & Development

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Reduced Instruction Set Computers - UC Davis ECEvojin/CLASSES/EEC70/W2004/RISC-v3.pdf · 1.1. RISC Architecture A special place in computer architecture has been given to RISC. RISC

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RiSC-oo.1.v Execution Example - ece.umd.edublj/RiSC/RiSC-ex.pdf · ENEE 446: Digital Computer Design — RiSC-oo.1.v Execution Example 1 ... (i.e. address 0 corresponds to the first

Comparison of RISC Archtectures - UNLPelectro.fisica.unlp.edu.ar/arq/downloads/Papers/RISC/IEEE_Micro_1989... · A Comparison of RISC Archtectures umerous new RISC architectures have