marc riedel the synthesis of stochastic logic for nanoscale computation iwls 2007, san diego may 31,...

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Marc Riedel The Synthesis of Stochastic The Synthesis of Stochastic Logic for Nanoscale Logic for Nanoscale Computation Computation IWLS 2007, San Diego May 31, 2007 A B C { { N W ires M W ires Weikang Qian and John Backes Circuits & Biology Lab, University of Minnesota joint work with

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Marc Riedel

The Synthesis of Stochastic Logic for The Synthesis of Stochastic Logic for Nanoscale ComputationNanoscale Computation

The Synthesis of Stochastic Logic for The Synthesis of Stochastic Logic for Nanoscale ComputationNanoscale Computation

IWLS 2007, San Diego May 31, 2007

A

B

C {

{

N Wires

M Wires

Weikang Qian and John Backes Circuits & Biology Lab, University of Minnesota

joint work with

5/31/07 IWLS 2007 2

Computing Beyond CMOSComputing Beyond CMOS

Intense research into novel materials and devices:

Carbon Nanotubes…

Molecular Switches…

Biological Processes…

5/31/07 IWLS 2007 3

Computing Beyond CMOSComputing Beyond CMOS

Many technologies still in exploratory phase:

b

a

XOR(a, b) !

5/31/07 IWLS 2007 4

Nanoscale CircuitsNanoscale Circuits

• Topological constraints.• Inherent randomness.• High defect rates.

Features:

Challenges:

• High density of bits.

Identify general traits that impinge upon logic synthesis:

{

{

N Wires

M Wires

carbon nanowire crossbar

Circuit Modeling Circuit Modeling

logic

0

1

0

0

1

Characterize probability of outcomes.

inputs outputs

Model defects, variations, uncertainty, etc.:

Circuit Modeling Circuit Modeling

logic

),,( 11 mxxf a

),,( 12 mxxf a

),,( 1 mn xxf a

1x

2x

mx

Functional description is Boolean:

inputs outputs

1x

2x

mx

Consider a probabilistic interpretation:

),,( 11 mxxp

),,( 12 mxxp

),,( 1 mn xxp

logicstochastic

logic

inputs outputs

Circuit Modeling Circuit Modeling

stochasticlogic

Stochastic Logic Stochastic Logic

inputs outputs

0

1

0

0,1,1,0,1,0,1,1,0,1,…

1,0,0,0,1,0,0,0,0,0,…

p1 = Prob(one)

p2 = Prob(one)

serial bit streams

Consider a probabilistic interpretation:

stochasticlogic

Stochastic Logic Stochastic Logic

inputs outputs

0

1

0 51

52

Consider a probabilistic interpretation:

stochasticlogic

Stochastic Logic Stochastic Logic

0

1

0

01001

01000

p1 = Prob(one)

p2 = Prob(one)

parallel bit streams

Consider a probabilistic interpretation:

stochasticlogic

Stochastic Logic Stochastic Logic

0

1

0

parallel bit streams

51

52

Consider a probabilistic interpretation:

stochasticlogic

Stochastic Logic Stochastic Logic

Interpret outputs according to fractional weighting:

0

1

0

5/31/07 IWLS 2007 13

Synthesis of Stochastic LogicSynthesis of Stochastic Logic

• Circuit that computes a probability distribution corresponding to a logical specification.

Given a technology characterized by:

Synthesize:

• High degree of structural parallelism.• Inherent randomness in logic/interconnects.

• Cast problem in terms of arithmetic operations.• Perform synthesis with binary moment diagrams.

Strategy:

5/31/07 IWLS 2007 14

A real value x in [0, 1] is encoded as a stream of bits X.For each bit, the probability that it is one is: P(X=1) = x.

Probabilistic BundlesProbabilistic Bundles

01001

xX

5/31/07 IWLS 2007 15

Arithmetic OperationsArithmetic Operations

AND

A

BC

A

BC

MUX

S

Multiplication (Scaled) Addition

ba

BPAP

CPc

)()(

)(

)

)1(

()](1[)()(

)(

bsas

BPSPAPSP

CPc

5/31/07 IWLS 2007 16

When A is a high, a FET-like region causes high resistance between the VDD and A.

A

VDD

A{

{N Wires

M Wires

Nanowire Crossbar (Nanowire Crossbar (idealizedidealized))

5/31/07 IWLS 2007 17

Nanowire Crossbar (Nanowire Crossbar (idealizedidealized))

{{N Wires

M Wires

Randomized connections,yet nearly one-to-one.

5/31/07 18

a0

a1

a2

a3

VDD

b0

b1

b2

b3

a3b2

a0b1

a1b3

a2b0

Inversion Occurs a0 a1 a3 a2

VDD VDD

b3 b2 b0 b1

Shuffled ANDShuffled AND

5/31/07 IWLS 2007 19

A1

A2

{}B

{

Takes the AND of randomly chosen pairs.Takes the AND of randomly chosen pairs.

MultiplicationMultiplication

Shuffled AND

5/31/07 20

VDD

a0

a1

a2

a3

b0

b1

b2

b3

Densit

y of 1

/4

a0

a1

b1

a3

VDD

Densit

y of 3

/4

BundleplexingBundleplexing

Scaled AdditionScaled Addition

a0

a1

a2

a3

b0

b1

b2

b3

a3

a2

b2

a1

Randomly selection of wires from different bundles, Randomly selection of wires from different bundles, according to a fixed ratio..

¾ Bundleplexer

5/31/07 IWLS 2007 22

Stochastic LogicStochastic Logic

Shuffled ANDs,Bundleplexers

Shuffled ANDs,Bundleplexers

{{

A0

A1

.

.

.

{An

}B

5/31/07 IWLS 2007 23

Stochastic LogicStochastic Logic

Shuffled ANDs,Bundleplexers

Shuffled ANDs,Bundleplexers

{{{

}...

1

0

1

5

2

5/31/07 IWLS 2007 24

Synthesis StrategySynthesis Strategy

• From circuit, construct a data structure called a multiplicative binary moment diagram (*BMD).

• Manipulate the *BMD into the right form.

• Implement a stochastic circuit with Shuffled AND gates and Bundleplexors.

5/31/07 IWLS 2007 25

AND1

AND3

OR1 OR2

AND2

x2

fx3

x4

x1

Arithmetic FunctionsArithmetic Functions

432143421321 2 xxxxxxxxxxxxf

5/31/07 IWLS 2007 26

x4

x3 x3

x2 x2

x1

0 1

-2

R L

Construct *BMDConstruct *BMD

See R. Bryant, “Verification of Arithmetic Circuits with BMDs,” 1995.

432143421321 2 xxxxxxxxxxxxf

x

xfwfwf RRLL

fL fR

x4

x3 x3

x2

x1

0 1

x4

x3

x2

x1

0 1

2

Split *BMDSplit *BMD

432143421321 2 xxxxxxxxxxxxf

positive negative

x4

x3 x3

x2

x1

0 1

1

2

1

2

1

3

2

3

3

x4

x3 x3

x2

x1

0 1

positive

NormalizeNormalize

43421321 xxxxxxxxf PX 432143421321 2 xxxxxxxxxxxxf

5/31/07 IWLS 2007 29

Implement Stochastic LogicImplement Stochastic Logic

x

w

fRfLX

w

N

N

N

SAND BUX

xfR

fL

X

5/31/07 IWLS 2007 30

x1

x2

x3

x4

SAND1SAND2

SAND4SAND3

counter

-2

+3y

1

2

BUX1

1

3

BUX2

N

N

NN

N

N

N

N

NN

Implement Stochastic LogicImplement Stochastic Logic

Size of Stochastic CircuitsSize of Stochastic Circuits

Circuit #Device #Input #Output #StDevice Ratio

C17 14 5 2 26 1.86

b1 18 3 4 18 1.00

majority 18 5 1 23 1.28

lion 19 4 3 30 1.58

cm138a 43 6 8 104 2.42

bbtas 44 5 5 74 1.68

cm42a 49 4 10 61 1.24

tcon 58 17 16 73 1.26

beecount 62 6 7 108 1.74

decod 69 5 16 194 2.81

sqrt8ml 74 8 4 87 1.18

sqrt8 79 8 4 87 1.10

c8 184 28 18 272 1.48

Average 1.54

Circuit S

Ratio of Bundle Widths to Scaling S

5 10 20 50 100

C17 4 8.36 3.13 1.02 0.00 0.00

b1 3 5.63 1.72 0.00 0.16 0.00

majority 9 4.69 1.88 0.94 0.31 0.00

mc 6 3.97 2.12 0.42 0.07 0.00

cm138a 8 0.55 0.51 0.22 0.02 0.00

bbtas 7 5.84 1.91 0.78 0.09 0.00

cm42a 4 0.91 0.56 0.03 0.03 0.00

tcon 2 1.50 0.23 0.01 0.00 0.00

Decod 16 4.81 1.90 0.72 0.11 0.05

Sqrt8ml 24 3.56 1.76 0.82 0.39 0.04

Sqrt8 24 6.60 1.52 0.86 0.12 0.12

c8 6 5.93 3.09 1.03 0.12 0.01

Average 9.13 4.36 1.83 0.60 0.12 0.02

Error PercentagesError Percentages

5/31/07 IWLS 2007 33

DiscussionDiscussion

• Exploits both parallelism and randomness.

• Obviates the need for post-fabrication configuration.

• Measured tradeoff between degree of redundancy and accuracy of the computation.

5/31/07 IWLS 2007 34

drugcompound

(fixed quantity)E. Coli

Research Theme: Probabilistic ComputingResearch Theme: Probabilistic Computing

Bacteria are genetically engineered to produce a drug that fights cancer.

5/31/07 IWLS 2007 35

Bacteria invade cancerous tissue:

cancerous tissue

Research Theme: Probabilistic ComputingResearch Theme: Probabilistic Computing

5/31/07 IWLS 2007 36

Compound is injected.

cancerous tissue

Bacteria produce the drug:

Research Theme: Probabilistic ComputingResearch Theme: Probabilistic Computing

5/31/07 IWLS 2007 37

produce drug

compound

E. Coli

Needed: synthesis of probabilistic response in each bacterium.

with Prob. 0.3

don’t produce drugwith Prob. 0.7

See B. Fett, J. Bruck and M. Riedel, “Synthesizing Stochasticity in Biochemical Systems”, DAC 2007.

Research Theme: Probabilistic ComputingResearch Theme: Probabilistic Computing