massively parallel laser-enabled transfer technology for ... unicarta.pdf · micro-transfer...
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Val MarinovCTO and Founder
UNIQARTA, INC
Massively Parallel Laser-Enabled Transfer Technology for Heterogeneous Integration of
High-Density SoC/SiP
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The Company
2
North Dakota SU (Fargo, ND) spin-off
Registered Nov 2013
Locations in Cambridge, MA and Fargo, ND
Current R&D projects totaling ~$1.8M
Focus: technology development
“Smart Paper”
Technologies for ultra-thin, flexible
electronics
Laser technologies for extremely high-rate
assembly of micro- and mini-LEDs Heterogeneous integration of chiplets
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DARPA CHIPS
Concept:
Different functionalities segregated
into small chiplets (IP blocks), which
are then combined onto an interposer
Supporting Technologies:
Design tools
IP blocks
Assembly methods
Fine pitch interconnects
Heterogeneous integration: small device handling, multi-device technology processing
Image: DARPA
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Chiplets Wafers → SoC Wafer
Semiconductor fabs Integrators
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Some examples for use in the next slides…
SoC 1:
6×6 mm2 ASIC
9 2×2 mm2 chiplets
1600 ASICs on a 12-in wafer
14,400 chiplets
SoC 2:
6×6 mm2 ASIC
144 0.5×0.5 mm2 chiplets
1600 ASICs on a 12-in wafer
230,400 chiplets
Image: Dolphin Integration
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How to put together all these chiplets?
High-speed flip-chip die bonder: assume a cycle time of 0.5 s (7,200 uph)
SOC 1 wafer needs 2 hr to assemble
SOC 2 wafer needs 32 hr to assemble!
A radically different approach is needed for chiplet assembly
Image: Amicra
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Micro-Transfer Printing, µTP
Relies on kinetically controlled adhesion to
pick and place dies: the PDMS stamp moves
at high speed during pick-up and low speed
during placement
Capable of transfer rates of M/uph
Meitl, A.M. eta al., Transfer printing by kinetic control of adhesion to an elastomeric stamp. Nature Materials V. 5, pp 33–38 (2006)
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However…
µTP cannot efficiently handle defective chiplets
CTE mismatch between the PDMS stamp and the Si
substrate may be a problem
Requires specially prepared wafers: chiplets
attached using tethers to allow for pick up by the
stamp’s relatively weak adhesion
Question: will fabs be willing to change their entire
CMOS process flow to accommodate the µTP
requirements?
There is a need, therefore, for assembly
technologies that are compatible with traditional
silicon chip processing.
Radauscher, E.J., et al. Miniaturized LEDs for Flat-Panel Displays. SPIE Proc. 10124, 2017
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Uniqarta’s LEAP Technology
Ultra-fast placement (>100M uph)
Known Good Die selectivity
Wide range of component types (Si, GaN, AlN,
sapphire, metal…) and sizes (20 µm to tens of mm)
LEAP = Laser-Enabled Advanced Placement
US 9,862,141; JP 6053756; CN ZL2012800270480; EP 2697822; KR 1020140045936,…
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LEAP in a Single-Die Transfer (SDT) ModeDemo: 1,040 ups (3.7M uph)
100 laser pulses, 100 transferred dies
1 die transferred per pulse
96 ms
CONFIDENTIAL INFORMATION
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LEAP is not only very fast but also precise
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
35 20 10
Pla
cem
ent
erro
rs, m
m
Transfer gap, mm
Accuracy Precision at 3STD
A field of transferred 50×50 µm dies
(image taken through the glass carrier)
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Uniqarta’s Ultra-Fast Placement Solution:
Milti-Die Transfer (MDT)
untransferred dies on carrier underside
locations of previously transferred dies
5x5 array to be transferred
die size: 45x45 µm
WO2017123780; US 62/518270; TW 201725642
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16 laser pulses, 64 transferred dies
4 dies transferred per pulse
18 ms
CONFIDENTIAL INFORMATION
LEAP in a Multi-Die Transfer ModeDemo: 2x2 MDT; 3,500 /s (12.6M uph)
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SDT and MDT used for Good-Die-Only Placement
Wafer
Substrate
bad dies
1. Bad Die Removalsingle-die mode
2. Good Die Placementmulti-die mode
3. Fill-Insingle-die mode
transfer field
(none)
missing dies
fully-populated substrate
placed dies
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Thank you.