matlab and simulink manual

MATLAB/Simulink X5 BSP Manual

MATLAB/Simulink X5 BSP ManualThe MATLAB/Simulink X5 BSP Manual was prepared by the technical staff of Innovative Integration on January 27, 2009.

For further assistance contact:

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This document is copyright 2009 by Innovative Integration. All rights are reserved.

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Table of ContentsMATLAB/Simulink X5 BSP Manual......................................................................................................................................2

Introduction................................................................................................................................................9Key Features.......................................................................................................................................................................9

Hardware Design Using System Generator........................................................................................................................... 10Design Flows Using System Generator........................................................................................................................... 10

Algorithm Exploration................................................................................................................................................10Implementing Part of a Larger Design....................................................................................................................... 10Implementing a Complete Design.............................................................................................................................. 11

System Level Modeling in System Generator................................................................................................................. 11System Generator Blockset........................................................................................................................................ 11Xilinx Blockset...........................................................................................................................................................12Innovative Integration Blockset................................................................................................................................. 13Bit-True and Cycle-True Modeling............................................................................................................................13Timing and Clocking..................................................................................................................................................14

Automatic Code Generation.............................................................................................................................................15Compiling and Simulating Using System Generator Block.......................................................................................15Compilation Type and the Generate Button...............................................................................................................16Compilation Results................................................................................................................................................... 17HDL Testbench.......................................................................................................................................................... 17

Compiling MATLAB into an FPGA................................................................................................................................18Importing a System Generator Design into a Bigger System................................................................................................19

NGC Netlist Compilation.................................................................................................................................................19Design Rules...............................................................................................................................................................20Synthesis ....................................................................................................................................................................20Simulation...................................................................................................................................................................21Step-by-Step Example................................................................................................................................................ 22Generating the NGC files for the System Generator Designs....................................................................................23Synthesizing the Top Level Design............................................................................................................................23

Using FPGA Hardware in the Loop...................................................................................................................................... 24Compiling a Model for Hardware Co-Simulation........................................................................................................... 24

Choosing a Compilation Target..................................................................................................................................24Invoking the Code Generator..................................................................................................................................... 24

Hardware Co-Simulation Blocks..................................................................................................................................... 25Hardware Co-Simulation Clocking..................................................................................................................................26

Single-Step Clock.......................................................................................................................................................26Free-Running Clock................................................................................................................................................... 26Selecting the Clock Mode.......................................................................................................................................... 26

Board-specific I/O Ports...................................................................................................................................................27

Installation Instructions.......................................................................................................................... 29

Design Flow...............................................................................................................................................30Start a New Design Using System Generator........................................................................................................................30Solutions for Timing Problems..............................................................................................................................................31Integrate the Design into FPGA.............................................................................................................................................33

Advanced Skills........................................................................................................................................ 36

MATLAB/Simulink X5 BSP Manual 3

Explore II BSP LIB................................................................................................................................................................36Modify the Library and Change Configurations in Simulink................................................................................................40Add Extra Ports to FrameWork Logic...................................................................................................................................42

II DSP LIB................................................................................................................................................ 43Software Prerequisites........................................................................................................................................................... 43Component Description......................................................................................................................................................... 44

Overview.......................................................................................................................................................................... 44ii_data_mover...................................................................................................................................................................45ii_flow_ctrl.......................................................................................................................................................................46ii_splitter and ii_joiner..................................................................................................................................................... 47ii_shifter........................................................................................................................................................................... 49ii_divider.......................................................................................................................................................................... 50ii_burst256........................................................................................................................................................................51Virtex5 Asymmetric FIFO............................................................................................................................................... 52

X5 400M Board Support Package.......................................................................................................... 54Software Prerequisites........................................................................................................................................................... 54Component Description......................................................................................................................................................... 55

Overview.......................................................................................................................................................................... 55ADC INTF....................................................................................................................................................................... 56DAC INTF....................................................................................................................................................................... 57DDR INTF....................................................................................................................................................................... 59ii_interleaver.................................................................................................................................................................... 60ii_deinterleaver.................................................................................................................................................................61ii_reorder ......................................................................................................................................................................... 63ii_packetizer..................................................................................................................................................................... 64PCI Express INTF............................................................................................................................................................ 66QDR SRAM INTF........................................................................................................................................................... 67DAC SPI INTF.................................................................................................................................................................69Digital IO......................................................................................................................................................................... 70System Configuration.......................................................................................................................................................71

Examples................................................................................................................................................................................74Example: x5_400m_default.mdl...................................................................................................................................... 75Example: fir_loopback.mdl..............................................................................................................................................78Example: user_design.mdl............................................................................................................................................... 80

X5 210M Board Support Package.......................................................................................................... 82Software Prerequisites........................................................................................................................................................... 82Component Description......................................................................................................................................................... 83

Overview.......................................................................................................................................................................... 83ADC INTF....................................................................................................................................................................... 84DDR INTF....................................................................................................................................................................... 85ii_interleaver_210m......................................................................................................................................................... 86ii_reorder ......................................................................................................................................................................... 87ii_packetizer..................................................................................................................................................................... 88PCI Express INTF............................................................................................................................................................ 90QDR SRAM INTF........................................................................................................................................................... 91ADC SPI INTF.................................................................................................................................................................93Digital IO......................................................................................................................................................................... 94System Configuration.......................................................................................................................................................95


Examples................................................................................................................................................................................98Example: x5_210m_default.mdl...................................................................................................................................... 99Example: user_design.mdl............................................................................................................................................. 102

FAQ......................................................................................................................................................... 105

Revision History..................................................................................................................................... 109


List of TablesTable 1. Xilinx Library Blocksets..........................................................................................................................................12Table 2. Compilation Results................................................................................................................................................16Table 3. ii_data_mover Logic Ports.......................................................................................................................................45Table 4. ii_flow_ctrl Logic Ports...........................................................................................................................................46Table 5. ii_splitter Logic Ports.............................................................................................................................................. 47Table 6. ii_joiner Logic Ports................................................................................................................................................ 48Table 7. ii_shifter Logic Ports............................................................................................................................................... 49Table 8. ii_divider Logic Ports.............................................................................................................................................. 50Table 9. ii_burst256 Logic Ports............................................................................................................................................50Table 10. Virtex5 Asymmetric FIFO Logic Ports................................................................................................................. 52Table 11. ADC INTF Logic Ports......................................................................................................................................... 56Table 12. DAC INTF Logic Ports......................................................................................................................................... 58Table 13. DDR INTF Logic Ports......................................................................................................................................... 59Table 14. ii_interleaver Logic Ports...................................................................................................................................... 60Table 15. ii_deinterleaver Logic Ports...................................................................................................................................61Table 16. ii_reorder Logic Ports............................................................................................................................................ 62Table 17. ii_packetizer Logic Ports....................................................................................................................................... 64Table 18. PCIE TX Logic Ports.............................................................................................................................................65Table 19. PCIE RX Logic Ports.............................................................................................................................................65Table 20. SRAM INTF Logic Ports.......................................................................................................................................67Table 21. Commands for DAC SPI INTF............................................................................................................................. 67Table 22. DAC SPI INTF Logic Ports...................................................................................................................................68Table 23. Digital IO Logic Ports........................................................................................................................................... 69Table 24. System Configuration Logic Ports.........................................................................................................................71Table 25. MATLAB Examples for X5 400M........................................................................................................................72


List of FiguresFigure 1. System Generator Blocksets...................................................................................................................................11Figure 2. Innovative Integration BSP Library....................................................................................................................... 12Figure 3. Simulink Gateways.................................................................................................................................................13Figure 4. Simulink Scope.......................................................................................................................................................13Figure 5. Xilinx System Generator Block............................................................................................................................. 15Figure 6. Compilation Flow...................................................................................................................................................18Figure 7. NGC compilation target......................................................................................................................................... 19Figure 8. Synthesis flow........................................................................................................................................................ 20Figure 9. Design Block Diagram.......................................................................................................................................... 21Figure 10. Invoking the code generator................................................................................................................................. 24Figure 11. Hardware Co-simulation..................................................................................................................................... 24Figure 12. Hardware Co-simulation Library block............................................................................................................... 24Figure 13. Clock source selection for hardware Co-simulation............................................................................................ 26Figure 14. Board Specific IO for PMC UWB from Innovative Integration ......................................................................... 27Figure 15. Design flow chart................................................................................................................................................. 29Figure 16. Xilinx Timing Analyzer....................................................................................................................................... 30Figure 17. Xilinx Floorplanner.............................................................................................................................................. 31Figure 18. X5 400M default example for FPGA implementation.........................................................................................32Figure 19. Configuration of System Generator Token for ngc generation............................................................................32Figure 20. In the example, the gray areas need to be modified............................................................................................. 33Figure 21. In the example, the gray areas need to be modified............................................................................................. 34Figure 22. X5 400M library and the non-memory gateways under the mask....................................................................... 35Figure 23. Relationship of FrameWork Logic and jtagcosim_top........................................................................................ 36Figure 24. Configuration of the token and XFLOW options.................................................................................................36Figure 25. Compilation flow..................................................................................................................................................37Figure 26. Generated bitstream for hardware co-simulation................................................................................................. 37Figure 27. Project for hardware co-simulation...................................................................................................................... 38Figure 28. Settings for hardware co-simulation block...........................................................................................................38Figure 29. Project block diagram...........................................................................................................................................39Figure 30. Block diagram of System Configuration block....................................................................................................40Figure 31. Write registers by adding a “Gateway In.”...........................................................................................................40Figure 32. Blocks in II DSP LIB........................................................................................................................................... 43Figure 33. ii_data_mover component.................................................................................................................................... 44Figure 34. ii_data_mover panel............................................................................................................................................. 44Figure 35. ii_flow_ctrl component........................................................................................................................................ 45Figure 36. ii_flow_ctrl panel................................................................................................................................................. 45Figure 37. ii_splitter and ii_joiner component.......................................................................................................................46Figure 38. ii_splitter and ii_joiner panel................................................................................................................................47Figure 39. ii_shifter component.............................................................................................................................................48Figure 40. ii_divider component............................................................................................................................................49Figure 41. ii_burst256 component......................................................................................................................................... 50Figure 42. Virtex5 Asymmetric FIFO component.................................................................................................................51Figure 43. FIFO with a 1:4 aspect ratio................................................................................................................................. 51Figure 44. FIFO with a 4:1 aspect ratio................................................................................................................................. 52Figure 45. X5 400M block diagram.......................................................................................................................................54Figure 46. ADC INTF component.........................................................................................................................................55Figure 47. ADC 0 INTF Panel...............................................................................................................................................55


Figure 48. DAC INTF component.........................................................................................................................................56Figure 49. DAC 0 INTF panel............................................................................................................................................... 57Figure 50. DDR INTF component.........................................................................................................................................58Figure 51. ii_interleaver component......................................................................................................................................59Figure 52. ii_deinterleaver component.................................................................................................................................. 61Figure 53. ii_reorder component........................................................................................................................................... 62Figure 54. ii_reorder panel.....................................................................................................................................................63Figure 55. ii_packetizer component.......................................................................................................................................63Figure 56. ii_packetizer under the mask................................................................................................................................64Figure 57. PCIE INTF component.........................................................................................................................................65Figure 58. QDR SRAM INTF component.............................................................................................................................66Figure 59. DAC SPI INTF component.................................................................................................................................. 68Figure 60. DIO component.................................................................................................................................................... 69Figure 61. System Configuration component........................................................................................................................ 70Figure 62. System Configuration panel................................................................................................................................. 70Figure 63. Xilinx Jtag pod configuration...............................................................................................................................72Figure 64. Block diagram of default example....................................................................................................................... 73Figure 65. Configuration of the token and XFLOW options.................................................................................................74Figure 66. Generated bitstream for hardware co-simulation................................................................................................. 74Figure 67. Project for hardware co-simulation...................................................................................................................... 75Figure 68. Settings for hardware co-simulation block...........................................................................................................75Figure 69. Block diagram of fir_loopback example.............................................................................................................. 76Figure 70. Filter coefficients generated in MATLAB FDATool...........................................................................................76Figure 71. DAC0 output on the oscilloscope.........................................................................................................................77Figure 72. Block diagram of user_design.mdl.......................................................................................................................78Figure 73. Write/read to ctl_reg44 through X5-400 Wave....................................................................................................78Figure 74. Write/read to ctl_reg44 through X5-400 Wave....................................................................................................79Figure 75. Value read back of ctl_reg44 in MATLAB/Simulink..........................................................................................79Figure 76. X5 210M block diagram.......................................................................................................................................81Figure 77. ADC INTF component.........................................................................................................................................82Figure 78. ADC 0 INTF Panel...............................................................................................................................................82Figure 79. DDR INTF component.........................................................................................................................................83Figure 80. PCIE INTF component.........................................................................................................................................84Figure 81. QDR SRAM INTF component.............................................................................................................................85Figure 82. DIO component.................................................................................................................................................... 87Figure 83. Packetizer component...........................................................................................................................................88Figure 84. System Configuration component........................................................................................................................ 89Figure 85. System Configuration panel................................................................................................................................. 89Figure 86. Xilinx Jtag pod configuration...............................................................................................................................91Figure 87. Block diagram of default example....................................................................................................................... 92


Introduction

System Generator™ for DSP is the industry’s leading high-level tool for designing high performance DSP systems using FPGAs. The tool provides abstractions that enable designers to develop high performance signal processing algorithms with the industry’s most advanced FPGAs, providing system modeling and automatic code generation from Simulink and MATLAB (The MathWorks, Inc.)

Innovative Integration products, including the Velocia DSP and PMC cards, support FPGA development and debug through board support packages (BSP) that integrate the hardware with the System Generator with MATLAB. The BSP packages provide direct access to the hardware from the MATLAB environment for real-time, hardware-in-the-loop testing and debug.

Key Features

• DSP Modeling. Build and debug high performance DSP systems in Simulink using Xilinx Blockset and Innovative Board Support Package (BSP). Xilinx blockset contains functions for signal processing such as FIR Filters and FFTs, error correction (i.e. Viterbi decoder, Reed-Solomon encoder/decoder), arithmetic, memories (e.g. FIFO, RAM,) and digital logic. The Innovative blockset contains functions for accessing various features on the board such as DDR memory, ADC, DAC, SBSRAM, RocketIO, PMC J4 interface.

• Automatic code generation of VHDL or Verilog from Simulink. Implement behavioral (RTL) generation and target specific IP cores from the Xilinx blockset. There is also a limited but useful ability to generate RTL functions written in MATLAB.

• Hardware co-simulation. Create an “FPGA-in-the-Loop” simulation target: a code generation option that allows you to validate working hardware and accelerate simulations in Simulink and MATLAB.

• Hardware/software co-design of embedded systems. Build and debug DSP co-processors for the Xilinx MicroBlaze™ 32-bit RISC processor. System Generator provides a shared memory abstraction of the HW/SW interface, automatically generating the DSP co-processor, the bus interface logic, software drivers, and software documentation for using the co-processor.


Hardware Design Using System Generator

System Generator is a system level modeling tool that facilitates FPGA hardware design. It extends Simulink in many ways to provide a modeling environment that is well suited to hardware design. The tool provides high level abstractions that are automatically compiled into an FPGA at the push of a button. The tool also provides access to underlying FPGA resources through low level abstractions, allowing the construction of highly efficient FPGA designs.

Design Flows Using System Generator

System Generator can be useful in many settings. Sometimes you may want to explore an algorithm without translating the design into hardware. Other times you might plan to use a System Generator design as part of something bigger. A third possibility is that a System Generator design is complete in its own right, and is to be used in FPGA hardware. This section describes all three possibilities.

Algorithm ExplorationSystem Generator is particularly useful for algorithm exploration, design prototyping, and model analysis. When these are the goals, the tool is used to flesh out an algorithm in order to get a feel for the design problems that are likely to be faced, and perhaps to estimate the cost and performance of an implementation in hardware. Work is preparatory, and there is little need to translate the design into hardware.

In this setting, a designer assembles key portions of the design without worrying about fine points or detailed implementation. Simulink blocks and MATLAB .m code provide stimuli for simulations, and for analyzing results. Resource estimation gives a rough idea of the cost of the design in hardware. Experiments using hardware generation can suggest the hardware speeds that are possible.

Once a promising approach has been identified, the design can be fleshed out. System Generator allows refinements to be done in steps, so some portions of the design can be made ready for implementation in hardware, while others remain high level and abstract. System Generator's facilities for incremental netlisting and hardware co-simulation are particularly useful when portions of a design are being refined.

Implementing Part of a Larger DesignOften System Generator is used to implement a portion of a larger design. For example, System Generator is a good setting in which to implement data paths and control, but is less well suited for sophisticated external interfaces that have strict timing requirements. In this case, it may be useful to implement parts of the design using System Generator, implement other parts outside, and then combine the parts into a working whole.

A typical approach to this flow is to create an HDL wrapper that represents the entire design, and to use the System Generator portion as a component. The non-System Generator portions of the design can also be components in the wrapper, or can be instantiated directly in the wrapper.


Implementing a Complete DesignMany times, everything needed for a design is available inside System Generator. For such a design, pressing the Generate button instructs System Generator to translate the design into HDL, and to write the files needed to process the HDL using downstream tools. The files written include the following:

• HDL that implements the design itself

• A clock wrapper that encloses the design. This clock wrapper produces the clock and clock enable signals that the design needs.

• A HDL testbench that encloses the clock wrapper. The testbench allows results from Simulink simulations to be compared against RTL simulations in a tool such as ModelSim.

• Project files and scripts that allow various synthesis tools (XST and Synplify) to operate on System Generator HDL.

• Files that allow the System Generator HDL to be used as a project in Project Navigator

System Level Modeling in System Generator

Xilinx's System Generator allows device-specific hardware designs to be constructed directly in a flexible high level system modeling environment. In a System Generator design, signals are not just bits. They can be signed and unsigned fixed point numbers, and changes to the design automatically translate into appropriate changes in signal types. Blocks are not just stand-ins for hardware. They respond to their surroundings, automatically adjusting the results they produce and the hardware they become.

System Generator allows designs to be composed from a variety of ingredients. Data flow models, traditional hardware design languages (VHDL, Verilog, and EDIF,) and functions derived from the MATLAB programming language, can be used side-by-side, simulated together, and synthesized into working hardware. System Generator simulation results are bit and cycle-accurate. This means results seen in simulation exactly match the results that are seen in hardware. System Generator simulations are considerably faster than those from traditional HDL simulators, and results are easier to analyze.

System Generator BlocksetA Simulink blockset is a library of blocks that can be connected in the Simulink block editor to create functional models of a dynamic system. For system modeling, System Generator blocksets are used like other Simulink blocksets in that the blocks provide abstractions of mathematical, logic, memory, and DSP functions that can be used to build sophisticated signal processing systems. There are also blocks that provide interfaces to other software tools (e.g., FDATool, ModelSim) as well as the System Generator code generation software.

System Generator blocks are bit-true and cycle-true. Bit-true blocks produce values in Simulink that match corresponding values produced in hardware; cycle-true blocks produce corresponding values at corresponding times. This is in essence a “what you see is what you get” system that accurately represents the system performance in time and bits.


Figure 1. System Generator Blocksets

Xilinx BlocksetThe Xilinx Blockset is a family of libraries that contain basic System Generator blocks. Some blocks are low level, providing access to device-specific hardware. Others are high level, implementing signal processing and advanced communications algorithms. For convenience, blocks with broad applicability (e.g., the Gateway I/O blocks) are members of several libraries. Every block is contained in the Index library as follows

Library Description

Index Every block in the Xilinx Blockset

Basic elements Standard building blocks for digital logic.

Communication Forward error correction and modulator blocks, commonly used in digital communications systems.

Control logic Blocks for control circuitry and state machines

Data types Blocks that convert data types (includes gateways).

DSP Digital signal processing (DSP) blocks.

Math Blocks that implement mathematical functions.


Memory Blocks that implement and access memories.

Shared memory Blocks that implement and access Xilinx shared memories.

Tools "Utility" blocks, e.g., code generation (System Generator block), resource estimation, HDL co-simulation, etc.

Table 1. Xilinx Library Blocksets

Innovative Integration BlocksetThe Innovative Integration (II) blockset is a library that contains board specific hardware and firmware components. For system modeling, these blocks can be used as Simulink blocks. Innovative Integration blockset provides means to communicate and control the resources available on the board such as DDR Memory, ADC, DAC, SRAM, RocketIO, PMC J4 interface etc.

Figure 2. Innovative Integration BSP Library

Bit-True and Cycle-True ModelingSimulations in System Generator are bit-true and cycle-true. To say a simulation is bit-true means that at the boundaries (i.e., interfaces between System Generator blocks and non-System Generator blocks,) a value produced in simulation is bit-for-bit identical to the corresponding value produced in hardware. To say a simulation is cycle-true means that at the boundaries, corresponding values are produced at corresponding times. The boundaries of the design are the points at which System


Generator gateway blocks exist. When a design is translated into hardware, Gateway In (respectively, Gateway Out) blocks become top-level input (resp., output) ports.

Timing and Clocking• Discrete time systems - Designs in System Generator are discrete time systems. In other words, the signals and the

blocks that produce them have associated sample rates. A block's sample rate determines how often the block is awoken (allowing its state to be updated.) System Generator sets most sample rates automatically. A few blocks, however, set sample rates explicitly or implicitly.

A simple System Generator model illustrates the behavior of discrete time systems. Consider the model shown below. It contains a gateway that is driven by a Simulink source (Sine Wave,) and a second gateway that drives a Simulink sink (Scope.)

Figure 3. Simulink Gateways

The Gateway In block is configured with a sample period of one second. The Gateway Out block converts the Xilinx fixed-point signal back to a double (so it can analyzed in the Simulink scope,) but does not alter sample rates. The scope output below shows the unaltered and sampled versions of the sine wave.

Figure 4. Simulink Scope


• Multi-rate Systems - System Generator supports multi-rate designs, i.e., designs having signals running at several sample rates. System Generator automatically compiles multi-rate models into hardware. This allows multi-rate designs to be implemented in a way that is both natural and straightforward in Simulink. More information about multi-rate systems can be found in Xilinx System Generator manual.

Automatic Code Generation

System Generator automatically compiles designs into low level representations. The ways in which System Generator compiles a model can vary, and depend on settings in the System Generator block. In addition to producing HDL descriptions of hardware, the tool generates auxiliary files. Some files (e.g., project files, constraints files) assist downstream tools, while others (e.g., VHDL testbench) are used for design verification. System Generator also provides incremental netlisting, making it possible to augment models with results that System Generator itself has produced.

Compiling and Simulating Using System Generator BlockSystem Generator automatically compiles designs into low-level representations. Designs are compiled and simulated using the System Generator block. This section describes how to use the block.

Before a System Generator design can be simulated or translated into hardware, the design must include a System Generator block. When creating a new design, it is a good idea to add a System Generator block immediately because it defines how the system will be compiled. The System Generator block is a member of the Xilinx Blockset's Basic Elements and Tools libraries. As with all Xilinx blocks, the System Generator block can also be found in the Index library.

A design must contain at least one System Generator block, but can contain several System Generator blocks on different levels (one per level.) A System Generator block that is underneath another in the hierarchy is a slave; one that is not a slave is a master. The scope of a System Generator block consists of the level of hierarchy into which it is embedded and all subsystems below that level. Certain parameters (e.g. Simulink System Period) can be specified only in a master.

Once a System Generator block is added, it is possible to specify how code generation and simulation should be handled. The block's dialog box is shown below:


Figure 5. Xilinx System Generator Block

Compilation Type and the Generate ButtonPressing the Generate button instructs System Generator to compile a portion of the design into equivalent low-level results. The portion that is compiled is the sub-tree whose root is the subsystem containing the block. (To compile the entire design, use a System Generator block placed at the top of the design.) The compilation type (under Compilation) specifies the type of result that should be produced. The possible types are

• Two types of Netlists, HDL Netlist and NGC Netlist

• Bitstream - produces an FPGA configuration bitstream that is ready to run in a hardware FPGA platform

• EDK Export Tool - for exporting to the Xilinx Embedded Development Kit

• Various varieties of hardware co-simulation (i.e. Innovative Integration products)

• Timing Analysis - a report on the timing of the design

HDL Netlist is the type used most often. In this case, the result is a collection of HDL and EDIF files, and a few auxiliary files that simplify downstream processing. The collection is ready to be processed by a synthesis tool (e.g., XST,) and then fed to the Xilinx physical design tools (i.e. ngdbuild, map, par, and bitgen) to produce a configuration bitstream for a Xilinx FPGA.

NGC Netlist is similar to HDL Netlist but the resulting files are NGC files instead of HDL files.

When targeting the compile for hardware co-simulation, System Generator produces an FPGA configuration bitstream that is ready to run in a hardware FPGA platform. The particular platform depends on the variety chosen. For example, when the variety is Hardware Co-simulation->UWB, the bitstream is suitable for the UWB PMC board. System Generator also produces a hardware co-simulation block to which the bitstream is associated. This block is able to participate in Simulink


simulations. It is functionally equivalent to the portion of the design from which it was derived, but is implemented by its bitstream. In a simulation, the block delivers the same results as those produced by the portion, but the results are calculated in working hardware.

Compilation ResultsThe low level files System Generator produces when HDL Netlist is selected on the System Generator block and Generate is pushed consist of HDL, NGC, and EDIF that implement the design. In addition, System Generator produces auxiliary files that simplify downstream processing, e.g., bringing the design into Project Navigator, simulating using ModelSim, and synthesizing using various synthesis tools. All files are written to the target directory specified on the System Generator block. If no testbench is requested, the key files produced by System Generator are the following:

File name or type Description

<design>.vhd/.v This contains most of the HDL for the design.

<design>_cw.vhd/.v This is a HDL wrapper for <design>_files.vhd/.v. It drives clocks and clock enables.

.edn and .ngc files Besides writing HDL, System Generator runs CORE Generator (coregen) to implement portions of the design. Coregen writes EDIF files whose names typically look something like multiplier_virtex2_6_0_83438798287b830b.edn. Other required files may be supplied as .ngc files

globals This file consists of key/value pairs that describe the design. The file is organized as a Perl hash table so that the keys and values can be made available to Perl scripts using Perl evals.

<design>_cw.xcf (or .ncf)

This contains timing and port location constraints. These are used by the Xilinx synthesis tool XST and the Xilinx implementation tools. If the synthesis tool is set to something other than XST, then the suffix is changed to .ncf.

<design>_cw.ise This allows the HDL and EDIF to be brought into the Xilinx project management tool Project Navigator.

hdlFiles This contains the full list of HDL files written by System Generator. The files are listed in the usual HDL dependency order.

synplify_<design>.prj, or xst_<design>.prj

These files allow the design to be compiled by the synthesis tool you specified

Vcom.do Modelsim script for behavioral simulationTable 2. Compilation Results

HDL TestbenchOrdinarily, System Generator designs are bit and cycle-accurate, so Simulink simulation results exactly match those seen in hardware. There are, however, times when it is useful to compare Simulink simulation results against those obtained from an HDL simulator. In particular, this makes sense when the design contains black boxes. The Create Testbench checkbox in the System Generator block makes this possible.


Suppose the design is named <design>, and a System Generator block is placed at the top of the design. Suppose also that in the block the Compilation field is set to HDL Netlist, and the Create Testbench checkbox is selected. When the Generate button is pushed, System Generator produces the usual files for the design, and in addition writes the following:

1. A file named <design>_tb.vhd/.v that contains a testbench HDL entity

2. Various .dat files that contain test vectors for use in an HDL testbench simulation

3. Scripts vcom.do and vsim.do that can be used in ModelSim to compile and simulate the testbench, comparing Simulink test vectors against those produced in HDL

System Generator generates the .dat files by saving the values that pass through gateways. In the HDL simulation, input values from the .dat files are stimuli, and output values are expected results. The testbench is simply a wrapper that feeds the stimuli to the HDL for the design, then compares HDL results against expected ones.

Compiling MATLAB into an FPGA

System Generator provides direct support for MATLAB through the MCode block. The MCode block applies input values to an M-function for evaluation using Xilinx's fixed-point data type. The evaluation is done once for each sample period. The block is capable of keeping internal states with the use of persistent state variables. The input ports of the block are determined by the input arguments of the specified M-function and the output ports of the block are determined by the output arguments of the M-function. The block provides a convenient way to build finite state machines, control logic, and computation heavy systems.

In order to construct an MCode block, an M-function must be written. The M-file must be in the directory of the model file that is to use the M-file or in a directory in the MATLAB path. Additional examples can be found at the System Generator User Guide.


Importing a System Generator Design into a Bigger System

A System Generator design is often incorporated as a part of a larger HDL design. This section shows how to embed two System Generator designs into a larger design, and how VHDL created by System Generator can be incorporated into a simulation model of the overall system.

The most convenient way to incorporate a System Generator design into an HDL design is to encapsulate the entire design into a single binary module in the NGC binary netlist format used by the Xilinx ISE tool suite. In this case, the System Generator design is viewed as a black box by the logic synthesis tool.

The design flow to import a System Generator design into a larger system is shown in Figure 6.

Figure 6. Compilation Flow

NGC Netlist Compilation

Selecting the NGC Netlist compilation target from the System Generator block, as shown in Figure 7, instructs System Generator to compile the design into a standalone Xilinx NGC binary netlist file.

When System Generator is configured to include clock wrapper logic, the design is compiled into <design>_cw.ngc in the target directory, where <design> is derived from the name of the portion of the System Generator model being compiled. Alternatively, the design is saved as <design>.ngc when the clock wrapper is not included.

The NGC netlist contains both the logic and constraint information for your design. This means that all HDL, cores, and constraint files normally created by System Generator are encapsulated within a single file. We will show how multiple NGC files can be used as modules in a larger design.


Figure 7. NGC compilation target

Design RulesWhen a System Generator model is to be included into a larger design, there are two design rules that must be followed. First, no Gateway or System Generator block should specify an IOB/CLK location constraint. Otherwise, the NGDBuild tool will issue the following warning:

WARNING:NgdBuild:483 - Attribute "LOC" on "clk" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.

Second, I/O buffers must not be inserted in the NGC netlist during synthesis. Instead, I/O buffers should be instantiated in the top level HDL code. Second, I/O buffers must not be inserted in the NGC netlist during synthesis. Instead, I/O buffers should be instantiated in the top level HDL code.

Synthesis Figure 8 shows the synthesis flow for an entire design when the NGC Netlist compilation target is used.


Figure 8. Synthesis flow

The System Generator NGC module can be directly instantiated inside the top level VHDL entity as follows:

component foo_cw is port ( . . . ); end component;

attribute box_type of foo_cw : component is "black_box";

attribute syn_black_box of foo_cw : component is true;

To make this process easier, System Generator creates an HDL component instantiation template when the design is compiled using the NGC target. When VHDL is selected as the hardware description language, the template is saved in the target directory as <design>_cw.vho (or <design>.vho when the clock wrapper is excluded.) The file is saved using a .veo extension when Verilog is selected as the hardware description language. You may use the component template to instantiate the component in your top level entity.

The box_type attribute should be used when synthesizing your VHDL with XST and the syn_black_box attribute should be used with Synplify.

SimulationWhen you compile a System Generator model into an NGC target, the VHDL files created by System Generator are necessary only for HDL simulation. They should not be included into the Project Navigator project for synthesis. This increases the performance of Project Navigator and synthesis of the top level.

If you wish to run the entire design through an HDL simulator, you need to specify a custom ModelSim .do file in Project Navigator, since the VHDL files are not included in the project. In addition to the VHDL files, you will need to place the memory initialization (.mif) and coefficient (.coe) files in the same directory as the VHDL files


Step-by-Step ExampleIn this example, two NGC netlists from System Generator are imported into a larger VHDL design. Design #1 is named SPRAM and design #2 is MAC_FIR. The top level VHDL entity combines the two data ports and a control signal from the SPRAM design to create a bidirectional bus. The top level VHDL also instantiates the MAC_FIR design and supplies it a separate clock signal named clk2. A block diagram of this design is shown in Figure 9.

Figure 9. Design Block Diagram

The files used in this example are provided in <path_to_sysgen>\examples\import. The default path to sysgen would be $MATLAB\toolbox\xilinx\sysgen. The following files are provided:

• spram.mdl - System Generator design #1

• mac_fir.mdl - System Generator design #2

Files within the sub-directory named top_level:

• top_level.vhd – Top level VHDL file

• top_level_testbench.vhd – Top level VHDL testbench file

• top_level.ise – Project Navigator project for compiling top_level design

• top_level_testbench.do – Custom ModelSim .do file

• wave.do – ModelSim .do file called by top_level_testbench.do to display waveforms


Generating the NGC files for the System Generator DesignsThe steps used to create the NGC files are as follows

• Open the first design, spram.mdl, in MATLAB. This is a multirate design due to the down sampling block placed after the output of the Single Port RAM. You should verify the constraints for this design have been applied properly by looking at the PAR report

• Double click on the System Generator block, select the NGC Netlist target and press the Generate button. By pressing the Generate button, the NGC file for this design is created in the <path_to_sysgen>\examples\import\ngc_netlist1 directory

• Repeat steps 1 and 2 for the mac_fir.mdl model. The NGC file for this design is created in the <path_to_sysgen>\examples\import\ngc_netlist2 directory

Synthesizing the Top Level DesignThe next two steps are used to synthesize the top_level design:

• Copy all the .ngc files from the ngc_netlist1 and ngc_netlist2 directories to the top_level project directory so that NGDBUILD can fill the Black Box in the top_level.vhd file. The .ngc files created are named spram_cw.ngc and mac_fir_cw.ngc

• Now we synthesize the top-level design. In Windows Explorer, go to the <path_to_sysgen>\examples\import\top_level directory and double click on the Project Navigator project file named top_level.ise. Select top_level-behavior in the Sources in Project window and then double left click on the Place & Route Report process (the process is under Implement Design -> Place & Route) process in the Processes for Source window.

There are a few important things to keep in mind during each phase of the process.

While creating a System Generator design:

• IOB constraints should not be specified on Gateways in the System Generator model; neither should the System Generator block specify a clock pin location

• Use the NGC Netlist compilation target in the System Generator block. The NGC netlist file that System Generator produces contains both the logic and constraint information for your design

To instantiate System Generator in the top_level HDL:

• Use a black box and assign the appropriate black box attribute

• The ce port is not connected to registers within your design. It is provide so that the VHDL file can be imported as a Black Box within System Generator


Using FPGA Hardware in the Loop

System Generator provides hardware co-simulation, making it possible to incorporate a design running in an FPGA directly into a Simulink simulation. “Hardware Co-simulation” compilation targets automatically create a bitstream and associate it to a block. When the design is simulated in Simulink, results for the compiled portion are calculated in hardware. This allows the compiled portion to be tested in actual hardware, and can speed up simulation dramatically.

Compiling a Model for Hardware Co-Simulation

The starting point for hardware co-simulation is the creating in MATLAB with System Generator a model or subsystem you would like to run in hardware. A model can be co-simulated, provided it meets the requirements of the underlying hardware platform. This model must include a System Generator block; this block defines how the model should be compiled into hardware. The first step, once you have a model that you are ready to run in hardware, is to open the System Generator block dialog box and select a compilation type under Compilation.

Choosing a Compilation TargetYou may choose the hardware co-simulation platform you would like System Generator to compile code for by selecting an appropriate compilation type in the System Generator block dialog box. Hardware co-simulation targets are organized under the Hardware Co-Simulation sub-menu in the Compilation dialog box field. When you install System Generator, several hardware co-simulation compilation targets are automatically installed. You may also install additional plug-in compilation targets that add hardware co-simulation support for your FPGA platform.

Invoking the Code GeneratorOnce you have selected a compilation target you can invoke the System Generator code generator to compile the model for hardware co-simulation. The code generator is invoked by pressing the Generate button in the System Generator block dialog box as shown in Figure 10.

The code generator produces a FPGA configuration bitstream for your design that is suitable for hardware co-simulation. System Generator not only generates the HDL and netlist files for your model during the compilation process, but it also runs the downstream tools necessary to produce an FPGA configuration file.

The configuration bitstream contains the hardware associated with your model, and also contains additional interfacing logic that allows System Generator to communicate with your design using a physical interface between the platform and the PC. This logic includes a memory map interface over which System Generator can read and write values to the input and output ports on your design. It also includes any platform-specific circuitry (e.g., DCMs, external component wiring) that is required for the target FPGA platform to function correctly.


Figure 10. Invoking the code generator

Hardware Co-Simulation Blocks

System Generator automatically creates a new hardware co-simulation block once it has finished compiling your design into an FPGA bitstream. A Simulink library is also created in order to store the hardware co-simulation block. At this point, you can copy the block out of the library and use it in your System Generator design as you would other Simulink and System Generator blocks.

Figure 11. Hardware Co-simulation

The hardware co-simulation block assumes the external interface of the model or subsystem from which it is derived. The port names on the hardware co-simulation block match the ports names on the original subsystem. The port types and rates also match the original design.

Figure 12. Hardware Co-simulation Library block


Hardware Co-Simulation Clocking

There are several ways in which a System Generator hardware co-simulation block can be synchronized with its associated FPGA hardware. In single-step mode, the FPGA is in effect clocked from Simulink, whereas in free-running clock mode, the FPGA runs off an internal clock, and is sampled asynchronously when Simulink wakes up the hardware co-simulation block.

Single-Step ClockIn single-step clock mode, the hardware is kept in lock step with the software simulation. This is achieved by providing a single clock pulse (or some number of clock pulses if the FPGA is over-clocked with respect to the input/output rates) to the hardware for each simulation cycle. In this mode, the hardware co-simulation block is bit-true and cycle-true to the original model.

Because the hardware co-simulation block is in effect producing the clock signal for the FPGA hardware only when Simulink awakens it, the overhead associated with the rest of the Simulink model's simulation, and the communication overhead (e.g. bus latency) between Simulink and the FPGA platform can significantly limit the performance achieved by the hardware. As a general rule of thumb, as long as the amount of computation inside the FPGA is significant with respect to the communication overhead (e.g. the amount of logic is large, or the hardware is significantly over-clocked,) the hardware will provide significant simulation speed-up.

Free-Running ClockIn free-running clock mode, the hardware runs asynchronously relative to the software simulation. Unlike the single-step clock mode, where Simulink effectively generates the FPGA clock, in free-running mode, the hardware clock runs continuously inside the FPGA itself.

In this mode, simulation is not bit and cycle true to the original model, because Simulink is only sampling the internal state of the hardware at the times when Simulink awakes the hardware co-simulation block. The FPGA port I/O is no longer synchronized with events in Simulink. When an event occurs on a Simulink port, the value is either read from or written to the corresponding port in hardware at that time. However, since an unknown number of clock cycles have elapsed in hardware between port events, the current state of the hardware cannot be reconciled to the original System Generator model. For many streaming applications, this is in fact highly desirable, as it allows the FPGA to work at full speed, synchronizing only periodically to Simulink.

In free-running mode, you must build explicit synchronization mechanisms into the System Generator model. A simple example is a status register, exposed as an output port on the hardware co-simulation block, which is set in hardware when a condition is met. The rest of the System Generator model can poll the status register to determine the state of the hardware.

Selecting the Clock ModeNot every hardware platform supports a free running clock. However, for those that do, the parameters dialog box for the hardware co-simulation block provides a means to select the desired clocking mode. You may change the co-simulation clocking mode before simulation starts by selecting either the Single stepped or Free running radio button under the Clocking etch box.


Figure 13. Clock source selection for hardware Co-simulation

Board-specific I/O Ports

FPGA platforms often include a variety of on-board devices (e.g., external memory, analog to digital converters, etc.) that the FPGA can communicate with. For a variety of reasons, it may be useful to form connections to these components in your System Generator models, and to use these components during hardware co-simulation. For example, if your board includes external memory, you may want to define the control and interface logic to this memory in your System Generator design, and use the physical memory during hardware co-simulation.

You can interface to these types of components by including board-specific I/O ports in your System Generator models. A board-specific port is a port that is wired to an FPGA pad when the model is compiled for hardware co-simulation. Note that this type of port differs from standard co-simulation ports that are controlled by a corresponding port on a hardware co-simulation block.


Figure 14. Board Specific IO for PMC UWB from Innovative Integration

A board-specific I/O port is implemented using special non-memory mapped gateway blocks that tell System Generator to wire the signals to the appropriate FPGA pins when the model is compiled into hardware. To connect a System Generator signal to a board-specific port, connect the appropriate wire to the special gateway (in the same way as is done for a traditional gateway.)

Non-memory mapped gateways that are common to a specific device are often packaged together in a Simulink subsystem or library. The Innovative Integration BSP, for example, provides a library of external device interface subsystems, including analog to digital converters, digital to analog converters, RocketIOs, and external memory. The interface subsystems are constructed using Gateways that specify board-specific port connections. These subsystems are treated like other System Generator subsystems during simulation (i.e., they perform double precision to Xilinx fixed-type conversions.) When System Generator compiles the design into hardware it connects the signals that are associated with the Gateways to the appropriate external devices they signify in hardware.


Installation Instructions

Before installing Innovative Integration Board Support Package, MATLAB/Simulink, Xilinx ISE, and System Generator need to be pre-installed and updated to the latest version. The software requirements for different products varies and are listed in the beginning of corresponding chapters.

The Board Support Package is in the folder <X5 root>\<product_name>\MATLAB\Rev#\BSP.

1. Open MATLAB.

2. Change the MATLAB directory to the folder containing “setup_<product_name>.m” file.

3. Type “setup_<product_name>” on the MATLAB command prompt.

4. Restart MATLAB.

Please be sure that the files under <X5 root>\<product_name>\MATLAB are not “read-only” before starting the design.

X5 400M BSP Installation

X5 400M BSP provides a library, locating in <Xilinx root>\DSP_Tools\sysgen\plugins\compilation\Hardware Co-Simulation\X5_400M_Rev#, targeted for Xilinx Virtex5 XC5VSX95T -1 ff1136 FPGA.

X5 210M BSP Installation

X5 210M BSP provides a library, locating in <Xilinx root>\DSP_Tools\sysgen\plugins\compilation\Hardware Co-Simulation\X5_210M_Rev#, targeted for Xilinx Virtex5 XC5VSX95T -1 ff1136 FPGA.


Design Flow

Start a New Design Using System Generator

Users should start the design by modifying “default.mdl” in <X5 root>\<product_name>\MATLAB\Rev#\Examples\default\, including the FrameWork logic components and default connections. The gateways wrapped in the II blocks need to be mapped in top level VHDL file in later compilation, so the II blocks should be included in every design. The design flow is described and illustrated as below.

1. Under MATLAB/Simulink environment, designers can build the project using Xilinx System Generator blockset. Simulate the project with the sources and sinks in Simulink and verify the functions.

2. Attach the logic to the hardware blocks using Innovative Integration library.

3. Compile the design and run hardware co-simulation with devices on the board.

4. Integrate the design into the logic, locating in <X5 root>\<product_name>\Logic\Rev#, as described in the next section.

Step 3 may be skipped if the logic is well simulated or having serious timing problem compiling with Jtag component.

Figure 15. Design flow chart


Start and Verify the design using Xilinx

Blocksets

Combine the designw ith peripheral

devices on boardHardw are Co-sim

II blocksets

Integrate the designinto logic

Solutions for Timing Problems

High timing score issue may still occur in the compilation. There are several solutions described as follows,

1. Buffer the signals to/from the FIFO.

2. Locate the timing problems using Xilinx “Timing Analyzer.” Use Timing Improvement Wizard to locate the error and eliminate the timing issues. Many problems are solved by simple pipelining of the logic using registers to reduce the number of logic levels and improve speed. Or avoid the combinatorial logic in the design. If there is any static path in the design, you can put a TIG constraint in the ucf file.

3. Rearrange the area constraints using Xilinx “Floorplanner.” The information from Timing Analyzer may give you an idea to improve the constraint.

The user constraint file can be found in <Xilinx root>\DSP_Tools\sysgen\plugins\compilation\Hardware Co-Simulation\<product_name_Rev#>\ <product_name>.ucf.

Figure 16. Xilinx Timing Analyzer


Figure 17. Xilinx Floorplanner


Integrate the Design into FPGA1. Remove all gateways from the design and replace them with constants. Select “NGC Netlist” in the System

Generator token and generate the “<project_name>_cw.ngc.”

Figure 18. X5 400M default example for FPGA implementation

Figure 19. Configuration of System Generator Token for ngc generation


2. Copy “<project_name>_cw.ngc” to the folder, <X5 root>\<product_name>\MATLAB\Rev#\Logic.

3. In <X5 root>\<product_name>\MATLAB\Rev#\Logic\source\<top_level>.vhd, change three places as shown in the figures below. Set generic option “implementation_logic” to 1 to generate a component for implementation. Then change the name of the component and make it consistent with the name of the ngc file.

(a)

(b)

(c)Figure 20. In the example, the gray areas need to be modified.

4. Click “Generate Programming File” in ISE Processes for bitstream.

Please refer to Xilinx System Generator v10.1.2 User Guide, “Importing a System Generator Design into a Bigger System” for more details.


Figure 21. In the example, the gray areas need to be modified.


Advanced Skills

Explore II BSP LIBII Board Support Package (BSP) is a powerful design tool based on II FrameWork Logic. Inside FrameWork Logic, the connections between components are for basic data acquisition and transmitting. To make a BSP, we broke the datapaths in the FrameWork Logic and inserted a new component, jtagcosim_top, in the top file. We created input/output ports for jtagcosim_top and connected them to the infrastructures for data exchange and controls. Then we packed these ports in Simulink and made interface blocks.

Figure 22. X5 400M library and the non-memory gateways under the mask


It is like making an empty black box in the FrameWork Logic as shown below. Users can design, simulate in MATLAB/Simulink environment using Xilinx System Generator, and the result is bit true and cycle true. To fill the empty black box, users need to connect the design with II blocks and follow the procedures.

Figure 23. Relationship of FrameWork Logic and jtagcosim_top

For hardware co-simulation, you will generate a bitstream that you can run the design in FPGA and interact with Simulink. Double-click on the System Generator token, choose the compilation target, and generate a bitstream for hardware co-simulation. You can choose XFLOW options files to have more controls in the compilation. The files provided by II are in <Xilinx_root>\DSP_Tools\sysgen\plugins\compilation\Hardware Co-Simulation\X5_400M\balanced_jtag.opt.

In MATLAB command window, you need to give ts a value for compilation. If the system is running at 200 MHz, so please type “ts=1/200e6;”.

Figure 24. Configuration of the token and XFLOW options


FrameWork Logic

MATLAB/Simulink

The Simulink/System Generator design becomes a “.ngc” file and merges with the other “.ngc” file generated from FrameWork Logic in NGDBUILD, as shown in the following picture.

Figure 25. Compilation flow

If the project is compiled without any timing problem, a hardware co-simulation block and a bit file are generated in the target folder. We can create signal sources from Simulink toolbox and send them to FPGA through jtag cable.

Figure 26. Generated bitstream for hardware co-simulation


Figure 27. Project for hardware co-simulation

Open the hwcosim block and set the clock in free running mode. If you are running the example, please check if the bitstream path is correct. Now you can click the play button and run co-simulation with the hardwares on the board.

Figure 28. Settings for hardware co-simulation block

Because the machine generated jtag interface may cause timing problems in the compilation, users can choose to skip hardware co-simulation and implement the design in the FrameWork Logic. You can follow the descriptions in Chapter 3 “Integrate the Design into FPGA” and generate a standalone bitstream for FPGA.


Modify the Library and Change Configurations in SimulinkSystem can be configured by writing the control registers through MATLAB/Simulink. The advantage is that FPGA can run hardware co-simulation without using host software. The disadvantage is that a compilation is necessary whenever the settings are changed. If users want to have the ability to change the configuration on the fly, there is a simple way to do it.

In the UWB Simulink project, right click on the “System Configuration” block. Disable the link to the library and look under the mask, as shown in the figures below. If you are interested in adjusting the value of adc0_gain on the fly, break the connection between the subsystem “adc0_gain” and Mux4. Add a “Gateway In” and setup the bit width and period. This new gateway will be synthesized as a port in the hardware co-simulation. If you are interested in monitoring a static signal, it can be done by adding a “Gateway Out” on the signal. Restricted by the speed of the Jtag cable, you need to use either SRAM or shared memory to watch the fast-changing signal in the Simulink.

Figure 29. Project block diagram


Figure 30. Block diagram of System Configuration block

Figure 31. Write registers by adding a “Gateway In.”


Add Extra Ports to FrameWork LogicIf you are not doing hardware co-simulation, it is possible to add extra ports to FrameWork Logic.

1. Connect the project with II blocks and remove all memory map gateways used by MATLAB/Simulink. Then add the new yellow gateways that you want to be new IO ports of component “<project_name>_cw” in FrameWork Logic. Select “NGC Netlist” in the System Generator token and generate the “<project_name>_cw.ngc.”

2. Copy “<project_name>_cw.ngc” to the folder, <X5 root>\<product_name>\Logic\Rev#\ipcores.

3. In <X5 root>\<product_name>\MATLAB\Rev#\Logic\source\<top_level>.vhd, find component “<project_name>_cw” and instance “inst_matlab_project” and change the input/output ports according to the change in step 1. You need to make corresponding changes in the top file or infrastructures source codes, locating in <X5 root>\<product_name>\Logic\RevB\source folder.

4. Click “Generate Programming File” in ISE Processes for bitstream.


II DSP LIB

Software Prerequisites

You must have the following software installed before installing II DSP LIB.

● Microsoft Windows XP Professional

● One of the following versions of MATLAB from The MathWorks Inc.:

1. MATLAB R2007b v7.5/Simulink v7.0.1

● Xilinx System Generator v10.1.2

● Xilinx ISE Foundation v10.1.02 (Service Pack 2) or later, along with the full version of the ISE Simulator.

● Xilinx ISE 10.1.02 CORE Generator IP Update 2


Component Description

Overview

This library provides reference designs for projects. They are built using black box in System Generator and may be good examples showing that how to write a VHDL code and how to import IP cores from Xilinx Core Generator. The library folder is in C:\Innovative\Sysgen\II_DSP_LIB.

Figure 32. Blocks in II DSP LIB


ii_data_mover

This component moves data between FIFOs. It moves data when source FIFO read count is larger than 3 and destination FIFO write count is smaller than the threshold.

Figure 33. ii_data_mover component

Figure 34. ii_data_mover panel

Pin Direction Function

reset In Reset

din In Data in. Data width is auto-detected and assigned.

src_rdcnt In Source FIFO read count. Data width is auto-detected and assigned.

dest_wrcnt In Destination FIFO write count. Data width is auto-detected and assigned.



dout Out Data out

valid Out Data valid

src_rd Out Read strobe to source FIFO.

Table 3. ii_data_mover Logic Ports

ii_flow_ctrl

This component moves data between FIFOs. It has two modes, which are bleed mode and drip mode. It can empty the last point by watching src_empty flag in the slower drip mode. Port “src_rdcnt” and “dest_wrcnt” data width is auto-detected and assigned. The “Destination FIFO Almost Full Threshold” can be changed for different size FIFO to make the decision when to stop reading.

Figure 35. ii_flow_ctrl component

Figure 36. ii_flow_ctrl panel



reset In Reset

src_rdcnt In Source FIFO read count. Data width is auto-detected and assigned.

src_empty In Source FIFO empty flag.

dest_wrcnt In Destination FIFO write count. Data width is auto-detected and assigned.

src_rd Out Read strobe to source FIFO.

Table 4. ii_flow_ctrl Logic Ports

ii_splitter and ii_joiner

Splitter splits incoming data stream into two channels for parallel processing. The input data stream is split into sets of consecutive data points, resulting in each data stream having half the data rate of the input stream.

Joiner joins the data from two parallel data channels. This component is used to reassemble data streams from parallel processing paths and make it a consecutive data stream for the next stage.

Joiner paces the data flow using “dest_rdy” from the destination and “dest_fifo_af” to the source. Unless there is a decimation algorithm in the design, size of data stream for each channel needs to be the same in splitter and joiner.

Figure 37. ii_splitter and ii_joiner component


Figure 38. ii_splitter and ii_joiner panel


reset In Reset

din[31:0] In Input data

wr In Write strobe for din[31:0]

dout1[31:0] Out Output data to the first channel

dout2[31:0] Out Output data to the second channel

valid1 Out Data valid signal for dout1[31:0]

valid2 Out Data valid signal for dout2[31:0]

Table 5. ii_splitter Logic Ports


reset In Reset

din1[31:0] In Input data from channel one FIFO

din2[31:0] In Input data from channel two FIFO

wr1 In Write strobe for din1[31:0]



wr2 In Write strobe for din2[31:0]

rd_cnt1[9:0] In Read count signal from channel one FIFO

rd_cnt2[9:0] In Read count signal from channel two FIFO

dest_rdy In Destination FIFO ready signal

dout[31:0] Out Output data

valid Out Output data valid signal

rd1 Out Read strobe for din1[31:0]

rd2 Out Read strobe for din2[31:0]

dest_fifo_af Out Almost full signal of destination FIFO

Table 6. ii_joiner Logic Ports

ii_shifter

This component shifts the 32 bits data toward MSB or LSB using ports “direction” and “num_shift.” Port “direction” is a Boolean doing left shift when it is high. Port “num_shift” is a 5 bits unsigned input for how many bits to be shifted.

Figure 39. ii_shifter component



reset In Reset

direction In Shift direction'1' => left shift,'0' => right shift.

num_shift[4:0] In Number of bits to shift



Table 7. ii_shifter Logic Ports

ii_divider

This component is doing division by simply subtracting divisor from dividend every clock cycle. The widths of dividend, divisor, quotient, and remainder are 32 bits.

Figure 40. ii_divider component


reset In Reset

dividend[31:0] In Dividend

wt In Write strobe of dividend



divisor[31:0] In Divisor

quotient[31:0] Out Quotient

remainder[31:0] Out Remainder

valid Out Valid signal

Table 8. ii_divider Logic Ports

ii_burst256

This component bursts 256 points when source FIFO has 256 points available for read. Width of “src_rdcnt” is auto-detected and assigned.

Figure 41. ii_burst256 component


reset In Reset

src_rdcnt In Source FIFO read count

src_rd Out Source FIFO read signal

Table 9. ii_burst256 Logic Ports


Virtex5 Asymmetric FIFO

The asymmetric FIFOs are used to convert input data to a different width on the other side. It is good for some applications requiring continuous data stream.

Figure 42. Virtex5 Asymmetric FIFO component

Xilinx document ug175.pdf says: “Example below is a FIFO with a 1:4 aspect ratio (write width = 2, read width = 8). In this figure, four consecutive write operations are performed before a read operation can be performed. The first write operation is 10, followed by 11, 00, and finally 01. The memory is filling up from the right to the left (LSB to MSB). When a read operation is performed, the received data is 01_00_11_10.”

Figure 43. FIFO with a 1:4 aspect ratio

On p.69 of ug 175.pdf, it says: “Example shows a FIFO with an aspect ratio of 4:1 (write width of 8, read width of 2). In this example, a single write operation is performed, after which four read operations are executed. The write operation is 11_00_01_11. When a read operation is performed, the data is received left to right (MSB to LSB). As shown, the first read results in data of 11, followed by 00, 01, and then 11.”


Figure 44. FIFO with a 4:1 aspect ratio


reset In Reset

din In Data in.

wr In Input data write strobe

rd In Output data read strobe

dout Out Data out


empty Out FIFO empty flag

full Out FIFO full flag

rd_cnt Out FIFO read count

wr_cnt Out FIFO write count

Table 10. Virtex5 Asymmetric FIFO Logic Ports


X5 400M Board Support Package


You must have the following software installed before installing the Board Support Package.







Note: Please find a compatible version of MATLAB and System Generator in the link. http://www.xilinx.com/ise/optional_prod/system_generator.htm

Note: The Microsoft Windows environment variable $XILINX must be set and point to your ISE software installation directory. ISE software service packs may be downloaded from the Software Updates Center.



Overview

The block diagram below shows hardware structure inside FPGA. The blue components are infrastructures for communication with onboard devices, such as DDR, QDR, ADC, DAC. The white block is MATLAB/Simulink component allowing us to do graphical design and hardware co-simulation. The green blocks are II blocks to talk to the infrastructures. Your design can be built and simulated using Xilinx System Generator. Then you can put the project on the datapath and use the interface component as required. The whole design can be compiled to a bitstream, downloaded to FPGA, and simulated with hardware. After the design is verified in hardware co-simulation, jtag gateways can be removed and the project can be synthesized as a stand alone logic in the hardware.

Figure 45. X5 400M block diagram


QDR SRAM

PCIE

deframer Digital IO/Serial RapidIO

DDR2Queue 0

Alert

DDR2Queue 1

32

64

DACSPI

Trigger

128

128

64 FIFO32i16o

Offset/gain

Offset/gain

DAC1

Trigger

FIFO32i16o

FIFO32i32o

FIFO32i32o

Offset/gain

Offset/gain

Offset/gain

Offset/gain

Offset/gain

Offset/gain

DAC0

ADC1

ADC0

32

32

16

16

32

32

PCIEINTF

DDRQueue 0

DDRQueue 1

ADC0

ADC1

DAC0

DAC1

QDRSRAM

User Design

MATLAB/Simulink

Packetizer

ADC INTF

This component sends out data after triggering at sample clock and error correction. Settings, such as software trigger, are from Simulink when “en_config = 1” in System Configuration block. Test ramp is enabled when “test = 1” for both ADC channels. Data sampled at time t is put in data(31 downto 16), and data sampled at time t+1 is put in data(15 downto 0).

data(31 downto 16) = adc(t);data(15 downto 0) = adc(t+1);

The configuration panel in “ADC0 INTF” block provides the controls to trigger, enable frame mode, and calibrations without host software. When “Use External Trigger” is checked, trigger from SYNC port is used as ADC/DAC trigger. When “Trigger Type” is set to “Level,” ADC samples data when trigger is high. When “Trigger Type” is set to “Positive Edge,” ADC samples data after the first positive edge of trigger.

There is an embedded flow control for ADC interface. For example, you can use destination FIFO “not empty” flag as dest_rdy for adc0_intf; or you can watch the destination FIFO “write count” and send a ready flag when the count is less than a threshold.

Figure 46. ADC INTF component

Figure 47. ADC 0 INTF Panel



test In Test ramp enable

trig In Software trigger

dest_rdy In Destination ready

data[31:0] Out Input data


Table 11. ADC INTF Logic Ports

DAC INTF

This component is passing data for triggering at sample clock and error correction. Settings, such as software trigger, are from Simulink when “en_config = 1” in System Configuration block. Test signal is enabled when “test = 1” for both DAC channels. Port “test mode = 0” enables a ramp, and “test mode = 1” enables a sine wave generator.

Ports "phase_inc0" and "phase_inc1" are the phase increment for the dual tone sine wave generator.

phase_inc = output frequency * 2^24 / dac_ref_clk;

data(31 downto 16) = dac(t);data(15 downto 0) = dac(t+1);

The configuration panel provides the controls for calibration and enable frame mode without host software. When “Use External Trigger” is checked, trigger from SYNC port is used as ADC/DAC trigger. When “Trigger Type” is set to “Level,” ADC samples data when trigger is high. When “Trigger Type” is set to “Positive Edge,” ADC samples data after the first positive edge of trigger. Data can be sent with a valid signal by watching the level of ready flag.

Figure 48. DAC INTF component


Figure 49. DAC 0 INTF panel


test In Software trigger

test_mode[1:0] In Test signal select'0' => ramp;'1' => sine wave

phase_inc[23:0] In Phase incrementphase_inc = output_freq * 2^24 / dac_ref_clk


data[31:0] In Output data

wr In Write strobe



rdy Out FIFO is ready for incoming data

Table 12. DAC INTF Logic Ports

DDR INTF

In X5-400M, two 256 MByte queues of virtual FIFO have been implemented. Each queue is independently managed and is essentially a large data FIFO for each ADC and DAC data flow. For the 128 bits “din” and “dout” ports, the first 16 bits data should be aligned to the MSB, and the last data is aligned to LSB as follows. The queues can be used for any purpose. In the FrameWork Logic, the queues are used to buffer the incoming data from ADCs and outgoing data to the DACs.

din(127 downto 112) = data(t);din(111 downto 96) = data(t+1);din( 95 downto 80) = data(t+2);din( 79 downto 64) = data(t+3);din( 63 downto 48) = data(t+4);din( 47 downto 32) = data(t+5);din( 31 downto 16) = data(t+6);din( 15 downto 0) = data(t+7).

Figure 50. DDR INTF component



wr In Write strobe



rd In Read strobe



ofifo_rdcnt[9:0] Out Output FIFO read count

ofifo_empty Out Output FIFO empty flag

ofifo_aempty Out Output FIFO almost empty flag

ififo_wrcnt[9:0] Out Input FIFO write count

ififo_rdy Out Input FIFO ready signal

Table 13. DDR INTF Logic Ports

ii_interleaver

This component interleaves incoming 32 bits data from two input channels as follows.

channel_en(0) = 1 => channel 0 is enable;channel_en(1) = 1 => channel 1 is enable. Both channels are enabled. At time = t, din0(31 downto 0) is [a | b]; din1(31 downto 0) is [c | d]. At time = t+1, din0(31 downto 0) is [e | f]; din1(31 downto 0) is [g | h]. At time = t+2, dout(127 downto 0) is [c | a | d | b | g | e | h | f]. Only one channel is enabled. At time = t, din0(31 downto 0) is [a | b]; din0(31 downto 0) is [c | d]. At time = t+1, din0(31 downto 0) is [e | f]; din0(31 downto 0) is [g | h]. At time = t+2, dout(127 downto 0) is [a | b | c | d | e | f | g | h].


Figure 51. ii_interleaver component


reset In Reset

ch_en[1:0] In Channel enable; bit 0 is for channel 0 and bit 1 is for channel 1.

din[31:0] In Data in

wr In Write strobe

dout[127:0] Out Data out


Table 14. ii_interleaver Logic Ports

ii_deinterleaver

This component deinterleaves incoming 128 bits data to two output channels as follows.

channel_en(0) = 1 => channel 0 is enable;channel_en(1) = 1 => channel 1 is enable. Both channels are enabled. At time = t, din(127 downto 0) is [a | b | c | d | e | f | g | h]. At time = t+1, dout0(31 downto 0) is [b | d]; dout1(31 downto 0) is [a | c]. At time = t+2, dout0(31 downto 0) is [f | h]; dout1(31 downto 0) is [e | g]. Only one channel is enabled.


At time = t, din(127 downto 0) is [a | b | c | d | e | f | g | h]. At time = t+1, dout0(31 downto 0) is [a | b]. At time = t+2, dout0(31 downto 0) is [c | d]. At time = t+3, dout0(31 downto 0) is [e | f]. At time = t+4, dout0(31 downto 0) is [g | h].

Figure 52. ii_deinterleaver component


reset In Reset

ch_en[1:0] In Channel enable; bit 0 is for channel 0 and bit 1 is for channel 1.


src_empty In Source FIFO empty flag

src_aempty In Source FIFO almost empty flag



rd Out Source data read strobe

Table 15. ii_deinterleaver Logic Ports


ii_reorder

This component is used to re-order the data for little-endian system. It is usually used in front of packetizer to rearrange the data for little-endian system.

When both channels are enabled, input data is [data1(t) | data0(t) | data1(t+1) | data0(t+1)]. Output data is [data1(t) | data0(t) | data1(t+1) | data0(t+1)].

When one channel is enabled, input data is [data0(t) | data0(t+1) | data0(t+2) | data0(t+3)]. Output data is [data0(t+1) | data0(t) | data0(t+3) | data0(t+2)].

Figure 53. ii_reorder component

Figure 54. ii_reorder panel



dout[63:0] Out Output

Table 16. ii_reorder Logic Ports


ii_packetizer

This component packetizes the incoming data with a header, including packet ID and packet size. The packetizer will collect enough data according to the packet size from one channel, packetize the data with header, and move to the next enabled channel. Currently, channel 0 is reserved to alert component. If we look under the mask, the packetizer is instantiated as a Xilinx System Generator black box. The corresponding files are located in <Xilinx root>\DSP_Tools\sysgen\plugins\compilation\Hardware Co-Simulation\X5_400M_Rev#\ii_packetizer_config.m and C:\Innovative\Sysgen\II_DSP_LIB\vhdl\X5\ii_packetizer.vhd. More sophisticated packet system can be made by changing the vhdl code and m file. Details can be found in Xilinx System Generator Help by typing “Black Box.” Be aware to keep all the yellow gateways, which are the input/output non-memory map ports to the top FrameWork Logic file.

Figure 55. ii_packetizer component


Figure 56. ii_packetizer under the mask


reset In Reset


src_rdcnt[15:0] In Source FIFO read count

dest_wrcnt[15:0] In Destination FIFO write count



src_rd Out Read strobe for source FIFO

Table 17. ii_packetizer Logic Ports


PCI Express INTF

PCIE TX component sends packets to the host through PCI Express interface and RX component deframes the data from PCI Express interface. The input and output data width is 64 bits, and the input FIFO write count and destination FIFO count are 16 bits wide. You need to concat or slice the FIFO count to be equal to 16 bits wide to avoid error.

For the PCIE_RX_INTF data, the order is as follows.

din(63 downto 48) = data(t);din(47 downto 32) = data(t+2);din(31 downto 16) = data(t+3);din(15 downto 0) = data(t+4).

Figure 57. PCIE INTF component

Figure 58. PCIE RX INTF panel



wr In Write strobe



wrcnt[15:0] Out Input FIFO write count

Table 18. PCIE TX Logic Ports




dest_cnt[15:0] In Destination FIFO write count

Table 19. PCIE RX Logic Ports

QDR SRAM INTF

This component is an interface between user's logic and the external QDR II SRAM. Samples captured from the logic can be stored in SRAM for further signal analysis using MATLAB or used as part of the application logic for data buffering. The 4 MB memory gives very powerful signal analysis capabilities to the board for real-time data buffering for MATLAB or application logic.

There are three addresses. Ports “wr addr” and “rd addr” are for MATLAB/Simulink read/write in slow mode; another “address” is in the ii_sram_intf.vhd for fast read/write in real-time. SRAM uses “wr addr” and “rd addr” when “fast_mode='0'” and “address” when “fast_mode='1'.” Due to the limited bandwidth of Xilinx JTAG pod, MATLAB can only read/write using slower jtag clock and “wr addr” and “rd addr.” If real-time read/write is required, “wr” and “rd” is connected to the data valid of the incoming data, and the address increases with system clock. So fast data logging and playback can be accomplished.

SRAM interface provides address and data control with specific support for MATLAB use. Port “wr addr” and “rd addr” and “end_addr” provide the flexibility to read/write a specific chunk of data in SRAM. Port “fast_mode” allows SRAM to be accessed with FPGA system clock. Port “rollover” provides the function to wrap the address back to 0 when “end_addr” is reached, thus providing a circular buffer.


Figure 59. QDR SRAM INTF component


fast mode In Fast mode select'1' => use “address” in ii_sbsram_intf.vhd'0' => use “wr addr” and “rd addr”

rollover In In fast mode, SRAM address wraps back to zero if rollover is '1'

end addr[17:0] In End address is a reference to rollover SRAM address in fast mode

wr addr[17:0] In SRAM address for MATLAB slowly write back through JTAG device

rd addr[17:0] In SRAM address for MATLAB slowly read back through JTAG device

din0[31:0] In Input data to SRAM


wr In Write strobe

rd In Read strobe

dout0[31:0] Out Output data from SRAM





Table 20. SRAM INTF Logic Ports

DAC SPI INTF

This component is an SPI port interface to the TI DAC5687. DAC5687 is configured prior to operation for data modes, clock configurations and other initialization steps over this SPI port. MATLAB/Simulink provides an easy way to configure registers by editing vectors in MATLAB “Workspace” and send them through SPI interface. There is a “dac_pll.m” file in every example folder for the simple PLL configuration. In MATLAB “Command Window,” please type

[spi_addr, spi_data, spi_wr]=dac_pll( ref_clk, interpolation ),

where “ref_clk” is the clock source from on board crystal or external clock; and interpolation can be 1, 2, 4 to match the input data rate plllock (dac_clk), which is basically the same as ref_clk, and output sample rate (Fdac) of DAC5687. There are some examples in the following table. More complicated operations can be done by changing the register values through the SPI interface. Please download the datasheet for advanced applications. (http://focus.ti.com/docs/prod/folders/print/dac5687.html )

Command Fdac (MHz) dac_clk (MHz) interpolation

[spi_addr, spi_data, spi_wr]=dac_pll( 125, 1 ) 125 125 1



Table 21. Commands for DAC SPI INTF

Figure 60. DAC SPI INTF component


http://focus.ti.com/docs/prod/folders/print/dac5687.html


addr[4:0] In SPI address

data[7:0] In SPI data

wr In Write strobe

Table 22. DAC SPI INTF Logic Ports

Digital IO

This component is a simple digital IO port that has an input register and output register. It may be used as a simple digital control port or easily customized. Port “dio_en” controls a mux to use data from the software or MATLAB/Simulink project. The 16 bit “rx_data” is connected to a register, which is written when “rd” is low. “tx_data” writes the output register when “wr” is high. The source VHDL is available in <X5 root>\400M\Logic\Rev#\source\ii_dio.vhd.

Figure 61. DIO component


dio_en In '1' => data from MATLAB'0' => data from software

tx_data[15:0] In Transmitted data

ctrl[1:0] In Input/output direction controlctrl(0) = '1' => ud( 7 downto 0 ) is an outputctrl(1) = '1' => ud( 15 downto 8 ) is an output

wr In Write strobe for tx_data



rd In Read strobe for rx_data

rx_data[15:0] Out Received data

Table 23. Digital IO Logic Ports

System Configuration

This component provides communication with the host computer and allows controls from ctl_reg44~47 and read data back through status44~47. Port “en_config” enables the settings, such as test, test mode, gain/offset, and DAC SPI interface, from Simulink environment. If “en_config = 0,” all the settings are from the host software. This port provides the possibility to work without supports from software in logic development.

Using “clk_sel,” users can use the onboard crystal or external clock as ADC/DAC sample clock. Port “clk_locked” shows DCM is locked and DDR, QDR are ready to be used. Port “sys_reset” provides system reset to Simulink components. When “adc_run” or “dac_run” is low, “sys_reset” is high. You can generate a reset for every run from software. Port “init_reset” provides a one time reset after the FPGA is loaded. Port “ext_sync” makes it possible to use external trigger in the MATLAB project.

On the panel, ADC sample clock can be sent to SYNC port for debug purpose, or use SYNC port as an external trigger input.

Figure 62. System Configuration component


Figure 63. System Configuration panel


clk_sel In Clock select'0' => external clock;'1' => 125 MHz onboard clock.

en_config In Enable Configuration from Simulink'1' => From Simulink;'0' => From the host.

status44[31:0] In status_reg(44) to PCI Express interface




clock_locked Out Clock locked signalsys_clk, ddr_ref_clk, ddr2_dcm, qdr0_dcm, qdr1_dcm are locked.

temp Out Temperature dataTemperature = temp * 0.492 - 273.15

sys_reset Out Reset is high if adc_run or dac_run is low.



init_reset Out Reset after loading the FPGA

ext_sync Out External trigger

ctl_reg44[31:0] Out ctl_reg(44) from PCI Express interface




Table 24. System Configuration Logic Ports


Examples

All the examples are available at <X5 root>\400M\MATLAB\Rev#\Examples.

File name (.mdl) Contentsx5_400m_default This example shows standard connections in FrameWork Logic for data acquisition.

fir_loopback This example shows data loopbacked from ADC to DAC through a FIR lowpass filter.

user_design This example shows explains where and how to place an user's application.

Table 25. MATLAB Examples for X5 400M

On X5 400M board, users need to run “dac_pll.m” to generate PLL setting for DAC SPI interface. Please type “[spi_addr, spi_data, spi_wr]=dac_pll(125,1);” in MATLAB Command Window to generate a configuration. Please read Component Description\DAC SPI INTF for more details. Users can edit vectors in “dac_pll.m” and send them through SPI interface for different applications.

After loading the generated bit file through Xilinx Jtag pod, the FPGA is free running at system clock. You need to restart the computer or re-enumerate the board in Windows “Device Manager” to enable PCI Express connection. After rebooting the machine, please run hardware cosimulation with “Skip device configuration” checked as figure shown below. So it won't load the logic again and kill the PCI Express connection.

Figure 64. Xilinx Jtag pod configuration

To use the settings from Simulink environment, please make sure that “en_config = '1'.” To give controls back to the host software, please set “en_config = '0'.”


Example: x5_400m_default.mdl

This example shows standard connections in FrameWork Logic. The 32 bits ADC 0 and ADC 1 data is interleaved and sent to DDR queue 0 for data buffering. The data out of queue 0 goes through an asymmetric FIFO and packetized for PCIE_TX_INTF. Data movements between FIFOs are flow controlled by “ii_flow_ctrl” or data valid strobe.

Data from the host is removed header and sent to MATLAB component through PCIE_RX_INTF, buffered in DDR queue 1, and deinterleaved as two 32 bits data for DAC 0 and DAC 1.

The project is actually a component in FrameWork Logic, and the board support package interface blocks are wrappers for the input/output ports. So most of the components are necessary to be instantiated in the compilation. For example, you need to keep “System_Configuration,” “ADC0/1_INTF,” “DAC0/1_INTF,” “DDR_Queue_0/1,” “ii_packetizer,” “PCIE_TX/RX_INTF,” “SRAM0/1_INTF,” “DIO_INTF,” “DAC_SPI_INTF.” You can remove “ii_interleaver,” “ii_deinterleaver,” “ii_flow_ctrl,” “ii_reorder,” “V5_FIFO.” The rest yellow gateways will become jtag ports exchanging data between MATLAB/Simulink and FPGA in hardware co-simulation.

Figure 65. Block diagram of default example

After building a project, you need to double-click on the System Generator token, choose the compilation target, and generate a bitstream for hardware co-simulation. You can choose XFLOW options files to have more controls in the compilation.


The files provided by II are in <Xilinx root>\DSP_Tools\sysgen\plugins\compilation\Hardware Co-Simulation\X5_400M\balanced_jtag.opt.

In MATLAB command window, you need to give ts a value for compilation. Currently the system is running at 200 MHz, so please type “ts=1/200e6;”.





Example: fir_loopback.mdl

In this example, a signal from ADC0_INTF is loopbacked through a lowpass filter to DAC0_INTF. ADC/DAC sample rate is 125 MHz and system clock is 200 MHz. The 32 bits ADC data is converted to 16 bits using a asymmetric FIFO for digital signal processing. It is converted to 32 bits data again for DAC0_INTF. The flow control is done by using ii_flow_ctrl and FIFO write count.

Figure 70. Block diagram of fir_loopback example

The filter is designed using MATLAB FDATool like the following picture. The passband of the frequency response is 3 MHz and the stopband is 8 MHz. The coefficients are passed to “FIR Compiler v3_2” by filling “xlfda_numerator('FDATool')” as coefficient vector. The output of “FIR Compiler v3_2” is 32 bits, and the slice block helps to determine the location of MSB to get the best precision. It shows the possibility to use the powerful tool in FPGA design for now and the future.

Figure 71. Filter coefficients generated in MATLAB FDATool


A simple experiment can be done using this example. We connect a function generator on ADC0 and an oscilloscope on DAC0. The generated sine wave starts from 1 MHz and the frequency is increased steadily to 8 MHz. On the scope, the amplitude should be gradually attenuated by the filter.

Figure 72. DAC0 output on the oscilloscope


Example: user_design.mdl

This example implements a parallel processing feature on the datapath of ADC0. Splitter shuffles the data to two channels according to the size on the panel, and Joiner collects data from two source FIFOs and joins the data to one channel output.

Figure 73. Block diagram of user_design.mdl

The experiment is done to check the data quality through the parallel processing structure. In hardware co-simulation, set “en_config = '1'” and load the bitstream to the FPGA. Restart the PC or re-enumerate the board in Windows “Device Manager.” Open SNAP and enable test counter. Snap the data to Binview. The incrementing ramp should be consecutive.

Four 32 bits control registers provide extra controls from the host software. Four 32 bits status registers receive data from the project for any purpose. The control registers are hooked up to status registers in the default example. We can write the control register 44 in example software Wave “Debug page” and see the correct value read back through status register 44 in the following picture.

Figure 74. Write/read to ctl_reg44 through X5-400 Wave


Figure 75. Write/read to ctl_reg44 through X5-400 Wave

Figure 76. Value read back of ctl_reg44 in MATLAB/Simulink


X5 210M Board Support Package


You must have the following software installed before installing the Board Support Package.







Note: Please find a compatible version of MATLAB and System Generator in the link. http://www.xilinx.com/ise/optional_prod/system_generator.htm

Note: The Microsoft Windows environment variable $XILINX must be set and point to your ISE software installation directory. ISE software service packs may be downloaded from the Software Updates Center.



Overview

The block diagram below shows hardware structure inside FPGA. The blue components are infrastructures for communication with onboard devices. The white block is MATLAB/Simulink component allowing users to do graphical design and simulations. The green blocks are II blocks talking to the infrastructures. Your design can be put on the datapath and utilize the powerful tools from Xilinx and Mathworks for DSP algorithm simulation and hardware cosimulation, as shown in the purple block. The whole design can be done in several steps and realized in the hardware. Please refer to Chapter 3 and 4 for more details.

Figure 77. X5 210M block diagram


QDR SRAM

PCIE

DDR2VFIFO

Alert32

128

64Trigger

FIFO16i16o

Offset/gain

ADC0

16 16

PCIEINTF

DDRVFIFO

ADC0

ADC1

SRAMINTF

User Design

MATLAB/Simulink

ADC2

ADC3

32 FIFO16i16o

Offset/gain

ADC1

16

32 FIFO16i16o

Offset/gain

ADC2

16

32 FIFO16i16o

Offset/gain

ADC3

16

Digital IO/Serial RapidIO

packetizer

X5-210M

ADC INTF

This component sends out data after triggering at sample clock and error correction. Settings, such as software trigger, are from Simulink when “en_config = 1” in System Configuration block. Test ramp is enabled when “test = 1” for all ADC channels.

The configuration panel in “ADC0 INTF” block provides the controls to trigger, enable frame mode, and calibrations without host software. When “Use External Trigger” is checked, trigger from SYNC port is used as ADC trigger.

There is an embedded flow control for ADC interface. For example, you can use destination FIFO “not empty” flag as dest_rdy for adc0_intf; or you can watch the destination FIFO “write count” and send a ready flag when the count is less than a threshold.

Figure 78. ADC INTF component

Figure 79. ADC 0 INTF Panel


test In Test ramp enable




dest_rdy In Destination ready



Table 26. ADC INTF Logic Ports

DDR INTF

In X5-210M, one 512 MByte queue of virtual FIFO has been implemented. For the 128 bits “din” and “dout” ports, the first 16 bits data should be aligned to the MSB, and the last data is aligned to LSB. The queue can be used for any purpose. In the FrameWork Logic, the queue is used to buffered the interleaved data from ADC channels.

din(127 downto 112) = data(t);din(111 downto 96) = data(t+1);din( 95 downto 80) = data(t+2);din( 79 downto 64) = data(t+3);din( 63 downto 48) = data(t+4);din( 47 downto 32) = data(t+5);din( 31 downto 16) = data(t+6);din( 15 downto 0) = data(t+7).

Figure 80. DDR INTF component



wr In Write strobe



rd In Read strobe



ofifo_rdcnt[10:0] Out Output FIFO read count

ofifo_empty Out Output FIFO empty flag

Table 27. DDR INTF Logic Ports

ii_interleaver_210m

This component stacks incoming data and make it interleaved data format at the input of VFIFO, suitable for host software.

All four channels are enabled. At time = t, din0(15:0) = [a]; din1(15:0) = [b]; din2(15:0) = [c]; din3(15:0) = [d]. At time = t+1, din0(15:0) = [e]; din1(15:0) = [f]; din2(15:0) = [g]; din3(15:0) = [h]. At time = t+2, dout(127:0) is [d | c | b | a | h | g | f | e].

Two channels are enabled. At time = t, din0(15:0) = [a]; din1(15:0) = [b]; At time = t+1, din0(15:0) = [c]; din1(15:0) = [d]; At time = t+2, din0(15:0) = [e]; din1(15:0) = [f]; At time = t+3, din0(15:0) = [g]; din1(15:0) = [h]; At time = t+4, dout(127:0) is [b | a | d | c | f | e | h | g].

Only one channel is enabled. At time = t, din0(15:0) is [a]. At time = t+1, din0(15:0) is [b]. At time = t+2, din0(15:0) is [c]. At time = t+3, din0(15:0) is [d]. At time = t+4, din0(15:0) is [e]. At time = t+5, din0(15:0) is [f]. At time = t+6, din0(15:0) is [g]. At time = t+7, din0(15:0) is [h]. At time = t+8, dout(127:0) is [a | b | c | d | e | f | g | h].


Figure 81. ii_interleaver_210m component


reset In Reset

ch_en[3:0] In Channel enable;bit 0 is for channel 0;bit 1 is for channel 1;bit 2 is for channel 2;bit 3 is for channel 3.


wt In Write strobe



Table 28. ii_interleaver_210m Logic Ports

ii_reorder

This component is used to re-order the data for little-endian system. It is usually used in front of packetizer to rearrange the data for little-endian system.


When all channels are enabled, input data is [data1(t) | data0(t) | data1(t+1) | data0(t+1)]. Output data is [data1(t) | data0(t) | data1(t+1) | data0(t+1)].

When one or two channels are enabled, input data is [data0(t) | data0(t+1) | data0(t+2) | data0(t+3)]. Output data is [data0(t+1) | data0(t) | data0(t+3) | data0(t+2)].

Figure 82. ii_reorder component

Figure 83. ii_reorder panel



dout[63:0] Out Output

Table 29. ii_reorder Logic Ports

ii_packetizer

This component packetizes the incoming data with a header, including packet ID and packet size. The packetizer will collect enough data according to the packet size from one channel, packetize the data with header, and move to the next enabled channel. Currently, channel 0 is reserved to alert component. If we look under the mask, the packetizer is instantiated as a Xilinx System Generator black box. The corresponding files are located in <Xilinx root>\DSP_Tools\sysgen\plugins\compilation\Hardware Co-Simulation\X5_210M_Rev#\ii_packetizer_config.m and C:\Innovative\Sysgen\II_DSP_LIB\vhdl\X5\ii_packetizer.vhd. More sophisticated packet system can be made by changing


the vhdl code and m file. Details can be found in Xilinx System Generator Help by typing “Black Box.” Be aware to keep all the yellow gateways, which are the input/output non-memory map ports to the top FrameWork Logic file.

Figure 84. ii_packetizer component

Figure 85. ii_packetizer under the mask



reset In Reset


src_rdcnt[15:0] In Source FIFO read count

dest_wrcnt[15:0] In Destination FIFO write count



src_rd Out Read strobe for source FIFO

Table 30. ii_packetizer Logic Ports

PCI Express INTF

This component sends and receives data to the host through PCI Express interface. The input and output data width is 64 bits, and the destination count and source count are 16 bits wide.

Figure 86. PCIE INTF component



wr In Write strobe



wrcnt[15:0] Out PICE ififo write count

Table 31. PCIE TX INTF Logic Ports


data[63:0] Out Output data

rdcnt[15:0] Out PICE ofifo read count

rd In Read strobe

Table 32. PCIE RX INTF Logic Ports

QDR SRAM INTF

This component is an interface between user's logic and the external QDR II SRAM. Samples captured from the logic can be stored in SRAM for further signal analysis using MATLAB or used as part of the application logic for data buffering. The 4 MB memory gives very powerful signal analysis capabilities to the board for real-time data buffering for MATLAB or application logic.

There are three addresses. Ports “wr addr” and “rd addr” are for MATLAB/Simulink read/write in slow mode; another “address” is in the ii_sram_intf.vhd for fast read/write in real-time. SRAM uses “wr addr” and “rd addr” when “fast_mode='0'” and “address” when “fast_mode='1'.” Due to the limited bandwidth of Xilinx JTAG pod, MATLAB can only read/write using slower jtag clock and “wr addr” and “rd addr.” If real-time read/write is required, “wr” and “rd” is connected to the data valid of the incoming data, and the address increases with system clock. So fast data logging and playback can be accomplished.

SRAM interface provides address and data control with specific support for MATLAB use. Port “wr addr” and “rd addr” and “end_addr” provide the flexibility to read/write a specific chunk of data in SRAM. Port “fast_mode” allows SRAM to be accessed with FPGA system clock. Port “rollover” provides the function to wrap the address back to 0 when “end_addr” is reached, thus providing a circular buffer.


Figure 87. QDR SRAM INTF component


fast mode In Fast mode select'1' => use “address” in ii_sbsram_intf.vhd'0' => use “wr addr” and “rd addr”

rollover In In fast mode, SRAM address wraps back to zero if rollover is '1'

end addr[17:0] In End address is a reference to rollover SRAM address in fast mode

wr addr[17:0] In SRAM address for MATLAB slowly write back through JTAG device

rd addr[17:0] In SRAM address for MATLAB slowly read back through JTAG device



wr In Write strobe

rd In Read strobe






Table 33. SRAM INTF Logic Ports

ADC SPI INTF

This component is an SPI port interface to TI ADS6149 for X5 210M Rev C board. ADS6149 is configured prior to operation for initialization steps over this SPI port. MATLAB/Simulink provides an easy way to configure registers by editing vectors in MATLAB “Workspace” and send them through SPI interface. More complicated operations can be done by changing the register values through the SPI interface. Please download the datasheet for advanced applications. (http://focus.ti.com/lit/ds/symlink/ads6149.pdf)

Software initialization in Snap is done using the following configurations.

//---------------------------------------------------------------------------// X5_210MInputDevice::ConfigureHardware()//---------------------------------------------------------------------------

void X5_210MInputDevice::ConfigureHardware(){ inherited::ConfigureHardware();

if (Owner->FpgaLogicVariant() >= 1) // Rev C or above { // X5-210M rev C A/D serial register initialization // initialize all four ADS6149 devices simultaneously ConfigReg.Port(0x20, 0x00); ConfigReg.Port(0x3f, 0x20); ConfigReg.Port(0x41, 0x80); // clock aligned with data. Used for rev C test plan test data ConfigReg.Port(0x44, 0xd8); // two's complement output format (for unsigned, use 0x06) ConfigReg.Port(0x50, 0x04); ConfigReg.Port(0x51, 0x00); ConfigReg.Port(0x52, 0x00); ConfigReg.Port(0x53, 0x00); ConfigReg.Port(0x55, 0x00); // test pattern off ConfigReg.Port(0x62, FPatternEnable ? 0x04 : 0x00);

ConfigReg.Port(0x63, 0x00); }}


http://focus.ti.com/lit/ds/symlink/ads6149.pdf

Figure 88. ADC SPI INTF component


spi_adc_sel In ADC selection“1” => ADC 0;“2” => ADC 1;“4” => ADC 2;“8” => ADC 3.

data[7:0] In SPI data

addr[7:0] In SPI address

wt In Write strobe

Table 34. ADC SPI INTF Logic Ports

Digital IO

This component is a simple digital IO port that has an input register and output register. It may be used as a simple digital control port or easily customized. Port “dio_en” controls a mux to use data from the software or MATLAB/Simulink project. The 16 bit “rx_data” is connected to a register, which is written when “rd” is low. “tx_data” writes the output register when “wr” is high. The source VHDL is available in <X5 root>\210M\Logic\Rev#\source\ii_dio.vhd.

Figure 89. DIO component



dio_en In '1' => data from MATLAB'0' => data from software

tx_data[15:0] In Transmitted data

ctrl[1:0] In Input/output direction controlctrl(0) = '1' => ud( 7 downto 0 ) is an outputctrl(1) = '1' => ud( 15 downto 8 ) is an output

wr In Write strobe for tx_data

rd In Read strobe for rx_data

rx_data[15:0] Out Received data

Table 35. Digital IO Logic Ports

System Configuration

This component provides communication with the host computer and allows controls from ctl_reg44~47 and read data back through status44~47. Port “en_config” enables the settings, such as test, test mode, gain/offset, and ADC SPI interface, from Simulink environment. If “en_config = 0,” all the settings are from the host software. This port provides the possibility to work without supports from software in logic development.

Using “clk_sel,” users can use the onboard crystal or external clock as ADC/DAC sample clock. Port “clk_locked” shows DCM is locked and DDR, QDR are ready to be used. Port “sys_reset” provides system reset to Simulink components. When “adc_run,” “sys_reset” is high. You can generate a reset for every run from software. Port “init_reset” provides a one time reset after the FPGA is loaded. Port “ext_sync” makes it possible to use external trigger in the MATLAB project.

On the panel, ADC sample clock can be sent to SYNC port for debug purpose, or use SYNC port as an external trigger input.


Figure 90. System Configuration component

Figure 91. System Configuration panel


clk_sel In Clock select'0' => external clock;'1' => 125 MHz onboard clock.

en_config In Enable Configuration from Simulink'1' => From Simulink;'0' => From the host.







clock_locked Out Clock locked signalsys_clk, ddr_ref_clk, ddr2_dcm, qdr0_dcm, qdr1_dcm are locked.

temperature Out Temperature dataTemperature = temp * 0.492 - 273.15

sys_reset Out Reset is high if adc_run or dac_run is low.

init_reset Out Reset after loading the FPGA

ext_sync Out External trigger





Table 36. System Configuration Logic Ports


Examples

All the examples are available at <X5 root>\210M\MATLAB\Rev#\Examples.

File name (.mdl) Contentsx5_210m_default This example shows standard connections in FrameWork Logic for data acquisition.

user_design This example shows explains where and how to place an user's application.

Table 37. MATLAB Examples for X5 210M

In MATLAB command window, you need to assign a value to “ts” for compilation. Currently the system is running at 200 MHz, so please type “ts=1/200e6;”.

To run the hardware co-simulation example, you can open the file “x5_210m_default_cosim.mdl” and push the play button. After loading the generated bit file through Xilinx Jtag pod, the FPGA is free running at system clock. You need to restart the computer or re-enumerate the board in Windows “Device Manager” to enable PCI Express connection. After rebooting the machine, please run hardware cosimulation with “Skip device configuration” checked as figure shown below. So it won't load the logic again and kill the PCI Express connection.

Figure 92. Xilinx Jtag pod configuration

To use the settings from Simulink environment, please make sure that “en_config = '1'.” To give controls back to the host software, please set “en_config = '0'.”


Example: x5_210m_default.mdl

This example shows standard connections in FrameWork Logic. The 16 bits ADC 0/1/2/3 data is interleaved and sent to DDRVFIFO for data buffering. The data out goes through an asymmetric FIFO and packetized for PCIE_TX_INTF. Data movements between FIFOs are flow controlled by “ii_flow_ctrl” or data valid strobe.

The project is actually a component in FrameWork Logic, and the board support package interface blocks are wrappers for the input/output ports. So most of the components are necessary to be instantiated in the compilation. For example, you need to keep “System_Configuration,” “ADC0/1/2/3_INTF,” “DDR_VFIFO,” “ii_packetizer,” “PCIE_TX/RX_INTF,” “SRAM0/1_INTF,” “DIO_INTF,” and “spi_adc” of Rev C board. You can remove “ii_interleaver_210m,” “ii_flow_ctrl,” “ii_reorder,” “V5_FIFO.” The rest yellow gateways will become jtag ports exchanging data between MATLAB/Simulink and FPGA in hardware co-simulation.

Figure 93. Block diagram of default example

After building a project, you need to double-click on the System Generator token, choose the compilation target, and generate a bitstream for hardware co-simulation. You can choose XFLOW options files to have more controls in the compilation. The files provided by II are in <Xilinx root>\DSP_Tools\sysgen\plugins\compilation\Hardware Co-Simulation\X5_210M\balanced_jtag.opt.

In MATLAB command window, you need to assign a value to “ts” for compilation. Currently the system is running at 200 MHz, so please type “ts=1/200e6;”.


Example: user_design.mdl

In this example, a signal from ADC_INTF goes through a lowpass filter to the host. ADC sample rate is 125 MHz and system clock is 200 MHz. The flow control is done by using valid strobe and DDR_VFIFO ready signal.

Figure 98. Block diagram of fir_loopback example

The filter is designed using MATLAB FDATool in the following picture. The passband of the frequency response is 3 MHz and the stopband is 8 MHz. The coefficients are passed to “FIR Compiler v3_2” by filling “xlfda_numerator('FDATool')” as coefficient vector. The output of “FIR Compiler v3_2” is 32 bits, and the slice block helps to determine the location of MSB to get the best precision. It shows the possibility to use the powerful tool in FPGA design for now and the future.

Figure 99. Design in user_design block


Figure 100. Filter coefficients generated in MATLAB FDATool

A simple experiment can be done using this example. We connect a function generator on ADC0 and snap the data in the host. The generated sine wave starts from 1 MHz and the frequency is increased steadily to 8 MHz. In Binview, the amplitude should be gradually attenuated by the filter.

Four 32 bits control registers provide extra controls from the host software. Four 32 bits status registers receive data from the project for any purpose. The control registers are hooked up to status registers in the default example. We can write the control register 44 in example software Snap “Debug page” and see the correct value read back through status register 44 in the following picture.

Figure 101. Write/read to ctl_reg44 through X5-210 Snap


Figure 102. Write/read to ctl_reg44 through X5-210 Snap

Figure 103. Value read back of ctl_reg44 in MATLAB/Simulink


FAQ

1. Why can't I compile the examples in MATLAB or load the projects into Xilinx ISE when I first installed the BSP?

After BSP installation, please right-click the installation folder and uncheck the “read-only” option. In the hardware co-simulation example, please double-click on the cosim block and check the path of bitstream.

2. When I run the hardware cosim example, Simulink showed the error: “Could not open the programming cable.”

Please check if cable is correctly attached to the connector. Is the light on Jtag pod green? Is the red line on the Jtag cord align to the square mark on the connector.

Please double-click the cosim block and see if the right cable is selected, as shown in the picture.

3. When I run the hardware cosim example, the result is different from what I expect.

Please double-click the cosim block and see if the block is in free-running mode, as shown in the picture.


4. I had high timing score problem in the PAR process. What can I do to reduce the timing problem?

The similar problem is discussed in “Chapter 3 Design Flow.” First, you can use “Floorplanner” and see if there is any signal traveled a long distance to its destination. You can buffer the signal by adding registers in Simulink. Second, you can use “Timing Analyzer” to locate the timing errors. You can either improve the problems according to the instructions in “Timing Analyzer” or rearrange the corresponding components in the floor plan.

5. I saw “license not found” error in the compilation.

Please check if you are using Microsoft Remote Desktop. If not, please contact tech support in II.


Revision History

The following table shows the revision history for the Board Support Package.

Date Version Revision

11/16/07 0.1 First release (Billy Kao)

01/16/09 1.0 Modified installation instruction, design flow, adv skills, x5 400m, x5 210m. Added ii_dsp_lib. (Billy Kao)

01/21/09 1.1 Added components in ii_dsp_lib. (Billy Kao)

01/26/09 1.2 Updated content of x5 210m. (Billy Kao)


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