University of Washington Department of Electrical Engineering

MATLAB Simulation

of the

MWA Digital Receiver Chain

Prepared by

Evan Ding and Lyutianyang Zhang

April 22, 2018

ii

Table of Contents

List of Figures .............................................................................................................................................. iii

1 Introduction ................................................................................................................................................ 1

2 System Description .................................................................................................................................... 1

2.1 System Model ..................................................................................................................................... 1

2.2 Channelization .................................................................................................................................... 2

2.3 Correlation .......................................................................................................................................... 7

2.4 Fixed Point Processing ........................................................................................................................ 8

3 System Verification ................................................................................................................................... 9

3.1 PFB Channelizer ............................................................................................................................... 10

4 Conclusion ............................................................................................................................................... 15

Appendix A : System Block Diagram ............................................................................................................ I

iii

List of Figures

Figure 1. High Level System Block Diagram ............................................................................................... 2

Figure 2. Visualization of Ideal Channelization ........................................................................................... 3

Figure 3. Visualization of Aliasing from Non-Ideal Filters in Channelization ............................................. 5

Figure 4. Illustration of Spectral Power Mixing in Second Stage Channelizer ............................................ 7

Figure 5. Rectangular Window Filters ........................................................................................................ 11

Figure 6. Validation of Rectangular Window Channelizer ......................................................................... 11

Figure 7. Prototype Low Pass Filters for the Two Channelizer Stages ...................................................... 12

Figure 8. Validation of Low Pass Filter Channelizer .................................................................................. 13

Figure 9. Validation of Power Splitting over Coarse Bins .......................................................................... 14

1

1 Introduction

The Murchison Widefield Array (MWA) is a low frequency radio telescope based at the Murchison

Radio-Astronomy Observatory (MRO) in Western Australia. The telescope has been developed by an

international collaboration for the purpose of detecting faint radio signals from far reaches of the universe.

The MWA consists of a group of 128 antenna tiles scattered over an area of approximately 2000 square

meters. Each tile contains a 4 by 4 array of dual-polarized dipole antennas. A tile acts as a telescope by

using beamforming to magnifying RF signals arriving from different directions in the sky.

The MWA operates over a wide frequency range of 30-300 MHz. As a result, a large amount of data must

be processed in real time to extract signals of interests. An intricate system of FPGAs, ADCs, and

communication fibers has been carefully designed to support the necessary digital signal processing

(DSP). However, non-idealities have been observed at the final system output. Some of these non-

idealities have been identified as radio-frequency interference (RFI). Others are suspected to be caused by

problems within the DSP chain itself.

A MATLAB simulation of the MWA DSP chain has been developed to support the investigation of these

problems. This report summarizes the simulation design and the capabilities offered.

2 System Description

Each of the 128 tiles in the MWA acts as a single beamforming unit, which produces two analog signals

corresponding to the measured signals for the two antenna polarizations. This produces a total of 256

different analog signal streams that must be processed. The signals are sampled at 655 MHz and

converted to the digital domain for processing. Signals of interest are extracted from the digitized signal

streams by computing pair-wise correlations. The visibility between a pair of signal streams is defined as

the time-averaged power spectrum of the cross correlation. The same DSP chain is used to compute the

visibilities for every pair of antennas, which are then stored in a database for further processing. Because

the same operations are used for every pair of signal streams, it suffices to simulate the processing

involved in the visibility computation of a single pair of signals.

2.1 System Model

Figure 1 summarizes the system model of the DSP that is performed on every pair of signal streams. The

two input streams are first individually channelized into discrete frequency bins to obtain their time-

varying spectra. The spectra from the two signals are pointwise multiplied to obtain the spectra of the

2

cross correlation. The cross-correlated spectra are then integrated over time to yield the visibility. To

reduce the amount of data that is stored, only a subset of the discrete frequency bins are selected for

correlation at any given time.

Figure 1. High Level System Block Diagram

A detailed block diagram of the system architecture and the I/O specifications of each block are provided

in Appendix A. Specification details were acquired from [1] as well as archives of email correspondences

with engineers who provided the firmware for the MWA DSP chain.

2.2 Channelization

An ideal N-bin channelizer decomposes the spectrum of a sampled input signal stream, 𝑥, into N different

output signals, {�̃�𝑘}𝑘=0𝑁−1, each sampled at 1/𝑁 th the rate of 𝑥 . The spectrum of �̃�𝑘 is precisely the

spectrum of a 2𝜋/𝑁 wide sub-band of 𝑥 centered at 2𝜋𝑘/𝑁 . Figure 2 illustrates the input-output

relationship of an ideal channelizer for N = 5 frequency bins. For ease of illustration, colors are used to

identify distinct blocks of the spectrum. The spectrum in each block is not necessarily flat, but blocks

with the same color indicate portions of the spectrum that share the same spectral shape. Ideal

channelization preserves all the information in the original signal and can be inverted to reconstruct the

original signal.

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Figure 2. Visualization of Ideal Channelization

The MWA DSP chain performs channelization in two stages. In the first stage, the baseband signal,

sampled at 655.36 MHz, is transformed into 𝑁 = 512 coarse frequency bins. This results in 512 complex

signals, each with 1.28 MHz bandwidth. Since the input signal is real, only 256 of the channelized signals

are distinct. Of the 256 distinct signals, 24 are selected by the user for further channelization. In the

second stage, each of the 24 coarse channels are transformed into 𝑁 = 128 fine frequency bins, yielding a

total of 3072 frequency bins used to perform the correlation.

If the channelizer used in each stage is ideal, the two stage channelization process is equivalent to a single

channelization with N = 65536 followed by the selection of a subset of the 65536 channels for

correlation.

4

In practice, the channelization performed by the MWA DSP chain is extremely non-ideal. The non-

ideality is dominated by two factors:

Channelization is performed with non-ideal filters. This causes spectral leakage between sub-

bands in the channelization process, so a particular output channel may have power contributions

from adjacent channels in the frequency domain.

o The two stage process aggravates this problem since leakage from the first stage distorts

the input signals being processed at the second stage.

Signals are represented with finite bit precision and all computations are performed using fixed

point arithmetic (Section Error! Reference source not found.). This produces non-linear

distortions in the spectral shape of the signal.

o Requantization also occurs between the two stages of channelization. In the physical

system this is due to need to compress the information for transmission across an

Ethernet link.

2.2.1 MWA Channelizer Each stage of channelization is conducted using a polyphase filter bank (PFB) architecture. The operation

performed by a general PFB channelizer can be described by:

𝑥𝑘[𝑚] = ∑ 𝑥[𝑚𝑁 + 𝑙]𝑤[𝑙]𝑒−𝑗2𝜋𝑘𝑙

𝑁

𝑄𝑁−1

𝑙=0

, 𝑘 = 0, … , 𝑁 − 1 (1)

Where 𝑥𝑘[𝑚] is the value of the 𝑘th frequency bin corresponding to time index 𝑚, 𝑥 is the input signal

stream, and 𝑤 ∈ ℝ𝑄𝑁 is the finite impulse response of a prototype low pass filter with cut-off frequency,

𝜔𝑐 =𝜋

𝑁.

To understand how (1) performs channelization, consider the set of vectors: {𝑤𝑘 ∈ ℂ𝑄𝑁}𝑘=0𝑁−1 such that

𝑤𝑘[𝑙] = 𝑤[𝑙]𝑒−𝑗2𝜋𝑘𝑙

𝑁 . Each 𝑤𝑘 can be interpreted as a bandpass filter with the same spectral shape as 𝑤

and cut-off frequencies 2𝜋𝑘

𝑁±

𝜋

𝑁. Using 𝑤𝑘, the expressing for 𝑥𝑘 can be written as:

𝑥𝑘[𝑚] = ∑ 𝑥[𝑚𝑁 + 𝑙]𝑤𝑘[𝑙]

𝑄𝑁−1

𝑙=0

= (𝑥 ∗ 𝑤𝑘)[𝑚𝑁] (2)

where ∗ is the linear convolution operator.

5

Thus, 𝑥𝑘 is a downsampled version of a bandpass filtered version of 𝑥. If 𝑤 is an ideal low pass filter,

then 𝑤𝑘 would be an ideal bandpass filter. In such a scenario, 𝑥𝑘 is equivalent to, �̃�𝑘, the 𝑘th channel of

the ideal N-band channelizer.

2.2.1.1 Aliasing due to Non-Ideal Filters

In practice, it is impossible to design an ideal low pass filter with finite impulse response. Since the sub-

band channels are sampled at Nyquist rate, the spectral leakage caused by non-ideal filters manifest as

aliasing between the energy of the main frequency bin and the energy leaked in from adjacent bins.

Figure 3 illustrates aliasing in a particular sub-band channel. The channelizer parameters and input signal

are the same as those from Figure 2. Similar aliasing effects would be present in all of the sub-bands.

Figure 3. Visualization of Aliasing from Non-Ideal Filters in Channelization

To mitigate aliasing, it is necessary to use filters with long impulse responses which better approximate

the ideal low pass filter. In the MWA system, a filter of length 𝑄𝑁 = 8(512) = 4096 is used in the first

stage and a filter of length 𝑄𝑁 = 12(128) = 1536 is used in the second stage.

Convolution with large filters is computationally expensive. However, the process can be simplified via

parallel processing. This can be shown by rewriting (1) as:

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𝑥𝑘[𝑚] = ∑ ∑ 𝑥[𝑚𝑁 + 𝑙 + 𝑞𝑁]𝑤[𝑙 + 𝑞𝑁]𝑒−𝑗2𝜋𝑘(𝑙+𝑞𝑁)

𝑁

𝑄

𝑞=0

𝑁−1

𝑙=0

= ∑ (𝑒−𝑗2𝜋𝑘𝑙

𝑁 ∑ 𝑥[(𝑚 − 𝑞)𝑁 + 𝑙]𝑤[𝑞𝑁 + 𝑙]

𝑄

𝑞=0

)

𝑁−1

𝑙=0

(3)

The inner sum is a convolution over the elements of 𝑥 and 𝑤 that are congruent modulo 𝑁. Suppose 𝑥 is

reshaped into 𝑁 parallel streams, {𝑦𝑙}𝑙=0𝑁−1 such that 𝑦𝑙[𝑟] = 𝑥[𝑟𝑁 + 𝑙] and 𝑤 is reshaped into a matrix,

𝑊 ∈ ℝ𝑁×𝑄, such that 𝑊[𝑙, 𝑞] = 𝑤[𝑞𝑁 + 𝑙] . Then:

𝑥𝑘[𝑚] = ∑ (𝑒−𝑗2𝜋𝑘𝑙

𝑁 (𝑦𝑙 ∗ 𝑊[𝑙, : ]) )

𝑁−1

𝑙=0

(4)

The rows of 𝑊 form a filter bank which can be convolved with the reshaped input stream in parallel,

Convolution with the filter bank produces time slices of length N that can then be Fast Fourier

transformed into the desired sub-band bins. The PFB channelizer is thus named for this reason.

2.2.1.2 Spectral Power Mixing in Second Stage

In addition to aliasing, the MWA system may also suffer from spectral power mixing due to the use of an

even number of channels in the second stage of channelization. The input to each second stage

channelizer is a baseband representation of a passband signal from the output of the first stage

channelizer. Thus, the sub-band frequency of each channel at the output of the second stage is, in reality,

relative to the center frequency associated with the input signal. When an even number of bins are used in

the second stage, there will be one bin that is centered at 𝜋. Because 𝜋 is equivalent to – 𝜋 in discrete

time, this particular fine bin would contain power from non-adjacent frequencies above and below the

center frequency of the coarse bin. Figure 4 summarizes the problem with a pictorial example.

The mixing of power from difference frequencies poses no problems to correlation, but it may cause

issues with the interpretation of visibility frequencies. For example, if a particular feature happens to

manifest in one of the mixed bins, there are two possible fine frequency bands from which it may have

originated in the analog signal.

Correcting for this issue is straightforward. By introducing a 5 kHz frequency shift prior to the second

stage channelization, the originally mixed bin can be pushed completely to the negative or positive side.

This will cause the fine bins to be symmetric about the center frequency of the coarse bin and no bin will

contain power from non-adjacent frequencies. However, the provided simulation does not implement

this correction since the real-world DSP chain does not appear to address this issue.

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Figure 4. Illustration of Spectral Power Mixing in Second Stage Channelizer

2.3 Correlation

The second stage channelizers output 3072 channels, each sampled at 10 kHz. These consist of 24 sets of

128 fine bins, where each set correspond to one of the selected coarse channels. It is assumed that the

same set of channels is selected for each signal stream.

In the correlation stage, the 3072 fine bins from two antenna signal streams are conjugate multiplied.

After multiplication, each set of 128 fine bins may be optionally blocked into wider bins. This is

accomplished by the choice of some factor, C, which divides 128 such that every consecutive block of C

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fine bins are pointwise added to produce the equivalent value for a fine frequency channel of bandwidth

10C kHz. The user has direct control over the value of C.

The values of the bins are then summed over a period of time, T, as specified by the user. Assuming the

signals are ergodic, this is equivalent to computing the expectation of the product, which is the

correlation. The resulting visibility is a function of time and frequency, where the frequency resolution is

10C kHz and the time resolution is 1/T Hz.

2.4 Fixed Point Processing

Real time processing imposes strong constraints on the hardware performance of the MWA DSP system.

FPGAs operate directly on bits, so they can be optimized for integer arithmetic. As a result, almost all of

the processing in the DSP chain is performed using fixed point arithmetic. To be consistent with the real

world model, quantization and fixed point arithmetic is also used in the simulation. Support for fixed

point operations is provided by the Fixed Point Designer Toolbox in MATLAB.

Non-idealities introduced by fixed point arithmetic are determined by the logic used for rounding and

requantization. In the simulation, the following follows rules summarize the logic for all fixed point

manipulations:

1. All fixed point data are signed two’s complement. So an n-bit value can take on integer values in

the range [−2𝑛, 2𝑛 − 1].

2. Requantization and casting are performed using the “ROUND” logic described in the Fixed Point

Designer documentation (https://www.mathworks.com/help/fixedpoint/ug/precision-and-

range.html).

Numbers are rounded to nearest integer.

In the event of ties, rounding is performed to maximize distance from 0.

3. Saturation logic is used when overflow is encountered. This minimizes the error between the true

value and the fixed point value.

4. All computation is performed using the maximal bit length. If two values are of different bit

lengths, the more constrained value will be casted into the higher bit precision before

computation.

5. In each block described in Appendix A, the output bit precision is obtained by casting after all

necessary computation has occurred.

6. A Radix-2 Fixed Point FFT is used in each of the PFB channelizers. The algorithm is consistent

with the one described here: https://www.mathworks.com/help/fixedpoint/examples/convert-fast-

fourier-transform-fft-to-fixed-point.html.

9

NOTE: The details regarding quantization logic in the actual MWA DSP chain is not well documented.

Some assumptions have been made in the simulation design.

2.4.1 Error from Fixed Point Processing Fixed point processing creates two main sources of error:

Quantization error is generated when the signal is cast from a long word length to a shorter word

length. This decreases the resolution of the signal, introducing errors between the signal being

operated on and the signal being represented.

Computational error is inherent to fixed point arithmetic operating on signals that are not

constrained to integers. Error is accumulated every time rounding is performed after an operation

to maintain an integer representation of the signal. Furthermore, saturation can occur when an

operation yields a result that exceeds the range supported by the word length.

It is expected that errors caused by quantization would largely be incurred at the points where the signal is

represented with the fewest number of bits. This corresponds to two points in the DSP chain:

1. After the first channelization stage, the signals from the 24 coarse bins of interests are quantized

to 5 bits of real and 5 bits of imaginary.

2. After the second channelization stage, the signals from all 3072 fine bins are quantized to 4 bits

of real and 4 bits of imaginary.

The computational error is more complicated and likely dependent on the characteristics of the signal

being processed as well as the word length used in the computation process.

In general, errors from fixed-point processing are difficult to dissect analytically. For this reason,

the simulation was built with floating point and fixed point modes. In the floating point mode, all of

the same DSP operations are performed, but with floating point precision. This allows a directly

comparison of floating point outputs with the fixed point counterpart. Furthermore the quantization bits

after each stage of channelization can be easily adjusted to examine the impact of word length on the

output of the respective channelizers.

3 System Verification

The system consists of two main parts: channelization and correlation. The correlation step is simple and

easily verified. However, the multi-stage channelization step warrants more systematic testing.

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3.1 PFB Channelizer

To verify the correct implementation of the channelizer, a series of tests were conducted using sinusoidal

inputs. Since all discrete time signals can be decomposed into a linear combination of sinusoids, this is an

efficient substitute for testing signals with different spectral characteristics.

Verification was only performed using floating point mode. There are several reasons for this:

1. The floating point and fixed point modes use the same signal flow, so validating one is sufficient

to validate the high level architecture.

2. Fixed point operations and quantization are handled by the MATLAB toolbox which is assumed

to be correct.

3. It is difficult to evaluate the correctness of fixed point operations since there is no analytical

theory to use as a reference.

3.1.1 Tests and Results The first test involves the use of PFBs that are simple rectangular windows. Figure 5 shows the filter

characteristics for the windows. Rectangular windows transform the channelizer into nested short time

Discrete Fourier Transforms. Figure 6 shows the result of passing a single cosine tone into the

channelizer. Because the spectral characteristics of the input signal is constant, the output of each stage

can be averaged over time and plotted to obtain a representative view of the output signal. The top plot

corresponds to the output of the first stage and the bottom plot is the output of the second stage. The

simulation outputs are plotted against the Discrete Fourier Transform (DFT) of the input to the

channelizer as well as the theoretical continuous spectrum of the signal being represented. The gray

circles mark peaks which appear at matching frequencies.

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Figure 5. Rectangular Window Filters

Figure 6. Validation of Rectangular Window Channelizer

12

As expected, the rectangular window yields an output with magnitude identical to the 512-FFT for the

first stage. The input signal is a cosine function of finite length so the spectrum is a sinc function.

In the second stage, a 128 point DFT is computed over each frequency bin of the first stage. This is

equivalent to sampling the spectrum corresponding to each sub-band channel of the first stage. The wide

rectangular window of the first stage produces a narrow sinc in frequency that is well approximated by a

delta function. Thus, each sub-band channel is effectively a DC signal corresponding to the amplitude of

input cosine sinc sampled at the corresponding coarse frequency bin. A finite length DC signal becomes a

sinc in frequency, so the second stage produces a sampled sinc centered and scaled by every peak in the

first stage output. Note that this characteristic differs from the 65536-FFT of the input signal, which

equivalent to sampling the spectrum of a longer cosine signal.

In the second floating point test, the correct MWA PFB are used in each stage of the channelizer, but the

integer filter coefficients are normalized to floating points. Figure 7 show the filter characteristics for the

filters.

Figure 7. Prototype Low Pass Filters for the Two Channelizer Stages

The same input signal from the first test was sent through the system with the new filters. Figure 8

summarizes the results.

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Figure 8. Validation of Low Pass Filter Channelizer

Unlike rectangular windows, the MWA filters have a flat gain over the entire bandwidth of a sub-band

and high suppression elsewhere. This means the signal in each coarse sub-channel has a spectrum that is

very close to the spectrum of the input signal windowed to the corresponding sub-band. The average

power, and therefore magnitude, of each coarse frequency bin is proportional to the power of the cosine

sinc contained within the corresponding sub-band. Since the bulk of the power of a sinc function is

contained near the center frequency, this means the coarse frequency bin containing the cosine frequency

should have much greater amplitude than the others. This is confirmed by the top plot in Figure 8. In the

second stage channelization, the same process occurs over the spectrum of each coarse bin. Due to the

nesting structure, this results in a single fine bin with significant power.

In this test, the results from both stages differ from that of the direct FFT. This makes sense because the

direct FFT samples the underlying continuous spectrum while the channelizer computes the average

power over bins.

As final confirmation that the observed results are consistent with theory, a third test was conducted in

which the input sinusoid frequency was chosen to lie exactly on the boundary between two coarse bins.

14

Theory predicts that the power of the sinusoid will be equally split between the two coarse bins. Figure 9

shows the output of the simulation.

Figure 9. Validation of Power Splitting over Coarse Bins

The coarse bins share the power of the sinusoid equally due to the symmetrical position of the sinusoid

peak. In the second stage, the nesting behavior once again manifests, resulting in the preservation of the

two peaks.

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4 Conclusion

This report summarizes MATLAB simulation developed for the DSP chain used in the Murchison

Widefield Array. The purpose of this simulation is to facilitate the analysis of RFI and other non-idealities

that have been observed at the output of the chain. A high fidelity model of the processing that is

performed in practice enables the numerical testing of factors which may be contributing to non-idealities.

Possible uses include, but are not limited to:

Characterization of known TV/Satellite signals at various points in the DSP chain.

Characterization of the impact of quantization bits on the fidelity of the output visibility.

Evaluation of proposed an existing RFI flagging techniques.

Evaluation of proposed methods for improving detection of desired RF signals.

Future work would largely be focused on optimizing simulation run-time. Minor adjustments may also be

made if new details emerge regarding the real-world implementation of the DSP chain.

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References

[1] T. Prabu, K.S Srivani, D.A Roshi, et al. “A digital-receiver for the MurchisonWidefield Array,”

Experimental Astronomy, Vol. 39, No. 1, pp 73-93, March, 2015.

[2] C. Harris, K. Haines. “A Mathematical Review of Polyphase Filterbank Implementations for

Radio Astronomy,” Publications of the Astronomical Society of Australia, Vol. 28, No. 4, pp 317-

322, Jan., 2013.

I

Appendix A: System Block Diagram

.

II

Block Name FIRST STAGE PFB CHANNELIZER

Input Description (L × 1) vector corresponding to L time samples for a specific signal

stream.

Input Data Type 9-bit real

Input Sampling Frequency 655.36 MHz

Filter Coefficients (8 × 512) 12 bit real

Kaiser window of length 4096 with β = 5 reshaped into PFB form.

FFT Coefficients 12 bit complex

Output Description

(M × 256) matrix corresponding to 256 coarse channels of first 256

bins of FFT.

M = L/512-7

Output Data Type (16,16)-bit complex

Output Sampling Frequency 1.28 MHz

Implementation Notes The highest frequency half band is omitted from the output

since the center frequencies of the output FFT bins are of

the form:

(1.28n)MHz, n = 0,1,…,255

Block Name CHANNEL SELECT AND QUANTIZATION

Input Description (M × 256) matrix corresponding to output of FIRST STAGE PFB.

Input Data Type (16,16)-bit complex

Input Sampling Frequency 1.28 MHz

User Input

CHSEL = (1 X 24) vector corresponding to 24 integer indices of

desired coarse channels.

Index n corresponds to the 1.28 MHz band centered at (1.28n)

MHz.

CHGAIN = (1 X 24) vector corresponding to 24 16 bit integers

that are the digital gain for each of the corresponding channels

given in CHSEL.

Default: CHGAIN = ones(1,24)

III

Output Description (M X 24) matrix corresponding to the requantized signals for the 24

selected coarse channels.

Output Data Type (5,5)-bit complex

Output Sampling Frequency 1.28 MHz

Implementation Notes Each course channel signal is multiplied by the respective

digital gain before being quantized to 5 bits.

Block Name SECOND STAGE PFB CHANNELIZER

Input Description

(M × 1) vector corresponding to time samples of a specific coarse

channel.

M must be a multiple of 128.

Input Data Type (5,5)-bit complex

Input Sampling Frequency 1.28 MHz

Filter Coefficients

(12 × 128) 32-bit real

Filter coefficients provided by MWA engineer. Exact design

specifications unknown. 32-bit precision was estimated from

elements of the filter vector.

FFT Coefficients 12 bit complex

Output Description (N × 128) matrix corresponding to 128 coarse channels of FFT. N

= M/128-11

Output Data Type (32,32)-bit complex

Output Sampling Frequency 10 kHz

Implementation Notes This block has the same architecture as FIRST STAGE

PFB.

This block is replicated 24 times (once per each of the 24

selected coarse channels).

IV

Block Name (4,4)-BIT COMPLEX QUANTIZER

Input Description

(N × 3072) matrix corresponding to the fine channels for the 24

selected coarse channels of a single antenna-polarization.

Columns 1-128 are the fine channels for the first of the 24 channels,

columns 129-512 are the fine channels for the second of the 24

channels, etc.

Input Data Type (32,32)-bit complex

Input Sampling Frequency 10 kHz

Output Description (N × 3072) matrix corresponding to the requantized input.

Output Data Type (4,4)-bit complex

Output Sampling Frequency 10 kHz

Block Name CROSS MULTIPLIER

Input Description Two (N × 3072) matrices corresponding to the output of (4,4)-BIT

COMPLEX QUANTIZER for two different signal streams.

Input Data Type (4,4)-bit complex

Input Sampling Frequency 10 kHz

Output Description (N × 3072) matrix corresponding to the point-wise product of the

input matrices.

Output Data Type Floating Point (64-bit double)

Output Sampling Frequency 10 kHz

Computation Precision Input is converted to floating point before computation.

Block Name CHANNEL COMBINER

Input Description (N × 3072) matrix corresponding to the 3072 channel output of

CROSS CORRELATOR for a given antenna-polarization pair.

Input Data Type Floating Point (64-bit double)

Input Sampling Frequency 10 kHz

V

User Input

C = Scalar indicating how many 10 kHz channels should be

combined to form composite bins of 10C kHz.

C must be a factor of 128.

Output Description (N × F) matrix corresponding to the point-wise sum of C

consecutive channels of the input.

F = 3072/C

Output Data Type Floating Point (64-bit double)

Output Sampling Frequency 10 kHz

Block Name TIME SUM

Input Description (N × F) matrix corresponding to the output of CHANNEL

COMBINER.

Input Data Type Floating Point (64-bit double)

Input Sampling Frequency 10 kHz

User Input

T = Scalar indicating how over how many seconds over which time

samples are to be summed.

10000T must be an integer less than N

Output Description (D × F) matrix corresponding to the summation over 10000T time

blocks.

D = N/(10000T)

Output Data Type Floating Point (64-bit double)

Output Sampling Frequency 1/T Hz

Implementation Notes If N is not a multiple of 10000T, input length is truncated

to nearest multiple of 10000T.