maximizing parallel performance review of...

13
1 Advanced Computer Architecture II: Multiprocessor Design Parallel Programming II: Maximizing Performance Professor Russ Joseph Department of Electrical and Computer Engineering Northwestern University January 13, 2005 2 Maximizing Parallel Performance Last Time: Introduced some parallel performance limiters Covered parallelization process Today we will look at: Look closer at fundamental performance limiters Examine effective parallelization techniques Discuss interactions/tradeoffs between optimization techniques 3 Limitations to Parallel Speedup As we have seen, there are many obstacles on the road to speedup: Today we will take a closer look at them from a programmer's perspective. This all starts with the parallelization process... 4 Review of Parallelization P 0 Tasks Processes Processors P 1 P 2 P 3 p 0 p 1 p 2 p 3 p 0 p 1 p 2 p 3 Partitioning Sequential computation Parallel program A s s i g n m e n t D e c o m p o s i t i o n M a p p i n g O r c h e s t r a t i o n

Upload: others

Post on 04-Jul-2020

2 views

Category:

Documents


0 download

TRANSCRIPT

Page 1: Maximizing Parallel Performance Review of Parallelizationusers.ece.northwestern.edu/~boz283/ece-453-original/ece453-lec-04... · Maximizing Parallel Performance Last Time: Introduced

1

Advanced Computer Architecture II:Multiprocessor Design

Parallel Programming II: Maximizing Performance

Professor Russ JosephDepartment of Electrical and Computer Engineering

Northwestern University

January 13, 2005

2

Maximizing Parallel Performance

Last Time:

Introduced some parallel performance limiters

Covered parallelization process

Today we will look at:

Look closer at fundamental performance limiters

Examine effective parallelization techniques

Discuss interactions/tradeoffs between optimization techniques

3

Limitations to Parallel Speedup

As we have seen, there are many obstacles on the road to speedup:

Today we will take a closer look at them from a programmer's perspective.

This all starts with the parallelization process...

�� � � �� � ��� � � ��

� �� � �� � �� � ��� �

�� � � � � � � �� � � � � ��� �� � � �� �� � � � � � � �� � � � � ��� �

4

Review of Parallelization

P0

Tasks Processes Processors

P1

P2 P3

p0 p1

p2 p3

p0 p1

p2 p3

Partitioning

Sequentialcomputation

Parallelprogram

Assignment

Decomposition

Mapping

Orchestration

Page 2: Maximizing Parallel Performance Review of Parallelizationusers.ece.northwestern.edu/~boz283/ece-453-original/ece453-lec-04... · Maximizing Parallel Performance Last Time: Introduced

5

Partitioning for Performance

Key goals in decomposition/assignment include:

Balance the workload

Reduce communication

Decrease amount of extra work

We will take a closer look at these three...

6

Balancing The Workload

Need to balance the load AND synchronization wait time.

Limit on speedup: Speedupproblem(p) <

• Work includes data access and other costs

• Not just equal work, but must be busy at same time

Keys to balancing workload:

Identify enough concurrency.

Decide how to manage it.

Determine the granularity at which to exploit it.

Reduce serialization and cost of synchronization.

�� �� � � � �� � � �

� � � �� � � �� �� � �� � �

7

Identifying Concurrency

Two key concepts:

data parallelism – identical operations performed on different items of same datasetfor(i = 0; i < n; i++) a[i] = b[i] + c[i];

function parallelism – different operations carried out on possibly diverse datasetsfor(i = 1; i < n; i++)

a[i] = a[i-1] + b[i];...for(i=1; i<n; i++)

c[i] = c[i-1] + b[n-i] * k;

Partition to exploit either of these types of parallelism.

8

Managing Concurrency

Assignment can be done either statically or dynamically.

Static:

• Algorithmic assignment based on input; won’t change.

• Low runtime overhead.

• Computation must be predictable.

Dynamic:• Adapt at runtime to balance load.

• Can increase communication and reduce locality.

• Can increase task management overheads.

Page 3: Maximizing Parallel Performance Review of Parallelizationusers.ece.northwestern.edu/~boz283/ece-453-original/ece453-lec-04... · Maximizing Parallel Performance Last Time: Introduced

9

Static Assignment

Parallelizing agent decides how to divide computational tasks among processes (threads).

Easy to do if the computations are regular and predictable.

Otherwise, we risk load imbalance.

10

Dynamic Assignment

Profile-based (semi-static):

• Profile work distribution at runtime

• Repartition dynamically

Dynamic Tasking:

• Maintain pool of tasks

• Threads take tasks until all done

• Deal with unpredictability in program or environment

• Cost of management could be significant (computation,communication,memory system interaction)

11

Dynamic Tasking with Task QueuesCentralized versus distributed queuesTask stealing with

distributed queues• Can compromise communication and compromise locality, and

increase synchronization• Whom to steal from, how many tasks to steal, ...• Termination detection• Maximum imbalance related to size of task

QQ 0 Q2Q1 Q3

All remove tasks

P0 inserts P1 inserts P2 inserts P3 inserts

P0 removes P1 removes P2 removes P3 removes

(b) Distributed task queues (one per pr ocess)

Others maysteal

All processesinsert tasks

(a) Centralized task queue

12

Impact of Dynamic Assignment

On SGI Origin 2000 (cache-coherent shared memory):

Spe

edup

●●

✖✖

■■

▲▲

1 3 5 7 9 11 13 15 17

Number of processors Number of processors

19 21 23 25 27 29 310

5

10

15

Spe

edup

20

25

30

0(a) (b)

5

10

15

20

25

30

●●

✖✖

■■

▲▲

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31

● Origin, dynamic✖ Challenge, dynamic■ Origin, static▲ Challenge, static

● Origin, semistatic✖ Challenge, semistatic■ Origin, static▲ Challenge, static

Page 4: Maximizing Parallel Performance Review of Parallelizationusers.ece.northwestern.edu/~boz283/ece-453-original/ece453-lec-04... · Maximizing Parallel Performance Last Time: Introduced

13

Determining Task Granularity

A key reoccurring concept is granularity – the quantity of work associated with a task.

General rule:

• Coarse-grained => often less load balance

• Fine-grained => more overhead; if not careful, more communication, and contention

Communication and contention actually affected by assignment, not size

14

Reducing Serialization

Try to reduce time spent waiting at synchronization points.

Closely tied to not just assignment, but also orchestration.

Choose granularity of event synchronization:

Fine-grain- Reduce use of conservative synchronization (point-to-point instead of barriers).

Course-grain- Easier to program, potentially fewer synchronization operations.

Apply better use of mutual exclusion:Separate locks for separate data.

Smaller, less frequent critical sections.Stagger critical sections in time.

15

Implications of Load Balance

Extends speedup limit expression to: <

Generally, responsibility of software.

Architecture can support task stealing and synchronization efficiently

• Fine-grained communication, low-overhead access to queues– efficient support allows smaller tasks, better load balance

• Naming logically shared data in the presence of task stealing– need to access data of stolen tasks, esp. multiply-stolen tasks

=> Hardware shared address space advantageous

• Efficient support for point-to-point communication

Sequential Work

Max (Work + Synch Wait)

16

Reducing Inherent Communication

Communication is so expensive, that we have to find ways of limiting it.

Important concept: communication to computation ratio

Focus here on inherent communication (we'll talk about other forms later).

Largely dependent on assignment, so assign tasks that access same data to same process.

Page 5: Maximizing Parallel Performance Review of Parallelizationusers.ece.northwestern.edu/~boz283/ece-453-original/ece453-lec-04... · Maximizing Parallel Performance Last Time: Introduced

17

Domain Decomposition

Assign related tasks (within the same “domain”) to the same process.

Usually these tasks operate on the same or similar set of data.

In scientific applications, domains often map to physical dimensions.

Exploits local-biased nature of physical problems (e.g. nearest-neighbor computations).

18

Example: Domain Decomposition

Comm to comp: for block, for strip

• Retain block from here on

Application dependent: strip may be better in other cases• E.g. particle flow in tunnel

4* pn

2*pn

Best domain decomposition depends on information requirementsNearest neighbor example: block versus strip decomposition:

P0 P1 P2 P3

P4

P8

P12

P5 P6 P7

P9 P11

P13 P14 P15

P10

n

n

n

p------

n

p------

19

Finding a Domain Decomposition

The right choice of domain decomposition to apply is highly specific to problem:

Static(Inspection)- computations are predictable.

Static(Analysis)- nature of computation is highly input-dependent.

Semi-static(Periodic Repartitioning) - characteristics change slowly.

Static/Semi-static(Dynamic Task Stealing) – highly unpredictable.

There are many variations on these approaches.

20

Implications of Communication Cost

Communication costs in a real system can be significant.

Sequential Work

Max (Work + Synch Wait Time + Comm Cost)Speedup <

Page 6: Maximizing Parallel Performance Review of Parallelizationusers.ece.northwestern.edu/~boz283/ece-453-original/ece453-lec-04... · Maximizing Parallel Performance Last Time: Introduced

21

Reducing Extra Work

Along the way, we've already talked about ways that extra work can be introduced:

• Effort in computing a good partition.

• Task, data and process management overhead.

Sometimes, extra work can be traded-off against communication/synchronization

• Redundant local computations to avoid global communication).

• Data transformation to reduce communication/synchronization.

Sequential Work

Max (Work + Synch Wait Time + Comm Cost + Extra Work)Speedup <

22

Summary: Analyzing Parallel Algorithms

Requires characterization of multiprocessor and algorithm

Historical focus on algorithmic aspects: partitioning, mapping

PRAM model: data access and communication are free

• Only load balance (including serialization) and extra work matter

• Useful for early development, but unrealistic for real performance

• Ignores communication and also the imbalances it causes

• Can lead to poor choice of partitions as well as orchestration

• More recent models incorporate comm. costs; BSP, LogP, ...

Sequential Instructions

Max (Instructions + Synch Wait Time + Extra Instructions)Speedup <

23

Enough With The Algorithm Analysis!

Inherent communication in parallel algorithm is not the end of the story.

Communication cost depends on frequency and communication time:

Artifactual increase frequency; causes include:

• program implementation

• architectural interactions (can dominate)

Communication time is obviously dependent on architectural implementations.

24

Basics: Multiprocessors

Multiprocessors are a collection of communicating processors.

These are multi-cache, multi-memory systems:

• Role of these components essential regardless of programming model

• Programming model and communication abstraction affect specific performance tradeoffs.

Page 7: Maximizing Parallel Performance Review of Parallelizationusers.ece.northwestern.edu/~boz283/ece-453-original/ece453-lec-04... · Maximizing Parallel Performance Last Time: Introduced

25

Memory-Oriented View

Multiprocessors have an extended memory hierarchy:

registers

caches

local memory

remote memory

Communication architecture glues it all together.

Guiding principles are exploiting temporal and spatial locality.

26

Uniprocessor Performance

Obviously, performance depends heavily on memory hierarchy.

Time spent by a program:

Timeprog(1) = Busy(1) + Data Access(1)

Data access time can be reduced by:

• Optimizing machine via bigger caches, reducing latency, increasing bandwidth...

• Optimizing program by exploiting temporal and spatial locality.

27

Multiprocessors and Extended HierarchyThings are necessarily more complex in the multiprocessor

case.

Key Issues:

• centralized memory- caches of other processors

• distributed memory- some local, some remote, and also network topology

• memory management– caches managed by hardware– main memory depends on programming model

• SAS: data movement between local and remote transparent• message passing: explicit

Levels closer to processor are lower latency and higher bandwidth.

28

Artifactual Communication in Extended Hierarchy

Accesses not satisfied in locally cause communication (both inherent and artifactual).

Artifactual communication is determined by program implementation and architecture interactions:

poor data allocation

unnecessary data in transfer

unnecessary transfers due to granularity

redundant communication

finite replication

Page 8: Maximizing Parallel Performance Review of Parallelizationusers.ece.northwestern.edu/~boz283/ece-453-original/ece453-lec-04... · Maximizing Parallel Performance Last Time: Introduced

29

Communication and Replication

Communication induced by finite capacity is most fundamental artifact (like cache size/miss rate in uniprocessors).

Basic concepts apply throughout extended memory hierarchy.

Classify “misses” in “cache” at any level as for uniprocessors:– compulsory or cold misses (no size effect)

– capacity misses (yes)

– conflict or collision misses (yes)

– communication or coherence misses (no)

Each type may be helped/hurt by large transfer granularity (spatial locality).

30

Working Sets

At first level cache (fully assoc, one-word block), inherent to algorithm.

Traffic from any type of miss can be local or nonlocal (communication).

First working set

Capacity-generated traffic(including conflicts)

Second working set

Dat

a tr

affic

Other capacity-independent communication

Cold-start (compulsory) traffic

Replication capacity (cache size)

Inherent communication

31

Orchestration for Performance

How can better orchestration help?

First: Reduce amount of communication.

• Inherent: change logical data sharing patterns in algorithm.

• Artifactual: exploit spatial, temporal locality in extended hierarchy (similar to uniprocessor).

Second: When communication is necessary, structure it to reduce cost.

32

Reducing Artifactual Communication

As we have seen orchestration is very model dependent.

Message Passing Model

• Communication and replication are both explicit.

• Even artifactual communication is in explicit messages.

Shared Address Space Model

• More interesting from an architectural perspective.

• Occurs transparently due to interactions of program and system.

Use shared address space to illustrate issues.

Page 9: Maximizing Parallel Performance Review of Parallelizationusers.ece.northwestern.edu/~boz283/ece-453-original/ece453-lec-04... · Maximizing Parallel Performance Last Time: Introduced

33

Exploiting Temporal Locality

• Structure program so that same memory locations are accessed in a short time frame.

• Map working set to memory hierarchy.

• Structure algorithm so working sets map well to hierarchy.– often techniques to reduce inherent communication do well here

– schedule tasks for data reuse once assigned

• With multiple data structures, may have to chose which one to exploit temporal locality on.

34

Example: Temporal Locality

Blocking is an example of a temporal locality exploitation technique.

�� �� � � � � � � � � � � �� � �� � �� � �� � �� � � � � � � � ��

� � � � � � � � � ��� � � �� � � �� � �� � �� � � �� � �� � � � � � ��� "!� � � � � # � � � � � � � � �%$

(a) Unblocked access pattern in a sweep (b) Blocked access pattern with B = 4

35

Exploiting Spatial LocalityGranularity plays an important role in spatial locality.

Types of granularity:

• allocation - for cache blocks and memory pages

• communication - for data transfer

• coherence - for data replication

Major spatial-related causes of artifactual communication:

• conflict misses• data distribution/layout (allocation granularity)

• fragmentation (communication granularity)• false sharing of data (coherence granularity)

36

Spatial Locality Example• Repeated sweeps over 2-d grid, each time adding 1 to

elements

• Natural 2-d versus higher-dimensional array representation

P6 P7P4

P8

P0 P3

P5 P6 P7P4

P8

P0 P1 P2 P3

P5

P2P1

Page straddlespartition boundaries:difficult to distribute memory well

Cache blockstraddles partitionboundary

(a) Two-dimensional array

Page doesnot straddlepartitionboundary

Cache block is within a partition

(b) Four-dimensional array

Contiguity in memory layout

Page 10: Maximizing Parallel Performance Review of Parallelizationusers.ece.northwestern.edu/~boz283/ece-453-original/ece453-lec-04... · Maximizing Parallel Performance Last Time: Introduced

37

Tradeoffs with Inherent Communication

Partitioning grid solver: blocks versus rows

• Blocks still have a spatial locality problem on remote data

• Rowwise can perform better despite worse inherent communication-to-computation ratio

Good spacial locality onnonlocal accesses atrow-oriented boudary

Poor spacial locality onnonlocal accesses atcolumn-orientedboundary

38

Performance Impact

Equation solver on SGI Origin2000

Spe

edup

Number of processors

Spe

edup

Number of processors

●●

▲▲

■■

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 310

5

10

15

20

25

30

●●●

■■■

▲▲

◆◆◆

✖✖

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 310

5

10

15

20

25

30

35

40

45

504D

4D-rr

■ 2D-rr

▲ 2D

◆ Rows-rr

✖ Rows● 2D

■ 4D

▲ Rows

39

Architectural Implications of Locality

Communication abstraction that makes exploiting it easy

For cache-coherent SAS, e.g.:

• Size and organization of levels of memory hierarchy

– cost-effectiveness: caches are expensive

– caveats: flexibility for different and time-shared workloads

• Replication in main memory useful? If so, how to manage?

– hardware, OS/runtime, program?

• Granularities of allocation, communication, coherence (?)

– small granularities => high overheads, but easier to program

40

Structuring CommunicationReduce cost of communication (inherent or artifactual).

Cost of communication as seen by process:

C = f * ( o + l + + tc - overlap)

– f = frequency of messages– o = overhead per message (at both ends)

– l = network delay per message

– nc = total data sent

– m = number of messages– B = bandwidth along path (determined by network, NI, assist)

– tc = cost induced by contention per message

– overlap = amount of latency hidden by overlap with comp. or communication

nc/mB

Page 11: Maximizing Parallel Performance Review of Parallelizationusers.ece.northwestern.edu/~boz283/ece-453-original/ece453-lec-04... · Maximizing Parallel Performance Last Time: Introduced

41

Reducing Overhead

Reduce number of messages m or overhead per message o.

o is usually determined by hardware or system software.

But programmer/compiler can coalesce data into larger messages:

• Easy for regular, coarse-grained communication

• Can be difficult for irregular, naturally fine-grained communication

42

Reducing Network Delay

Network delay component = f*h*th

• h = number of hops traversed in network

• th = link+switch latency per hop

Reducing f: communicate less, or make messages larger

Reducing h: map communications patterns to network topology

43

Reducing Contention

All resources have nonzero occupancy:• Memory, communication controller, network link, etc.• Can only handle so many transactions per unit time.

Effects of contention:• Increased end-to-end cost for messages.

• Reduced available bandwidth for individual messages.

• Causes imbalances across processors.

Particularly insidious performance problem:• Easy to ignore when programming.

• Slow down messages that don’t even need that resource.

• Effect can be devastating: Don’t flood a resource!

44

Types of ContentionNetwork contention and end-point contention (hot-spots)

Location and Module Hot-spotsLocation: e.g. accumulating into global variable, barrier

– solution: tree-structured communication�� ��� ��� � � �� �� � � � �� � � ���� � � �� � ��� � � � � ����

� � � � � � �

� � ��� �� � � � � � � � � � � �� � � ��� ��� � � �� � � �� �� � � � �� ��

� �� �� �� �� � � � � � �

� � � � �� � ��� �� ��� �� �� �� �� �� � �� � � �� �� �� � � � � !

� "� �� �� � � � � � � �� � �

Flat Tree structured

Contention Little contention

Page 12: Maximizing Parallel Performance Review of Parallelizationusers.ece.northwestern.edu/~boz283/ece-453-original/ece453-lec-04... · Maximizing Parallel Performance Last Time: Introduced

45

Overlapping Communication

Cannot afford to stall for high latencies.

Overlap with computation or communication to hide latency.

Requires extra concurrency (slackness), higher bandwidth.

Techniques:

• Prefetching

• Block data transfer

• Proceeding past communication

• Multithreading

46

Understanding Tradeoffs

Different goals often have conflicting demands:

• Load Balance– fine-grain tasks

– random or dynamic assignment

• Communication– usually coarse grain tasks

– decompose to obtain locality: not random/dynamic

• Extra Work– coarse grain tasks

– simple assignment

• Communication Cost:– big transfers: amortize overhead and latency

– small transfers: reduce contention

47

Processor-Centric Perspective

P 0 P 1 P 2 P 3

Busy-usefulBusy-overhead

Data-local

Synchronization Data-remote

Time (s)

Time (s)

100

75

50

25

100

75

50

25

(a) Sequential (b) Parallel with four processors

48

Relationship between Perspectives

Synch wait

Data-remote

Data-localOrchestration

Busy-overheadExtra work

Performance issueParallelization step(s) Processor time component

Decomposition/assignment/orchestration

Decomposition/assignment

Decomposition/assignment

Orchestration/mapping

Load imbalance and synchronization

Inherent communication volume

Artifactual communication and data locality

Communication structure

Page 13: Maximizing Parallel Performance Review of Parallelizationusers.ece.northwestern.edu/~boz283/ece-453-original/ece453-lec-04... · Maximizing Parallel Performance Last Time: Introduced

49

A Final Look At Speedup

Speedupprob(p) =

Goal is to reduce denominator components.

Both programmer and system have role to play.

Architecture cannot do much about load imbalance or too much communication.

But it can:

• reduce incentive for creating ill-behaved programs (efficient naming, communication and synchronization)

• reduce artifactual communication

• provide efficient naming for flexible assignment

• allow effective overlapping of communication

Busy(1) + Data(1)

Busyuseful(p)+Datalocal(p)+Synch(p)+Dateremote(p)+Busyoverhead(p)

50

Summary

There are numerous types of performance limiters in parallel systems.

There are an equal number of techniques for dealing with them.

Performance issues trade off with one another.