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Minimum Dynamic Power CMOS Circuits

Minimum Dynamic Power CMOS Circuits

Vishwani D. AgrawalRutgers University, Dept. of ECE

Piscataway, NJ 08854http://cm.bell-labs.com/cm/cs/who/va

Collaborators: M. L. Bushnell and T. Raja, Rutgers University(Support from NSF)

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Power in a CMOS GatePower in a CMOS GateVDD = 5VVDD = 5V

IDDIDD

GroundGround

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Problem StatementProblem Statement•Design a digital circuit for minimum

transient energy consumption by eliminating hazards

Ref: Agrawal (`97), Agrawal et al. (`99)

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Theorem 1Theorem 1•For correct operation with minimum

energy consumption, a Boolean gate must produce no more than one event per transition

Ref: Agrawal, et al., Proc. VLSI Design’99

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• Given that events occur at the input of a gate (inertial delay = d ) at times t1 < . . . < tn , the number of events at the gate output cannot exceed

Theorem 2Theorem 2

min ( min ( n n , 1 + ), 1 + )ttnn – t – t11

----------------dd

ttnn - t - t11 + d + d

tt11 t t22 t t33 t tnn t tnn + +

dd

timetime

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Minimum Transient Design

Minimum Transient Design

•Minimum transient energy condition for a Boolean gate:

| t| tii - t - tjj | < d | < d

Where tWhere tii and t and tjj are arrival times of input are arrival times of input

events and d is the inertial delay of gateevents and d is the inertial delay of gate

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Linear Program (LP)Linear Program (LP)

•Variables: gate and buffer delays

•Objective: minimize number of buffers

•Subject to: overall circuit delay

•Subject to: minimum transient condition for multi-input gates

•AMPL, MINOS 5.5 (Fourer, Gay and Kernighan)

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Limitations of This LPLimitations of This LP

•Constraints are written by path enumeration.

•Since number of paths in a circuit is exponential in circuit size, the formulation is infeasible for large circuits.

•Example: c880 has 6.96M constraints.

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A New LP ModelA New LP Model

•Introduce two new variables per gate output:

• ti Earliest time of signal transition at gate i.

• Ti Latest time of signal transition at gate i.t1, T1

tn, Tn

.

.

.

ti, Ti

Ref: Raja et al. (`03)

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New Linear ProgramNew Linear Program

•Gate variables d4 . . . d12

•Buffer Variables d15 . . . d29

•Corresponding window variables t4 . . . t29 and T4 . . . T29.

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Multiple-Input Gate ConstraintsMultiple-Input Gate Constraints

T7 > T5 + d7; t7 < t5 + d7; d7 > T7 - t7;

T7 > T6 + d7; t7 < t6 + d7;

For Gate 7:

t5 T5

t6 T6t7 T7

t5+d7 T5+d7

t6+d7 T6+d7

Input windows: Outputwindows:

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Single-Input Gate ConstraintsSingle-Input Gate Constraints

T16 + d19 = T19 ;

t16 + d19 = t19 ;

Buffer 19:

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Overall Delay ConstraintsOverall Delay Constraints

T11 < maxdelay

T12 < maxdelay

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Why New Model is Superior?Why New Model is Superior?

• Path constraints from old model:2 × 2 × … 2 = 2n paths between an I/O pair

• For new model, a single constraint per PO controls I/O delay.

• For new model, number of minimum energy constraints for each gate depends on gate inputs.

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Comparison of ConstraintsComparison of Constraints

Number of gates in circuit

Nu

mb

er

of

con

str

ain

ts

c880

3,611

6.96x106

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Results: 1-Bit AdderResults: 1-Bit Adder

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Estimation of PowerEstimation of Power•Circuit is simulated by an event-driven

simulator for both optimized and un-optimized gate delays.

•All transitions at a gate are counted as Events[gate].

•Power consumed Events[gate] x # of fanouts.

•Ref: “Effects of delay model on peak power estimation of VLSI circuits,” Hsiao, et al. (ICCAD`97).

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Original 1-Bit AdderOriginal 1-Bit Adder

Colo

r co

des

for

num

ber

of

transi

tions

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Optimized 1-Bit AdderOptimized 1-Bit Adder

Colo

r co

des

for

num

ber

of

transi

tions

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Benchmark CircuitsBenchmark CircuitsCircuit

C432

C880

C6288

c7552

Maxdel.(gates)

1734

2448

4794

4386

No. ofBuffers

9566

6234

294120

366111

Average

0.720.62

0.680.68

0.400.36

0.28* 0.26*

Peak

0.670.60

0.540.52

0.360.34

0.24* 0.22*

Normalized Power

* Corrected data

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Results: 4-Bit ALUResults: 4-Bit ALU

maxdelay Buffers inserted

7 5

10 2

12 1

15 0

Power Savings :

Peak = 33 %, Average = 21 %

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Physical DesignPhysical Design

Gatel/w Gate

l/w

Gatel/w

Gatel/w

Gate delay modeled as a linear function of gate size, total load capacitance, and fanout gate sizes (Berkelaar and Jacobs, 1996).

Layout circuit with some nominal gate sizes.

Enter extracted routing delays in LP as constants and solve for gate delays.

Change gate sizes as determined from a linear system of equations.

Iterate if routing delays change.

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Power Dissipation of ALU4Power Dissipation of ALU4En

erg

y in

nan

ojo

ule

s

0

1

2

3

4

5

6

7

0.0 0.5 1.0 1.5 2.0microseconds

Original ALUdelay ~ 3.5ns

Minimum energy ALUdelay ~ 10ns

1 micron CMOS, 57 gates, 14 PI, 8 PO100 random vectors simulated in Spice

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ALU: Original and OptimizedALU: Original and Optimized

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ReferencesReferences• R. Fourer, D. M. Gay and B. W. Kernighan, AMPL: A Modeling

Language for Mathematical Programming, South San Francisco: The Scientific Press, 1993.

• M. Berkelaar and E. Jacobs, “Using Gate Sizing to Reduce Glitch Power,” Proc. ProRISC Workshop, Mierlo, The Netherlands, Nov. 1996, pp. 183-188.

• V. D. Agrawal, “Low Power Design by Hazard Filtering,” Proc. 10th Int’l Conf. VLSI Design, Jan. 1997, pp. 193-197.

• M. Hsiao, E. M. Rudnick and J. H. Patel, “Effects of Delay Model in Peak Power Estimation of VLSI Circuits,” Proc. ICCAD, Nov. 1997, pp. 45-51.

• V. D. Agrawal, M. L. Bushnell, G. Parthasarathy and R. Ramadoss, “Digital Circuit Design for Minimum Transient Energy and Linear Programming Method,” Proc. 12th Int’l Conf. VLSI Design, Jan. 1999, pp. 434-439.

• V. D. Agrawal, “Low Power Circuits Through Hazard Pulse Suppression,” US Patent 5,983,007, Nov. 9, 1999.

• T. Raja, V. D. Agrawal and M. L. Bushnell, “Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program,” Proc. 16th Int’l Conf. VLSI Design, Jan. 2003.

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ConclusionConclusion• Obtained an LP constraint-set that is linear in the size of

the circuit. LP solution:

• Eliminates glitches at all gate outputs,

• Holds I/O delay within specification, and

• Combines path-balancing and hazard-filtering to

minimize the number of delay buffers.

• New LP produces results exactly identical to old LP

requiring exponential constraint-set.

• Results show peak power reduction up to 78% and

average power savings up to 74%.