mb91f467r preliminary datasheet · • 5 chip select areas with individual area size, data bus...

FUJITSU SEMICONDUCTOR

MB91F467R preliminary datasheet

MB91460 series

Fujitsu Limited

Fujitsu Limited MB91F467R preliminary datasheet ver 0.16

Fujitsu Confidential - Internal Use Only of 57

Revision History

Latest revision is 0.16

Version Date Remark 0.10 2006-05-12 Initial draft 0.11 2006-05-15 feature list, I/O map and operating conditions are changed 0.12 2006-05-24 Change comments in the pin assignment figure 0.13 2006-08-01 Pin assignment and Flash serial programming support are

changed. 0.14 2006-08-17 Register(0xC03) is changed to “reserved”. 0.15 2006-08-18 Register names(0x678-67A) are changed. 0.16 2006-08-25 Oprrating temperature correction(105C --> 85C)



Table of contents

1.1 Block Diagram.............................................................................................................4 2 Feature List ......................................................................................................................5

2.1 Overview Table ...........................................................................................................5 2.2 Core Functionality .......................................................................................................6

2.2.1 Memory Map.........................................................................................................6 2.2.2 FR70 CPU Core....................................................................................................7 2.2.3 Instruction Cache..................................................................................................7 2.2.4 Interrupt Controller................................................................................................7 2.2.5 Internal Data RAM ................................................................................................8 2.2.6 Internal Program/Data RAM .................................................................................8 2.2.7 Embedded Program/Data Memory .......................................................................8 2.2.8 External Bus Interface ..........................................................................................9 2.2.9 DMA Controller .....................................................................................................9

2.3 Peripheral Function .....................................................................................................9 3 I/O Map............................................................................................................................13 4 Interrupt Vector Table ...................................................................................................18 5 Package and Pin Assignment.......................................................................................18

5.1 Pin Assignment .........................................................................................................18 5.2 Package ....................................................................................................................18 5.3 I/O Pins and their functions .......................................................................................18

6 Boot procedure ..............................................................................................................18 7 Input threshold level settings.......................................................................................18 8 Shutdown mode.............................................................................................................18

8.1 Registers ...................................................................................................................18 8.1.1 SHDE : shut down enable...................................................................................18 8.1.2 EXTE : External interrupt enable ........................................................................18 8.1.3 EXTF : External interrupt flag .............................................................................18 8.1.4 EXTLV : External interrupt Level ........................................................................18

9 Flash memory and security ..........................................................................................18 10 Flash serial programming support ..............................................................................18 11 Electrical Characteristics..............................................................................................18

11.1 Absolute Maximum Ratings ......................................................................................18 11.2 Operating Conditions ................................................................................................18 11.3 Converter Characteristics..........................................................................................18



Overview

The MB91F467R is a device of the M91460 family. The corresponding evaluation device is the MB91V460.

1.1 Block Diagram

Ext. Int x 14

I2C x 3

LIN-USART x 5

FRT x 8

OCU x 4FR70 CPU0.18 um96 MHz

FR70 CPU0.18 um96 MHz

WatchdogInt. Control

CAN x 332 msg

Bit Search

EDSU/MPU

Harvard BusConverter

RAM 32KB

FLASH 1 MB

RAM 32KB

DMA (5 ch)

Ext. I/F

Pre - fetch 8KB

BootROM 4KB

4Mhz

32 kHz

P x

Core : 1.8V IO : 5.0V-3.3V

ICU x 8

R - Tim er x 8

RTC Ext. Int x 16

I2C x 3

10bit ADC x 16

LIN-USART x 7

FRT x 8

OCU x 4FR70 CPU0.18 um96 MHz

FR70 CPU0.18 um80 MHz

WatchdogInt. Control

CAN x 232 msg + 64 msg

Bit Search

EDSU/MPU

Harvard BusConverter

FLASH 1 MB

RAM32KB+16KB

DMA (5 ch) GPIO

Ext. I/F

Pre - fetch 8KB

BI-ROM 4KB

4Mhz

32 kHz

PPG x 8

ICU x 4

R - Tim er x 5

RTC

QFP208 QFP176

DA

TA

INS

TR

RAM 16KB

RC Osc. 100kHz / 2MHz Subclock 32 kHz Power Control

Clock Control

Clock modulation



2 Feature List

2.1 Overview Table

*1: Max freqency operation is allowed when the clock modulator is on.

Feature MB91V460 MB91F467R Core frequency 80 MHz 80(92*1) MHz Resource frequency 40 MHz 40(46*1) MHz Watchdog yes Yes Bit Search yes Yes Reset Input yes Yes Clock Modulator (yes) Yes DMA 5 ch 5 ch MPU/EDSU 16 ch 4 ch Flash external 1088 kB Flash Protection n.a. Yes D-bus RAM 64 kB 32 kB+16kB GP RAM 64 kB 16 kB Direct mapped cache 16kB 8 kB BI-ROM - 4 kB RTC 1 ch 1 ch Free Running Timer 8 ch 4 ch ICU 8 ch 4 ch OCU 8 ch 4 ch Reload Timer 8 ch 5 ch PPG 16 ch 8 ch C_CAN 6 ch (128 msg buffer) 2 ch (32msg +64msg) LIN-USART 16 ch (4 ch FIFO) 7 ch (4 ch FIFO) I2C 4 ch 3 ch FR external bus 32-bit address / 32-bit data 24-bit address / 16-bit data External Interrupts 16 ch 16 ch NMI 1 1 ADC (10-bit) 32 ch 16 ch Low voltage detection yes Yes Package BGA 660 LQFP-176



2.2 Core Functionality 2.2.1 Memory Map

MB91F467R

RO

MS0

-7 s

ettin

g fix

ed to

inte

rnal

are

a R

OM

S8-1

5 se

tting

fixe

d to

ext

erna

l are

a

available, but no memory mapped

access

Flash Memory Area (1024 kB + 64 kB)

or

External Bus Area depending on ROMA

setting

Legend Memory available in this area Memory not available in this area

0048:0000h-004F:FFFFh

0050:0000h-FFFF:FFFFh

0014:0000h-0017:FFFFh

0020:0000h-0027:FFFFh

ROMS12(512 kB)

MB91V460A

External Bus I-Cache (4 kB) orInstruction RAM (4 kB)

0000:2000h- 0000:5FFFh Flash Memory I-Cache (16 kB) or

Instruction RAM (16 kB)

0001:0000h- 0001:FFFFh

0000:0000h- 0000:00FFh 0000:0100h- 0000:01FFh 0000:0200h- 0000:03FFh

External Bus Area

External Bus Area

0038:0000h-003F:FFFFh

0040:0000h-0047:FFFFh

0028:0000h-002F:FFFFh

0030:0000h-0037:FFFFh

0018:0000h-001B:FFFFh

001C:0000h-001F:FFFFh

000E:0000h-000F:FFFFh

0010:0000h-0013:FFFFh

0004:0000h-0005:FFFFh

0006:0000h-0007:FFFFh

0008:0000h-0009:FFFFh

000A:0000h-000B:FFFFh

000C:0000h-000D:FFFFh

External Bus I-Cache (4 kB) or Instruction RAM (4 kB)

0002:0000h-0002:FFFFh

I/O Byte Data

Flash Memory Control Flash Memory I-Cache Control

I/O

CAN

DMA

0000:0100h-0000:01FFh

I/O Halfword Data 0000:0200h-0000:03FFh I/O Word Data

0000:0000h-0000:00FFh

0000:2000h-0000:5FFFh

0000:C000h-0000:CFFFh

0003:0000h-0003:FFFFh

0000:0400h-0000:0FFFh

0000:7000h-0000:70FFh

0000:1000h-0000:10FFh

0000:8000h-0000:BFFFh

0001:0000h-0001:FFFFh

ROMS13(512 kB)

ROMS14(512 kB)

ROMS15(512 kB)

ROMS08(256 kB)

ROMS09(256 kB)

ROMS10(512 kB)

ROMS11(512 kB)

Emulation SRAM Area (max 4.864 kB)

or

External Bus Area depending on ROMA/ROMS

setting

External Bus Area

ROMS00(128 kB)

ROMS01(128 kB)

ROMS02(128 kB)

ROMS03(128 kB)

ROMS04(128 kB)

ROMS05(128 kB)

ROMS06(256 kB)

ROMS07(256 kB)

Instruction/Data RAM (64 kB)

I/O Byte Data

I/O Halfword Data

I/O Word Data

I/O

DMA

Flash Memory Control Flash Memory I-Cache Control

CAN

Data RAM (64 kB)

0038:0000h- 003F:FFFFh 0040:0000h- 0047:FFFFh 0048:0000h- 004F:FFFFh 0050:0000h- FFFF:FFFFh

001C:0000h- 001F:FFFFh 0020:0000h- 0027:FFFFh 0028:0000h- 002F:FFFFh 0030:0000h- 0037:FFFFh

000E:0000h- 000F:FFFFh 0010:0000h- 0013:FFFFh 0014:0000h- 0017:FFFFh 0018:0000h- 001B:FFFFh

0006:0000h- 0007:FFFFh 0008:0000h- 0009:FFFFh 000A:0000h- 000B:FFFFh 000C:0000h- 000D:FFFFh

0000:0400h- 0000:0FFFh

0002:0000h- 0002:FFFFh 0003:0000h- 0003:FFFFh 0004:0000h- 0005:FFFFh

0000:1000h- 0000:10FFh

0000:7000h- 0000:70FFh 0000:8000h- 0000:BFFFh 0000:C000h- 0000:CFFFh

Boot ROM (4 kB) BI ROM (4 kB)

Flash Memory I-Cache (8 kB) or Instruction RAM (8 kB)

Data RAM (32 kB+16kB)

Instruction/Data RAM (16 kB)



2.2.2 FR70 CPU Core

• 32-bit RISC, load/store architecture, pipeline 5 stages

• Maximum operating frequency: Core clock = 80 MHz (Source oscillation= 4 MHz, multiplied by 20 (PLL clock multiplier method))

• General-purpose registers: 16 x 32 bits

• 16-bit fixed-length instruction (Base instruction)

• 32-bit linear address space: 4 Gbytes

• Instructions suitable for embedded application

• Transfer command between memories

• Bit-processing instruction

• Barrel-shift instructions

• Instructions supporting C-language

• Function's enter command /exit command

• Multi-load/store command of register contents

• Assembler statement is also easily available Register's interlock function

• Multiplier's embedded application/command level support

• Signed 32-bit multiplication: 5 cycles

• Signed 16-bit multiplication: 3 cycles

• Interrupt (PC/PS are saved): 6 cycles (16 priority level)

• Harvard architecture enables simultaneous execution of program access and data access

• Memory protection function

• Embedded debug support

• Commands compatible with FR family

2.2.3 Instruction Cache

• Direct mapped I-cache

• 8 kByte integrated

• Lock function enabling programs to be resident

2.2.4 Interrupt Controller

• A total of 16 external interrupt lines ( 10 normal interrupt pins, 6 interrupt pins shared (with peripheral inputs for Wake Up from STOP mode, e.g. CAN RX and I2C SDA/SCL)

• Interrupts from internal peripherals (128 interrupt vectors)

• Priority levels programmable for normal interrupt lines excluding the nonmaskable one (16 levels)

• Capable of using the normal interrupt and nonmaskable interrupt pins for Wake Up from STOP mode



2.2.5 Internal Data RAM

• 16 kBytes and 32kBytes integrated

• Zero wait state for read/write access of 16kBytes

• One wait state for read/write access of 32kBytes

2.2.6 Internal Program/Data RAM

• 16 kBytes integrated

• Zero wait state for read/write access of instructions

• One wait state for read/write access of data

2.2.7 Embedded Program/Data Memory

• 1 MByte Flash

• Programmable wait state for read/write access

• Flash security

ROMS1

ROMS0

Flash memory map in CPU mode (MD[2:0] = 00x)

addr+6

ROMS5

ROMS4

ROMS6

ROMS7

ROMS3

ROMS2

dat[31:16] dat[15:0]

dat[31:0] dat[31:0]

dat[31:16] dat[15:0]16bit write mode

32bit write mode

addr+7addr+2

SA0 (8kB)

addr

0014:FFFFh0014:C000h SA7 (8kB)

SA5 (8kB)

SA3 (8kB)

SA1 (8kB)

SA23 (64kB)

SA6 (8kB)

SA4 (8kB)

SA2 (8kB)

SA22 (64kB)

SA20 (64kB)

SA16 (64kB)

SA10 (64kB)

SA21 (64kB)

0013:FFFFh0012:0000h

0011:FFFFh0010:0000h

SA18 (64kB) SA19 (64kB)

0014:BFFFh0014:8000h

0014:7FFFh0014:4000h

0014:3FFFh0014:0000h

000F:FFFFh000E:0000h

SA15 (64kB)

SA12 (64kB) SA13 (64kB)

addr+0 addr+1 addr+3 addr+4 addr+5

SA11 (64kB)

SA8 (64kB) SA9 (64kB)

000D:FFFFh000C:0000h

000B:FFFFh000A:0000h

0009:FFFFh0008:0000h

0007:FFFFh0006:0000h

0005:FFFFh0004:0000h

SA17 (64kB)

SA14 (64kB)



2.2.8 External Bus Interface

• 5 chip select areas with individual area size, data bus width selection (8, 16-bit) and wait

• Address bus 24 bit wide

• Programmable auto-wait function or external wait input (RDY)

• Basic bus cycles : 2 cycles

• Prefetch function

• Burst access function

• SDRAM support

2.2.9 DMA Controller

• Four transfer modes supported: single/block, burst, continuous transfer, and fly-by

• 5 channels (including 1 channel for external-to-external transfer)

• 3 types of transfer sources (external pins/internal peripherals/and software)

• Up to 128 selectable internal transfer sources

• Addressing mode: Specifying up to 32-bit addresses (Increment/decrement/fixed)

• Transfer mode (Demand transfer/burst transfer/step transfer/block transfer)

• Fly-by transfer supported (between external I/O and memory)

• Transferred data size selectable from among 8, 16, and 32 bits

2.3 Peripheral Function

• General-purpose port: All functional pins can be used as general-purpose ports, if the corresponding function is not needed.

• N channel open drain port out of above: 6 (for I2C)

• A/D converter : 16 channels (1 unit)

• Series-parallel type

• Resolution: 10 bits

• Minimum conversion time: 3μs

• Single conversion mode

• Continuous conversion mode

• Stop conversion mode

• Activation by software or external trigger can be selected

• Reload timer 7 and A/D Converter co-operate



• External interrupt input : 16 channels

• Can be programmed to be edge sensitive or level sensitive

• Interrupt mask and request pending bits per channel

• 2 channels combined with CAN RX for wakeup • 4 channels combined with I2C SDC/SCL for wakeup

• Bit search module (using REALOS)

• Function to search the first bit position of “1”, “0”, “Changed” from MSB (most significant bit) within 1 word

• Reload timer : 16 bits x 5 channels

• 16-bit reload counter

• Includes clock prescaler (fRES/21, fRES/23, fRES/25, fRES/26, fRES/27)

• Free-run timer : 16 bits x 4 channels

• 16-bit free running counter, signals an interrupt when overflow or match with compare register

• Includes prescaler (fRES/22, fRES/24, fRES/25, fRES/26)

• Timer data register has R/W access

• PPG : 16 bit x 8 channels

• 16 bit down counter, cycle and duty setting registers

• Interrupt at triggering, cycle or duty match

• PWM operation and one-shot operation

• Internal prescaler allows fRES/20, fRES/22, fRES/24, fRES/26 as counter clock

• Can be triggered by software or reload timer

• Reload timer 0/1 available as trigger for PPG 0/1/2/3

• Reload timer 2/3 available as trigger for PPG 4/5/6/7

• External trigger for PPG 0 (shared)




• Input capture : 16 bits x 4 channels

• Rising edge, falling edge or rising & falling edge sensitive

• Free-run timer 0 and input capture 0/1 co-operate

• Free-run timer 1 and input capture 2/3 co-operate



• Output compare : 16 bits x 4 channels

• Signals an interrupt when a match with of 16-bit IO timer occurs

• An output signal can be generated

• Free-run timer 2 and output compare 0/1 co-operate

• Free-run timer 3 and output compare 2/3 co-operate

• LIN-USART (LIN=Local Interconnect Network) : 7 channels

• Full-duplex double buffer system ( ch with 16 byte RX/TX FIFO buffer each)

• With parity/without parity selectable

• 1 or 2 stop bits selectable

• 7 or 8 bits data length selectable

• NRZ type transfer format

• Asynchronous /synchronous communications selectable

• Master-slave communication function (multiprocessor mode)

• Dedicated baud rate prescaler is embedded in each channel

• External clock is able to use as transfer clock

• Parity error, frame error, and overrun error detecting functions

• SPI compatible

• LIN master and slave

• LIN USART 0 and ICU 0 co-operate (for LIN sync field in slave mode)




• CAN : 2 channels

• Supports CAN protocol version 2.0 part A and B

• Bit rates up to 1 Mbit/s

• 32 message objects(ch0) and 64 message objects(ch1)

• Each message object has its own identifier mask

• Programmable FIFO mode (cocatenation of message objects)

• Maskable interrupt

• Programmable loop-back mode for self-test operation

• I2C (400k fast mode) : 3 channels

• Master or slave transmission

• Arbitration function

• Clock synchronization function

• Slave address and general call address detect function

• Transfer direction detect function

• Start condition repeat generation and detection function



• Bus error detect function

• Compatible to I2C standard and fast mode specification (operation up to 400 kHz, 10 bit addressing)

• Includes clock divider functionality

• SCL and SDA lines include optional noise filter. The noise filter allows the suppression of spikes in the range of 1 to 1.5 cycles of RES

• Timebase/watchdog timer (26 bits)

• Adjustable watchdog timer interval (between 220 and 226 system clock cycles)

• Real-time clock (counts during stop mode)

• RTC module can be clocked either from 32 kHz quartz, 4 MHz quartz or from the RC Oscillator

• Facility to correct oscillation deviation (subclock calibration)

• Read/write accessible second/minute/ hour registers

• Can signal interrupts every halfsecond/second/ minute/hour/day

• Internal clock divider and prescaler provide exact 1s clock based on a 4 MHz or a 32 kHz clock input

• Prescaler value for 4 MHz is 1E847FH

• Prescaler value for 32 kHz is 003FFFH

• Clock modulator

• Reduction of Electro Magnetic Emission (EME)

• Subclock calibration

• Calibration of the RTC timer in 32 kHz or RC oscillator operation, based on the more accurate 4 MHz quartz is possible

• Main oscillation stabilisation timer

• 23 bit counter for main oscillation stabilisation wait when running in sub clock mode

• Generates an interrupt when stabilisation time has elapsed

• Sub oscillation stabilisation timer

• 15 bit counter for sub oscillation stabilisation wait when running in main clock mode

• Generates an interrupt when stabilisation time has elapsed



3 I/O Map This section shows the association between memory space and each register of peripheral resources. • Table convention

AddressAddress offset/Register name Block

+0 +1 +2 +3000000H PDRD[R/W] PDR1[R/W] PDR2[R/W] PDR3[R/W]

xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxxT-unit

Port data register

Read/Write attribute (R: Read, W: Write)

Register initial value ("0", "1", "X" : undefined, "-" : not implemented)

Register name (First column register is 4n address, Second column register is 4n+2 address...)

Leftmost register address(For Word access, first register becomes MSB side of the data.)

MSB LSB

Note : Bit value of register shows initial values as follows.

•"1": Initial value is "1".

• "0": Initial value is "0".

• "X": Initial value is indeterminate.

• "N/A": No physical register exists in the position.

Do not use other data access attributes to access data.



Register Address

+0 +1 +2 +3

Block

000000H PDR00 [R/W] XXXXXXXX

PDR01 [R/W] XXXXXXXX res. res.

000004H res. PDR05 [R/W] XXXXXXXX

PDR06 [R/W] XXXXXXXX


000008H PDR08 [R/W] XXXX - - XX

PDR09 [R/W] - - - XXXXX

PDR10 [R/W] - XXXXXXX

PDR11 [R/W] - - - - - - XX

00000CH res. PDR13 [R/W] - - - - - XXX

PDR14 [R/W] - - - - XXXX

PDR15 [R/W] - - - - XXXX

000010H PDR16 [R/W] X - - - - - - -


PDR18 [R/W] - - - - - XXX

PDR19 [R/W] - XXX - XXX

000014H PDR20 [R/W] - XXX - XXX

PDR21 [R/W] - XXX - XXX

PDR22 [R/W] XXXXXX – X

PDR23 [R/W] - X - XXXXX

000018H PDR24 [R/W] XXXXXXXX res. res. res.

00001CH PDR28 [R/W] XXXXXXXX

PDR29 [R/W] XXXXXXXX res. res.

R-bus Port Data Register

000020H - 00002CH

reserved

000030H EIRR0 [R/W] 00000000

ENIR0 [R/W] 00000000

ELVR0 [R/W] 00000000 00000000

Ext. INT 0-7 NMI

000034H EIRR1 [R/W] 00000000

ENIR1 [R/W] 00000000

ELVR1 [R/W] 00000000 00000000 Ext. INT 8-15

000038H DICR [R/W] - - - - - - - 0

HRCL [R/W] 0 - - 11111 res. DLYI/I-unit

00003CH reserved

000040H SCR00 [R/W,W] 00000000

SMR00 [R/W,W]00000000

SSR00 [R/W,R] 00001000

RDR00/TDR00 [R/W]

00000000

000044H ESCR00 [R/W] 00000X00

ECCR00 [R/W,R,W] -00000XX

Res.

USART(LIN) 0

000048H SCR01 [R/W,W] 00000000

SMR01 [R/W,W]00000000

SSR01 [R/W,R] 00001000

RDR01/TDR01 [R/W]

00000000

00004CH ESCR01 [R/W] 00000X00


res.

USART(LIN) 1



Register Address

+0 +1 +2 +3

Block

000050H SCR02 [R/W,W] 00000000

SMR02 [R/W,W]00000000

SSR02 [R/W,R] 00001000

RDR02/TDR02 [R/W]

00000000

000054H ESCR02 [R/W] 00000X00


res.

USART(LIN) 2

000058H SCR03 [R/W,W] 00000000

SMR03 [R/W,W]00000000

SSR03 [R/W,R] 00001000

RDR03/TDR03 [R/W]

00000000

00005CH ESCR03 [R/W] 00000X00


res.

USART(LIN) 3

000060H SCR04 [R/W,W] 00000000

SMR04 [R/W,W]00000000

SSR04 [R/W,R] 00001000

RDR04/TDR04 [R/W]

00000000

000064H ESCR04 [R/W] 00000X00


FSR04 [R] - - - 00000

FCR04 [R/W] 0001 - 000

USART(LIN) 4 with FIFO

000068H SCR05 [R/W,W]

00000000 SMR05 [R/W,W]

00000000 SSR05 [R/W,R]

00001000

RDR05/TDR05 [R/W]

00000000

00006CH ESCR05 [R/W]

00000X00


FSR05 [R] - - - 00000

FCR05 [R/W] 0001 - 000


000070H SCR06 [R/W,W]

00000000 SMR06 [R/W,W]

00000000 SSR06 [R/W,R]

00001000

RDR06/TDR06 [R/W]

00000000

000074H ESCR06 [R/W]

00000X00


FSR06 [R] - - - 00000

FCR06 [R/W] 0001 - 000


000078H

00007CH reserved



Register Address

+0 +1 +2 +3

Block

000080H BGR100 [R/W] 00000000

BGR000 [R/W] 00000000

BGR101 [R/W] 00000000

BGR001 [R/W] 00000000

000084H BGR104 [R/W] 00000000

BGR004 [R/W] 00000000

BGR105 [R/W] 00000000

BGR005 [R/W] 00000000

000088H BGR106 [R/W] 00000000

BGR006 [R/W] 00000000

BGR107 [R/W] 00000000

BGR007 [R/W] 00000000

00008CH BGR102 [R/W] 00000000

BGR002 [R/W] 00000000 res. res.

Baudrate Generator USART (LIN)

0-6

000090H

- 0000CCH

reserved

0000D0H IBCR0 [R/W] 00000000

IBSR0 [R] 00000000

ITBAH0 [R/W] - - - - - - 00

ITBAL0 [R/W] 00000000

0000D4H ITMKH0 [R/W] 00 - - - - 11

ITMKL0 [R/W] 11111111

ISMK0 [R/W] 01111111

ISBA0 [R/W] - 0000000

0000D8H res. IDAR0 [R/W] 00000000

ICCR0 [R/W] - 0011111 res.

I2C 0

0000DCH IBCR1 [R/W] 00000000

IBSR1 [R] 00000000

ITBAH1 [R/W] - - - - - - 00

ITBAL1 [R/W] 00000000

0000E0H ITMKH1 [R/W] 00 - - - - 11

ITMKL1 [R/W] 11111111

ISMK1 [R/W] 01111111

ISBA1 [R/W] - 0000000

0000E4H res. IDAR1 [R/W] 00000000

ICCR1 [R/W] - 0011111 res.

I2C 1

0000E8H - 0000FCH

reserved

000100H GCN10 [R/W] 00110010 00010000 res. GCN20 [R/W]

- - - - 0000 PPG Control 0-3

000104H GCN11 [R/W] 00110010 00010000 res. GCN21 [R/W]

- - - - 0000 PPG Control 4-7

000108H reserved

000110H PTMR00 [R] 11111111 11111111

PCSR00 [W] XXXXXXXX XXXXXXXX

000114H PDUT00 [W] XXXXXXXX XXXXXXXX

PCNH00 [R/W] 0000000 -

PCNL00 [R/W] 000000 - 0

PPG 0

000118H PTMR01 [R] 11111111 11111111


00011CH PDUT01 [W] XXXXXXXX XXXXXXXX

PCNH01 [R/W] 0000000 -

PCNL01 [R/W] 000000 - 0

PPG 1



Register Address

+0 +1 +2 +3

Block

000120H PTMR02 [R] 11111111 11111111



PCNH02 [R/W] 0000000 -

PCNL02 [R/W] 000000 - 0

PPG 2

000128H PTMR03 [R] 11111111 11111111



PCNH03 [R/W] 0000000 -

PCNL03 [R/W] 000000 - 0

PPG 3

000130H PTMR04 [R] 11111111 11111111



PCNH04 [R/W] 0000000 -

PCNL04 [R/W] 000000 - 0

PPG 4

000138H PTMR05 [R] 11111111 11111111



PCNH05 [R/W] 0000000 -

PCNL05 [R/W] 000000 - 0

PPG 5

000140H PTMR06 [R] 11111111 11111111



PCNH06 [R/W] 0000000 -

PCNL06 [R/W] 000000 - 0

PPG 6

000148H PTMR07 [R] 11111111 11111111



PCNH07 [R/W] 0000000 -

PCNL07 [R/W] 000000 - 0

PPG 7

000170H

- 00017CH

Reserved

000180H res. ICS01 [R/W] 00000000 res. ICS23 [R/W]

00000000

000184H IPCP0 [R] XXXXXXXX XXXXXXXX

IPCP1 [R] XXXXXXXX XXXXXXXX

000188H IPCP2 [R] XXXXXXXX XXXXXXXX

IPCP3 [R] XXXXXXXX XXXXXXXX

Input Capture 0-3

00018CH OCS01 [R/W] - - - 0 - - 00 0000 - - 00

OCS23 [R/W] - - - 0 - - 00 0000 - - 00

000190H OCCP0 [R/W] XXXXXXXX XXXXXXXX

OCCP1 [R/W] XXXXXXXX XXXXXXXX

000194H OCCP2 [R/W] XXXXXXXX XXXXXXXX

OCCP3 [R/W] XXXXXXXX XXXXXXXX

Output Compare 0-3



Register Address

+0 +1 +2 +3

Block

000198H

00019CH Reserved

0001A0H ADERH [R/W] 00000000 00000000

ADERL [R/W] 00000000 00000000

0001A4 ADCS1 [R/W] 00000000

ADCS0 [R/W] 00000000

ADCR1 [R] 000000XX

ADCR0 [R] XXXXXXXX

0001A8H ADCT1 [R/W] 00010000

ADCT0 [R/W] 00101100

ADSCH [R/W] - - - 00000

ADECH [R/W] - - - 00000

A/D

Converter

0001ACH res. ACSR0 [R/W] - 11XXX00 res. res. Alarm

Comparator 0

0001B0H TMRLR0 [W] XXXXXXXX XXXXXXXX

TMR0 [R] XXXXXXXX XXXXXXXX

0001B4H res. TMCSRH0

[R/W] - - - 00000

TMCSRL0 [R/W]

0 - 000000

Reload Timer 0 (PPG 0-1)

0001B8H TMRLR1 [W] XXXXXXXX XXXXXXXX


0001BCH res. TMCSRH1

[R/W] - - - 00000

TMCSRL1 [R/W]

0 - 000000


0001C0H TMRLR2 [W] XXXXXXXX XXXXXXXX


0001C4H res. TMCSRH2

[R/W] - - - 00000

TMCSRL2 [R/W]

0 - 000000


0001C8H TMRLR3 [W] XXXXXXXX XXXXXXXX


0001CCH res. TMCSRH3

[R/W] - - - 00000

TMCSRL3 [R/W]

0 - 000000


0001D0H - 0001E4H

0001E8H TMRLR7 [W] XXXXXXXX XXXXXXXX


0001ECH res. TMCSRH7

[R/W] - - - 00000

TMCSRL7 [R/W]

0 - 000000

Reload Timer 7 (ADC)

0001F0H TCDT0 [R/W] XXXXXXXX XXXXXXXX res. TCCS0 [R/W]

00000000

Free Running Timer 0 (ICU 0-1)



Register Address

+0 +1 +2 +3

Block


00000000

Free Running Timer 1 (ICU 2-3)


00000000

Free Running Timer 2 (OCU 0-1)

0001FCH TCDT3 [R/W] XXXXXXXX XXXXXXXX res. TCCS3 [R/W]

00000000

Free Running Timer 3 (OCU 2-3)

000200H DMACA0 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX

000204H DMACB0 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX


00020CH DMACB1 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX




00021CH DMACB3 [R/W] 00000000 00000000 XXXXXXXX XXXXXXXX



000228H

- 00023CH

reserved

000240H DMACR [R/W] 00 - - 0000 reserved

DMAC

000244H - 000364H

reserved



Register Address

+0 +1 +2 +3

Block

000368H IBCR2 [R/W] 00000000

IBSR2 [R] 00000000

ITBAH2 [R/W] - - - - - - 00

ITBAL2 [R/W] 00000000

00036CH ITMKH2 [R/W] 00 - - - - 11

ITMKL2 [R/W] 11111111

ISMK2 [R/W] 01111111

ISBA2 [R/W] - 0000000

000370H res. IDAR2 [R/W] 00000000

ICCR2 [R/W] - 0011111 res.

I2C 2

000374H - 00038CH

reserved

000390H ROMS [R] 11111111 00000000 res. ROM Select

Register

000394H

- 0003ECH

reserved

0003F0H BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003F4H BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003F8H BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

0003FCH BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

Bit Search Module

000400H

- 00043CH

reserved

000440H ICR00 [R/W] ---11111

ICR01 [R/W] ---11111

ICR02 [R/W] ---11111

ICR03 [R/W] ---11111

000444H ICR04 [R/W] ---11111

ICR05 [R/W] ---11111

ICR06 [R/W] ---11111

ICR07 [R/W] ---11111

000448H ICR08 [R/W] ---11111

ICR09 [R/W] ---11111 reserved ICR11 [R/W]

---11111

00044CH ICR12 [R/W] ---11111

ICR13 [R/W] ---11111 reserved reserved

Interrupt Control Unit



Register Address

+0 +1 +2 +3

Block

000450H ICR16 [R/W] ---11111 reserved reserved ICR19 [R/W]

---11111

000454H ICR20 [R/W] ---11111

ICR21 [R/W] ---11111

ICR22 [R/W] ---11111

ICR23 [R/W] ---11111

000458H reserved ICR25 [R/W] ---11111

ICR26 [R/W] ---11111

ICR27 [R/W] ---11111

00045CH reserved ICR29 [R/W] ---11111 reserved reserved

000460H reserved reserved reserved reserved

000464H reserved reserved ICR38 [R/W] ---11111

ICR39 [R/W] ---11111


ICR43 [R/W] ---11111

00046CH reserved reserved reserved reserved

000470H ICR48 [R/W] ---11111

ICR49 [R/W] ---11111

ICR50 [R/W] ---11111

ICR51 [R/W] ---11111

000474H reserved reserved reserved reserved


ICR59 [R/W] ---11111

00047CH reserved ICR61 [R/W] ---11111

ICR62 [R/W] ---11111

ICR63 [R/W] ---11111

000480H RSRR [R/W] 10000000

STCR [R/W] 00110011

TBCR [R/W] 00XXX – 00

CTBR [W] XXXXXXXX

000484H CLKR [R/W] ---- 0000

WPR [W] XXXXXXXX

DIVR0 [R/W] 00000011

DIVR1 [R/W] 00000000

Clock Control Unit



Register Address

+0 +1 +2 +3

Block

000488H reserved

00048CH PLLDIVM [R/W] - - - 00000

PLLDIVN [R/W] - - - 00000

PLLDIVG [R/W]- - - 00000

PLLDIVG [W] 00000000

000490H PLLCTRL [R/W] - - - - 0000 res. res. res.

PLL Clock Gear Unit

000494H

- 00049CH

reserved

0004A0H res. WTCER [R/W] - - - - - - 00

WTCR [R/W] 00000000 000 – 00 – 0

0004A4H res. WTBR [R/W] - - - XXXXX XXXXXXXX XXXXXXXX

0004A8H WTHR [R/W] - - - 00000

WTMR [R/W] - - 000000

WTSR [R/W] - - 000000 res.

Real Time Clock (Watch Timer)

0004ACH res. res. CSCFG [R/W] 0X000000

CMCFG [R/W] 00000000 Clock Monitor

0004B0H CUCR [R/W] - - - - - - - - - - - 0 - - 00

CUTD [R/W] 10000000 00000000

0004B4H CUTR1 [R] - - - - - - - - 00000000

CUTR2 [R] 00000000 00000000

Calibration Unit of Sub Oscillation

0004B8H CMPR [R/W] - - 000010 11111101 res. CMCR [R/W]

- 001 - - 00

0004BCH CMT1 [R/W] 00000000 1 - - - 0000

CMT2 [R/W] - - 000000 - - 000000

Clock Modulation

0004C0H CANPRE [R/W] 0 - - - 0000 res. res. res. CAN Clock

Control

0004C4H LVSEL [R/W] 00000111

LVDET [R/W] 0000 0 – 00 res. res. LV Detection

0004C8H OSCRH [R/W] 000 - - 001

OSCRL [R/W] - - - - - 000

WPCRH [R/W] 00 - - - 000

WPCRL [R/W] - - - - - - 00

Main-/Sub-Oscillation Stabilisation Timer

0004CCH OSCCR [R/W] - - - - - - - 0 res. res. res.

Main- Oscillation Standby Control



Register Address

+0 +1 +2 +3

Block

0004D4H SHDE [R/W] 0 - - - - - - - reserved EXTE [R/W]

00000000 EXTF [R/W] 00000000

0004D8H EXTLV [R/W] 00000000 00000000 reserved reserved

Shutdown control

0004DCH - 00063CH

reserved

000640H ASR0 [R/W] 00000000 00000000

ACR0 [R/W] 1111**00 001000001

000644H ASR1 [R/W] XXXXXXXX XXXXXXXX

ACR1 [R/W] XXXXXXXX XXXXXXXX



00064CH ASR3 [R/W] XXXXXXXX XXXXXXXX




000654H reserved reserved

000658H reserved reserved

00065CH reserved reserved

000660H AWR0 [R/W] 01001111 11111011

AWR1 [R/W] XXXXXXXX XXXXXXXX

000664H AWR2 [R/W] XXXXXXXX XXXXXXXX

AWR3 [R/W] XXXXXXXX XXXXXXXX

000668H AWR4 [R/W] XXXXXXXX XXXXXXXX reserved

00066CH reserved reserved

000670H MCRA [R/W] XXXXXXXX

MCRB [R/W] XXXXXXXX reserved

000674H reserved

000678H IOWR0 [R/W] XXXXXXXX

IOWR1 [R/W] XXXXXXXX

IOWR2 [R/W] XXXXXXXX res.

00067CH reserved

External Bus Unit

1 ACR0[11:10] depends on Modevector fetch information on buswidth



Register Address

+0 +1 +2 +3

Block

000680H CSER [R/W] 00000001

CHER [R/W] 11111111 res. TCR [R/W]

0000****2

000684H RCRH [R/W] 00XXXXXX

RCRL [R/W] XXXX0XXX reserved

000688H - 0007F8H

reserved

External Bus Unit

0007FCH res. MODR [W] XXXXXXXX res. res. Mode Register

000800H

- 000BFCH

reserved

000C00H reserved I-Unit

0000H

- 000CFCH

reserved

000D00H PDRD00 [R] XXXXXXXX

PDRD01 [R] XXXXXXXX res. res.

000D04H res. PDRD05 [R] XXXXXXXX

PDRD06 [R] XXXXXXXX

PDRD07 [R] XXXXXXXX

000D08H PDRD08 [R] XXXX - - XX

PDRD09 [R] - - - XXXXX

PDRD10 [R] - XXXXXXX

PDRD11 [R] - - - - - - XX

000D0CH res. PDRD13 [R] - - - - - XXX

PDRD14 [R] - - - - XXXX

PDRD15 [R] - - - - XXXX

000D10H PDRD16 [R] X - - - - - - -

PDRD17 [R] XXXXXXXX

PDRD18 [R] - - - - - XXX

PDRD19 [R] - XXX - XXX

000D14H PDRD20 [R] - XXX - XXX

PDRD21 [R] - XXX - XXX

PDRD22 [R] XXXXXX – X

PDRD23 [R] - X – XXXXX

000D18H PDRD24 [R] XXXXXXXX res. res. res.

000D1CH PDRD28 [R] XXXXXXXX

PDRD29 [R] XXXXXXXX res. res.

R-bus Port Data Direct Read Register

2 TCR[3:0] INIT value = 0000, keeps value after RST



Register Address

+0 +1 +2 +3

Block

000D20H

- 000D3CH

Reserved

000D40H DDR00 [R/W] 00000000

DDR01 [R/W] 00000000 res. res.

000D44H res. DDR05 [R/W] 00000000

DDR06 [R/W] 00000000

DDR07 [R/W] 00000000

000D48H DDR08 [R/W] 0000 - - 00

DDR09 [R/W] - - - 00000

DDR10 [R/W] - 0000000

DDR11 [R/W] - - - - - - 00

000D4CH res. DDR13 [R/W] - - - - - 000

DDR14 [R/W] - - - - 0000

DDR15 [R/W] - - - - 0000

000D50H DDR16 [R/W] 0 - - - - - - -

DDR17 [R/W] 00000000

DDR18 [R/W] - - - - - 000

DDR19 [R/W] - 000 - 000

000D54H DDR20 [R/W] - 000 - 000

DDR21 [R/W] - 000 - 000

DDR22 [R/W] 000000 - 0

DDR23 [R/W] - 0 - 00000

000D58H DDR24 [R/W] 00000000 res. res. res.

000D5CH DDR28 [R/W] 00000000

DDR29 [R/W] 00000000 res. res.

R-bus Port Direction Register

000D60H

- 000D7CH

Reserved

000D80H PFR00 [R/W] 11111111

PFR01 [R/W] 11111111 res. res.

000D84H res. PFR05 [R/W] 11111111

PFR06 [R/W] 11111111

PFR07 [R/W] 11111111

000D88H PFR08 [R/W] 1111 - - 11

PFR09 [R/W] - - - 11111

PFR10 [R/W] - 1111111

PFR11 [R/W] - - - - - - 00

000D8CH res. PFR13 [R/W] - - - - - 000

PFR14 [R/W] - - - - 0000

PFR15 [R/W] - - - - 0000

000D90H PFR16 [R/W] 0 - - - - - - -

PFR17 [R/W] 00000000

PFR18 [R/W] - - - - - 000

PFR19 [R/W] - 000 - 000

000D94H PFR20 [R/W] - 000 - 000

PFR21 [R/W] - 000 - 000

PFR22 [R/W] 000000 – 0

PFR23 [R/W] - 0 - 00000

000D98H PFR24 [R/W] 00000000 res. res. res.

000D9CH PFR28 [R/W] 00000000

PFR29 [R/W] 00000000 res. res.

R-bus Port Function Register



Register Address

+0 +1 +2 +3

Block

000DA0H

- 000DBCH

Reserved

000DC0H res. res. res. res.

000DC4H res. res. res. res.

000DC8H res. res. EPFR10 [R/W] - - 00 - - - 0 res.

000DCCH res. EPFR13 [R/W] - - - - - 0 - -

EPFR14 [R/W] - - - - 0000

EPFR15 [R/W] - - - - 0000

000DD0H EPFR16 [R/W] 0 - - - - - - - res. EPFR18 [R/W]

- - - - - 0 - - EPFR19 [R/W]

- 0 - - - 0 - -

000DD4H EPFR20 [R/W] - 0 - - - 0 - -

EPFR21 [R/W] - 0 - - - 0 - - res. res.

000DD8H res. res. res. res.

000DDCH res. res. res. res.

R-bus Port Extra Function Register

000DE0H

- 000DFCH

Reserved

000E00H PODR00 [R/W] 00000000

PODR01 [R/W] 00000000 res. res.

000E04H res. PODR05 [R/W] 00000000

PODR06 [R/W] 00000000

PODR07 [R/W] 00000000

000E08H PODR08 [R/W] 0000 - - 00

PODR09 [R/W] - - - 00000

PODR10 [R/W] - 0000000

PODR11 [R/W] - - - - - - 00

000E0CH res. PODR13 [R/W] - - - - - 000

PODR14 [R/W] - - - - 0000

PODR15 [R/W] - - - - 0000

000E10H PODR16 [R/W] 0 - - - - - - -

PODR17 [R/W] 00000000

PODR18 [R/W] - - - - - 000

PODR19 [R/W] - 000 - 000

000E14H PODR20 [R/W] - 000 - 000

PODR21 [R/W] - 000 - 000

PODR22 [R/W] 000000 - 0

PODR23 [R/W] - 0 - 00000

000E18H PODR24 [R/W] 00000000 res. res. res.

000E1CH PODR28 [R/W] 00000000

PODR29 [R/W] 00000000 res. res.

R-bus Port Output Drive Select Register



Register Address

+0 +1 +2 +3

Block

000E20H

- 000E3CH

reserved

000E40H PILR00 [R/W] 00000000

PILR01 [R/W] 00000000 res. res.

000E44H res. PILR05 [R/W] 00000000

PILR06 [R/W] 00000000

PILR07 [R/W] 00000000

000E48H PILR08 [R/W] 0000 - - 00

PILR09 [R/W] - - - 00000

PILR10 [R/W] - 0000000

PILR11 [R/W] - - - - - - 00

000E4CH res. PILR13 [R/W] - - - - - 000

PILR14 [R/W] - - - - 0000

PILR15 [R/W] - - - - 0000

000E50H PILR16 [R/W] 0 - - - - - - -

PILR17 [R/W] 00000000

PILR18 [R/W] - - - - - 000

PILR19 [R/W] - 000 - 000

000E54H PILR20 [R/W] - 000 - 000

PILR21 [R/W] - 000 - 000

PILR22 [R/W] 000000 - 0

PILR23 [R/W] - 0 - 00000

000E58H PILR24 [R/W] 00000000 res. res. res.

000E5CH PILR28 [R/W] 00000000

PILR29 [R/W] 00000000 res. res.

R-bus Port Input Level Select Register

000E60H - 000E7CH

reserved

000E80H res. res. res. res.



000E8CH res. res. EPILR14 [R/W] - - - - 0000

EPILR15 [R/W] - - - - 0000

000E90H res. EPILR17 [R/W] - - - - 0000

EPILR18 [R/W] - - - - - 000

EPILR19 [R/W] - 000 - 000

000E94H EPILR20 [R/W] - 000 - 000

EPILR21 [R/W] - 000 - 000

EPILR22 [R/W] - - - - 00 - 0

EPILR23 [R/W] - 0 - 00000

000E98H EPILR24 [R/W] 00 - - 0000 res. res. res.

000E9CH res. res. res. res.

R-bus Port Extra Input Level Select Register



Register Address

+0 +1 +2 +3

Block

000EA0H

- 000EBCH Reserved

000EC0H PPER00 [R/W] 00000000

PPER01 [R/W] 00000000 res. res.

000EC4H res. PPER05 [R/W] 00000000

PPER06 [R/W] 00000000

PPER07 [R/W] 00000000

000EC8H PPER08 [R/W] 0000 - - 00

PPER09 [R/W] - - - 00000

PPER10 [R/W] - 0000000

PPER11 [R/W] - - - - - - 00

000ECCH res. PPER13 [R/W] - - - - - 000

PPER14 [R/W] - - - - 0000

PPER15 [R/W] - - - - 0000

000ED0H PPER16 [R/W] 0 - - - - - - -

PPER17 [R/W] 00000000

PPER18 [R/W] - - - - - 000

PPER19 [R/W] - 000 - 000

000ED4H PPER20 [R/W] - 000 - 000

PPER21 [R/W] - 000 - 000

PPER22 [R/W] - - - - 00 - 0

PPER23 [R/W] - 0 - 00000

000ED8H PPER24 [R/W] 00 - - 0000 res. res. res.

000EDCH PPER28 [R/W] 00000000

PPER29 [R/W] 00000000 res. res.

R-bus Port Pull-Up/Down Enable Register

000EE0H - 000EFCH

Reserved

000F00H PPCR00 [R/W] 11111111

PPCR01 [R/W] 11111111 res. res.

000F04H res. PPCR05 [R/W] 11111111

PPCR06 [R/W] 11111111

PPCR07 [R/W] 11111111

000F08H PPCR08 [R/W] 1111 - -11

PPCR09 [R/W] - - - 11111

PPCR10 [R/W] - 1111111

PPCR11 [R/W] - - - - - -11

000F0CH res. PPCR13 [R/W] - - - - - 111

PPCR14 [R/W] - - - - 1111

PPCR15 [R/W] - - - - 1111

000F10H PPCR16 [R/W] 1 - - - - - - -

PPCR17 [R/W] 11111111

PPCR18 [R/W] - - - - - 111

PPCR19 [R/W] - 111 - 111

000F14H PPCR20 [R/W] - 111 - 111

PPCR21 [R/W] - 111 - 111

PPCR22 [R/W] 111111 - 1

PPCR23 [R/W] - 1 – 11111

000F18H PPCR24 [R/W] 11 - - 1111 res. res. res.

000F1CH PPCR28 [R/W] 11111111

PPCR29 [R/W] 11111111 res. res.

R-bus Port Pull-Up/Down Control Register



Register Address

+0 +1 +2 +3

Block

000F20H

- 000F3CH

reserved

001000H DMASA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

001004H DMADA0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX


00100CH DMADA1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX




00101CH DMADA3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX



DMAC

001028H - 001FFCH

reserved

002000H

- 005FFCH

MB91F467R Instruction RAM size is 8kB : 004000H – 005FFCH Instruction RAM 16 kB

006000H - 006FFCH

reserved

007000H FMCS [R/W] 01101000

FMCR [R] - - - 00000

FCHCR [R/W] - - - - - - 00 10000011

007004H FMWT [R/W] 11111111 11111111

FMWT2 [R] - 001 - - - -

FMPS [R/W] - - - - - 000

007008H FMAC [R] 00000000 00000000 00000000 00000000

Flash Memory/ Cache Control Register

00700CH FCHA0 [R/W] - - - - - - - - - - - 00000 00000000 00000000

I-Cache Non-cacheable area



Register Address

+0 +1 +2 +3

Block

007010H FCHA1 [R/W] - - - - - - - - - - - 00000 00000000 00000000

setting Register

007014H

- 00BFFCH

reserved

00C000H CTRLR0 [R/W] 00000000 00000001

STATR0 [R/W] 00000000 00000000

00C004H ERRCNT0 [R] 00000000 00000000

BTR0 [R/W] 00100011 00000001

00C008H INTR0 [R] 00000000 00000000

TESTR0 [R/W] 00000000 X0000000

00C00CH BRPE0 [R/W] 00000000 00000000 res.

CAN 0 Control Register

00C010H IF1CREQ0 [R/W] 00000000 00000001

IF1CMSK0 [R/W] 00000000 00000000

00C014H IF1MSK20 [R/W] 11111111 11111111

IF1MSK10 [R/W] 11111111 11111111

00C018H IF1ARB20 [R/W] 00000000 00000000

IF1ARB10 [R/W] 00000000 00000000

00C01CH IF1MCTR0 [R/W] 00000000 00000000 res.

00C020H IF1DTA10 [R/W] 00000000 00000000

IF1DTA20 [R/W] 00000000 00000000

00C024H IF1DTB10 [R/W] 00000000 00000000

IF1DTB20 [R/W] 00000000 00000000

00C028H - 00C02CH

Reserved

00C030H IF1DTA20 [R/W] 00000000 00000000

IF1DTA10 [R/W] 00000000 00000000

00C034H IF1DTB20 [R/W] 00000000 00000000

IF1DTB10 [R/W] 00000000 00000000

CAN 0 IF 1 Register



Register Address

+0 +1 +2 +3

Block

00C038H

- 00C03CH

reserved

00C040H IF2CREQ0 [R/W] 00000000 00000001

IF2CMSK0 [R/W] 00000000 00000000

00C044H IF2MSK20 [R/W] 11111111 11111111

IF2MSK10 [R/W] 11111111 11111111

00C048H IF2ARB20 [R/W] 00000000 00000000

IF2ARB10 [R/W] 00000000 00000000

00C04CH IF2MCTR0 [R/W] 00000000 00000000 res.

00C050H IF2DTA10 [R/W] 00000000 00000000

IF2DTA20 [R/W] 00000000 00000000

00C054H IF2DTB10 [R/W] 00000000 00000000

IF2DTB20 [R/W] 00000000 00000000

00C058H - 00C05CH

Reserved

00C060H IF2DTA20 [R/W] 00000000 00000000

IF2DTA10 [R/W] 00000000 00000000

00C064H IF2DTB20 [R/W] 00000000 00000000

IF2DTB10 [R/W] 00000000 00000000

00C068H - 00C07CH

Reserved

CAN 0 IF 2 Register

00C080H TREQR20 [R] 00000000 00000000

TREQR10 [R] 00000000 00000000

00C084H

- 00C08CH

reserved

00C090H NEWDT20 [R] 00000000 00000000

NEWDT10 [R] 00000000 00000000

00C094H - 00C09CH

reserved

00C0A0H INTPND20 [R] 00000000 00000000

INTPND10 [R] 00000000 00000000

00C0A4H - 00C0ACH

reserved

00C0B0H MSGVAL20 [R] 00000000 00000000

MSGVAL10 [R] 00000000 00000000

CAN 0 Status Flags



Register Address

+0 +1 +2 +3

Block

00C0B4H

- 00C0FCH

reserved

00C100H CTRLR1 [R/W] 00000000 00000001

STATR1 [R/W] 00000000 00000000

00C104H ERRCNT1 [R] 00000000 00000000

BTR1 [R/W] 00100011 00000001

00C108H INTR1 [R] 00000000 00000000

TESTR1 [R/W] 00000000 X0000000

00C10CH BRPE1 [R/W] 00000000 00000000 res.

CAN 1 Control Register

00C110H IF1CREQ1 [R/W] 00000000 00000001

IF1CMSK1 [R/W] 00000000 00000000

00C114H IF1MSK21 [R/W] 11111111 11111111

IF1MSK11 [R/W] 11111111 11111111

00C118H IF1ARB21 [R/W] 00000000 00000000

IF1ARB11 [R/W] 00000000 00000000

00C11CH IF1MCTR1 [R/W] 00000000 00000000 res.

00C120H IF1DTA11 [R/W] 00000000 00000000

IF1DTA21 [R/W] 00000000 00000000

00C124H IF1DTB11 [R/W] 00000000 00000000

IF1DTB21 [R/W] 00000000 00000000

00C128H

- 00C12CH

reserved

00C130H IF1DTA21 [R/W] 00000000 00000000

IF1DTA11 [R/W] 00000000 00000000

00C134H IF1DTB21 [R/W] 00000000 00000000

IF1DTB11 [R/W] 00000000 00000000

CAN 1 IF 1 Register



Register Address

+0 +1 +2 +3

Block

00C138H

- 00C13CH

reserved

00C140H IF2CREQ1 [R/W] 00000000 00000001

IF2CMSK1 [R/W] 00000000 00000000

00C144H IF2MSK21 [R/W] 11111111 11111111

IF2MSK11 [R/W] 11111111 11111111

00C148H IF2ARB21 [R/W] 00000000 00000000

IF2ARB11 [R/W] 00000000 00000000

00C14CH IF2MCTR1 [R/W] 00000000 00000000 res.

00C150H IF2DTA11 [R/W] 00000000 00000000

IF2DTA21 [R/W] 00000000 00000000

00C154H IF2DTB11 [R/W] 00000000 00000000

IF2DTB21 [R/W] 00000000 00000000

00C158H - 00C15CH

reserved

00C160H IF2DTA21 [R/W] 00000000 00000000

IF2DTA11 [R/W] 00000000 00000000

00C164H IF2DTB21 [R/W] 00000000 00000000

IF2DTB11 [R/W] 00000000 00000000

00C168H - 00C17CH

reserved

CAN 1 IF 2 Register

00C180H TREQR21 [R] 00000000 00000000

TREQR11 [R] 00000000 00000000

00C184H TREQR41 [R] 00000000 00000000

TREQR31 [R] 00000000 00000000

00C188H - 00C18CH

reserved

00C190H NEWDT21 [R] 00000000 00000000

NEWDT11 [R] 00000000 00000000

00C194H NEWDT41 [R] 00000000 00000000

NEWDT31 [R] 00000000 00000000

00C198H - 00C19CH

reserved

00C1A0H INTPND21 [R] 00000000 00000000

INTPND11 [R] 00000000 00000000

00C1A4H INTPND41 [R] 00000000 00000000

INTPND31 [R] 00000000 00000000

CAN 1 Status Flags



Register Address

+0 +1 +2 +3

Block

00C1A8H - 00C1ACH

reserved

00C1B0H MSGVAL21 [R] 00000000 00000000

MSGVAL11 [R] 00000000 00000000

00C1B4H MSGVAL41 [R] 00000000 00000000

MSGVAL31 [R] 00000000 00000000

00C1B8H - 00EFFCH

reserved

CAN 1

Status Flags

00F000H BCTRL [R/W]

- - - - - - - - - - - - - - - - 11111100 00000000

00F004H BSTAT [R/W] - - - - - - - - - - - - - 000 00000000 10 - - 0000

00F008H BIAC [R] - - - - - - - - - - - - - - - - 00000000 00000000

00F00CH BOAC [R] - - - - - - - - - - - - - - - - 00000000 00000000

00F010H BIRQ [R/W] - - - - - - - - - - - - - - - - 00000000 00000000

00F014H

- 00F01CH

reserved

00F020H BCR0 [R/W] - - - - - - - - 00000000 00000000 00000000

00F024H BCR1 [R/W] - - - - - - - - 00000000 00000000 00000000

00F028H BCR2 [R/W] - - - - - - - - 00000000 00000000 00000000

00F02CH BCR3 [R/W] - - - - - - - - 00000000 00000000 00000000

EDSU / MPU

00F030H - 00F07CH

reserved

00F080H BAD0 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX



EDSU / MPU



Register Address

+0 +1 +2 +3

Block

00F08CH BAD3 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX




00F09CH BAD7 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00F0A0H BAD8 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX



00F0ACH BAD11 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00F0B0H BAD12 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX



00F0BCH BAD15 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX

00F0C0H

- 027FFCH

reserved

024000H - 02BFFCH

MB91F467R-RAM size is 32kB : 024000H – 02BFFCH (data access is 1 waitcycles)

D-RAM 32 kB

02C000H - 02FFFCH

MB91F467R-RAM size is 16kB : 02C000H – 02FFFCH (data access is 0 waitcycles)

D-RAM 16 kB

030000H

- 033FFCH

MB91F467R I-/D-RAM size is 16kB : 030000H – 033FFCH

(instruction access is 0 waitcycles, data access is 1 waitcycle) I-/D-RAM 16 kB

034000H - 03FFFCH

reserved



Register Address

+0 +1 +2 +3

Block

040000H

- 05FFFCH

ROMS00 area (128kB)

060000H - 07FFFCH

ROMS01 area (128kB)

080000H - 09FFFCH

ROMS02 area (128kB)

0A0000H

- 0BFFFCH

ROMS03 area (128kB)

0C0000H - 0DFFFCH

ROMS04 area (128kB)

0E0000H

- 0FFFF4H

ROMS05 area (128kB)

0FFFF8H Mode Vector

0FFFFCH Reset Vector

Reset/Mode Vector

100000H - 13FFFCH

ROMS06 area (256kB)

140000H - 17FFFCH

ROMS07 area (256kB)

180000H - 4FFFFCH

reserved

Write operations to address 0FFFF8H and 0FFFFCH are not possible. When reading these addresses, the values shown above will be read.



4 Interrupt Vector Table This section shows the allocation of interrupt and interrupt vector/interrupt register.

Interrupt number Interrupt level*1 Interrupt vector*2

Interrupt

Decimal Hexa- decimal

Setting Register

Register address Offset Default Vector

address RN

Reset 0 00 - - 0x3FC 0x000FFFFC

Mode vector 1 01 - - 0x3F8 0x000FFFF8

System reserved 2 02 - - 0x3F4 0x000FFFF4

System reserved 3 03 - - 0x3F0 0x000FFFF0

System reserved 4 04 - - 0x3EC 0x000FFFEC

CPU supervisor mode (INT #5 instruction) *6 5 05 - - 0x3E8 0x000FFFE8

Memory Protection exception *6 6 06 - - 0x3E4 0x000FFFE4

Co-processor fault trap *5 7 07 - - 0x3E0 0x000FFFE0

Co-processor error trap *5 8 08 - - 0x3DC 0x000FFFDC

INTE instruction *5 9 09 - - 0x3D8 0x000FFFD8

Instruction break exception *5 10 0A - - 0x3D4 0x000FFFD4

Operand break trap *5 11 0B - - 0x3D0 0x000FFFD0

Step trace trap *5 12 0C - - 0x3CC 0x000FFFCC

NMI interrupt (tool)*5 13 0D - - 0x3C8 0x000FFFC8

Undefined instruction exception 14 0E - - 0x3C4 0x000FFFC4

NMI request 15 0F FH fixed 0x3C0 0x000FFFC0

External Interrupt 0 16 10 0x3BC 0x000FFFBC 0

External Interrupt 1 17 11

ICR00 0x440

0x3B8 0x000FFFB8 1



External Interrupt 2 18 12 0x3B4 0x000FFFB4 2


ICR01 0x441

0x3B0 0x000FFFB0 3

External Interrupt 4 20 14 0x3AC 0x000FFFAC


ICR02 0x442

0x3A8 0x000FFFA8

External Interrupt 6 22 16 0x3A4 0x000FFFA4


ICR03 0x443

0x3A0 0x000FFFA0

External Interrupt 8 24 18 0x39C 0x000FFF9C


ICR04 0x444

0x398 0x000FFF98

External Interrupt 10 26 1A 0x394 0x000FFF94

External Interrupt 11 27 1B

ICR05 0x445

0x390 0x000FFF90

External Interrupt 12 28 1C 0x38C 0x000FFF8C

External Interrupt 13 29 1D

ICR06 0x446

0x388 0x000FFF88

External Interrupt 14 30 1E 0x384 0x000FFF84

External Interrupt 15 31 1F

ICR07 0x447

0x380 0x000FFF80

Reload Timer 0 32 20 0x37C 0x000FFF7C 4

Reload Timer 1 33 21

ICR08 0x448

0x378 0x000FFF78 5

Reload Timer 2 34 22 0x374 0x000FFF74


ICR09 0x449

0x370 0x000FFF70

reserved 36 24 0x36C 0x000FFF6C

reserved 37 25

ICR10 0x44A

0x368 0x000FFF68

reserved 38 26 0x364 0x000FFF64


ICR11 0x44B

0x360 0x000FFF60

Free Run Timer 0 40 28 0x35C 0x000FFF5C

Free Run Timer 1 41 29

ICR12 0x44C

0x358 0x000FFF58



Free Run Timer 2 42 2A 0x354 0x000FFF54

Free Run Timer 3 43 2B

ICR13 0x44D

0x350 0x000FFF50

reserved 44 2C 0x34C 0x000FFF4C

reserved 45 2D

ICR14 0x44E

0x348 0x000FFF48

reserved 46 2E 0x344 0x000FFF44

reserved 47 2F

ICR15 0x44F

0x340 0x000FFF40

CAN 0 48 30 0x33C 0x000FFF3C

CAN 1 49 31

ICR16 0x450

0x338 0x000FFF38

reserved 50 32 0x334 0x000FFF34

CAN 3 51 33

ICR17 0x451

0x330 0x000FFF30

CAN 4 52 34 0x32C 0x000FFF2C

CAN 5 53 35

ICR18 0x452

0x328 0x000FFF28

USART (LIN) 0 RX 54 36 0x324 0x000FFF24 6

USART (LIN) 0 TX 55 37

ICR19 0x453

0x320 0x000FFF20 7

USART (LIN) 1 RX 56 38 0x31C 0x000FFF1C 8


ICR20 0x454

0x318 0x000FFF18 9

USART (LIN) 2 RX 58 3A 0x314 0x000FFF14

USART (LIN) 2 TX 59 3B

ICR21 0x455

0x310 0x000FFF10

USART (LIN) 3 RX 60 3C 0x30C 0x000FFF0C

USART (LIN) 3 TX 61 3D

ICR22 0x456

0x308 0x000FFF08

System reserved 62 3E 0x304 0x000FFF04

Delayed Interrupt 63 3F

ICR23 *4 0x457

0x300 0x000FFF00

System reserved *3 64 40 0x2FC 0x000FFEFC

System reserved *3 65 41

(ICR24) (0x458)

0x2F8 0x000FFEF8

reserved

reserved

reserved



USART (LIN, FIFO) 4 RX 66 42 0x2F4 0x000FFEF4 10

USART (LIN, FIFO) 4 TX 67 43

ICR25 0x459

0x2F0 0x000FFEF0 11

USART (LIN, FIFO) 5 RX 68 44 0x2EC 0x000FFEEC 12


ICR26 0x45A

0x2E8 0x000FFEE8 13

USART (LIN, FIFO) 6 RX 70 46 0x2E4 0x000FFEE4


ICR27 0x45B

0x2E0 0x000FFEE0

reserved 72 48 0x2DC 0x000FFEDC

reserved 73 49

ICR28 0x45C

0x2D8 0x000FFED8

I2C 0 / I2C 2 74 4A 0x2D4 0x000FFED4

I2C 1 75 4B

ICR29 0x45D

0x2D0 0x000FFED0

USART (LIN) 8 RX 76 4C 0x2CC 0x000FFECC

USART (LIN) 8 TX 77 4D

ICR30 0x45E

0x2C8 0x000FFEC8

USART (LIN) 9 RX 78 4E 0x2C4 0x000FFEC4

USART (LIN) 9 TX 79 4F

ICR31 0x45F

0x2C0 0x000FFEC0

USART (LIN) 10 RX 80 50 0x2BC 0x000FFEBC


ICR32 0x460

0x2B8 0x000FFEB8

USART (LIN) 11 RX 82 52 0x2B4 0x000FFEB4


ICR33 0x461

0x2B0 0x000FFEB0

USART (LIN) 12 RX 84 54 0x2AC 0x000FFEAC


ICR34 0x462

0x2A8 0x000FFEA8

USART (LIN) 13 RX 86 56 0x2A4 0x000FFEA4


ICR35 0x463

0x2A0 0x000FFEA0

USART (LIN) 14 RX 88 58 0x29C 0x000FFE9C


ICR36 0x464

0x298 0x000FFE98

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved

reserved



USART (LIN) 15 RX 90 5A 0x294 0x000FFE94

USART (LIN) 15 TX 91 5B

ICR37 0x465

0x290 0x000FFE90

Input Capture 0 92 5C 0x28C 0x000FFE8C

Input Capture 1 93 5D

ICR38 0x466

0x288 0x000FFE88

Input Capture 2 94 5E 0x284 0x000FFE84

Input Capture 3 95 5F

ICR39 0x467

0x280 0x000FFE80

reserved 96 60 0x27C 0x000FFE7C

reserved 97 61

ICR40 0x468

0x278 0x000FFE78

reserved 98 62 0x274 0x000FFE74

reserved 99 63

ICR41 0x469

0x270 0x000FFE70

Output Compare 0 100 64 0x26C 0x000FFE6C

Output Compare 1 101 65

ICR42 0x46A

0x268 0x000FFE68

Output Compare 2 102 66 0x264 0x000FFE64


ICR43 0x46B

0x260 0x000FFE60

Output Compare 4 104 68 0x25C 0x000FFE5C


ICR44 0x46C

0x258 0x000FFE58

Output Compare 6 106 6A 0x254 0x000FFE54

Output Compare 7 107 6B

ICR45 0x46D

0x250 0x000FFE50

reserved 108 6C 0x24C 0x000FFE4C

reserved 109 6D

ICR46 0x46E

0x248 0x000FFE48

reserved 110 6E 0x244 0x000FFE44

reserved 111 6F

ICR47 *4 0x46F

0x240 0x000FFE40

Prog. Pulse Gen. 0 112 70 0x23C 0x000FFE3C 15

Prog. Pulse Gen. 1 113 71

ICR48 0x470

0x238 0x000FFE38

reserved

reserved

reserved

reserved

reserved

reserved



Prog. Pulse Gen. 2 114 72 0x234 0x000FFE34


ICR49 0x471

0x230 0x000FFE30

Prog. Pulse Gen. 4 116 74 0x22C 0x000FFE2C


ICR50 0x472

0x228 0x000FFE28

Prog. Pulse Gen. 6 118 76 0x224 0x000FFE24


ICR51 0x473

0x220 0x000FFE20

reserved 120 78 0x21C 0x000FFE1C

reserved 121 79

ICR52 0x474

0x218 0x000FFE18

reserved 122 7A 0x214 0x000FFE14

reserved 123 7B

ICR53 0x475

0x210 0x000FFE10

reserved 124 7C 0x20C 0x000FFE0C

reserved 125 7D

ICR54 0x476

0x208 0x000FFE08

reserved 126 7E 0x204 0x000FFE04

reserved 127 7F

ICR55 0x477

0x200 0x000FFE00

reserved 128 80 0x1FC 0x000FFDFC

Up/Down Counter 1 129 81

ICR56 0x478

0x1F8 0x000FFDF8

reserved 130 82 0x1F4 0x000FFDF4

reserved 131 83

ICR57 0x479

0x1F0 0x000FFDF0

Real Time Clock 132 84 0x1EC 0x000FFDEC

Calibration Unit 133 85

ICR58 0x47A

0x1E8 0x000FFDE8

A/D Converter 0 134 86 0x1E4 0x000FFDE4 14

reserved 135 87

ICR59 0x47B

0x1E0 0x000FFDE0

reserved 136 88 0x1DC 0x000FFDDC

Alarm Comparator 1 137 89

ICR60 0x47C

0x1D8 0x000FFDD8

reserved

reserved



Low Voltage Detection 138 8A 0x1D4 0x000FFDD4

reserved 139 8B

ICR61 0x47D

0x1D0 0x000FFDD0

Timebase Overflow 140 8C 0x1CC 0x000FFDCC

PLL Clock Gear 141 8D

ICR62 0x47E

0x1C8 0x000FFDC8

DMA Controller 142 8E 0x1C4 0x000FFDC4

Main/Sub OSC stability wait 143 8F

ICR63 0x47F

0x1C0 0x000FFDC0

reserved 144 90 - - 0x1BC 0x000FFDBC

Used by the INT instruction.

145 to 255

91 to FF

- - 0x1B8 to 0x000

0x000FFDB8 to 0x000FFC00

Notes: *1 The ICRs are located in the interrupt controller and set the interrupt level for each interrupt request. An ICR is provided for each interrupt request. *2 The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the table base register value (TBR). The TBR specifies the top of the EIT vector table. The addresses listed in the table are for the default TBR value (0x000FFC00). The TBR is initialized to this value by a reset. *3 Used by REALOS *4 ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0x0C03 : IOS[0]) *5 System reserved *6 Memory Protection Unit (MPU) support



5 Package and Pin Assignment 5.1 Pin Assignment A LQFP176 package will be used for MB91F467R. The package code is FPT-176P-M07 (176-pin plastic LQFP, lead pitch: 0.50mm, 24.0 x 24.0 mm(body size))

*1: 3.3V/5V capable terminals are divided into 3 blocks. {(1),(2)and(3)} Each block can be used as a 3.3V terminals or 5V terminals. I2C terminals in (1) block is capable of 5V input only when 5V power is supplied to the VCC5 (#176 pin). The I2C terminals have an input theshold based on the 3.3V

*2: When an any blocks is used in 5V condition, block (3) must be supplied with 5V. This is because of that the INITX needs 5V level input.

PP

G2

PP

G1

PP

G0

ICU

3/TIN

3/TR

G3

ICU

2/TIN

2/TR

G2

ICU

1/TIN

1/TR

G1

ICU

0/TIN

0/TR

G0

INT13

INT12

INT11

INT10

OC

U3/TO

T3

OC

U2/TO

T2

OC

U1/TO

T1

OC

U0/TO

T0

SC

K6

SO

T6

SIN

6

SC

K5

SO

T5

SIN

5

SC

K4

SO

T4

SIN

4

SC

K3/F

RC

K3

SO

T3

SIN

3

SC

K2/F

RC

K2

SO

T2

SIN

2

SC

K1/F

RC

K1

SO

T1

SIN

1

SC

K0/F

RC

K0

SO

T0

SIN

0

/ / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /

VC

C5

P17_

3

P17_

2

P17_

1

P17_

0

P14_

3

P14_

2

P14_

1

P14_

0

P22_

3

P22_

2

P22_

0

P23_

6

P23_

4

VC

C5

VSS

P15_

3

P15_

2

P15_

1

P15_

0

P18_

2

P18_

1

P18_

0

P19_

6

P19_

5

P19_

4

P19_

2

P19_

1

P19_

0

VC

C5

VSS

P20_

6

P20_

5

P20_

4

P20_

2

P20_

1

P20_

0

P21_

6

P21_

5

P21_

4

P21_

2

P21_

1

P21_

0

VC

C5

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

VSS 1 132 VSS

INT2 /P24_2 2 131 INITXINT3 /P24_3 3 130 MD0

SDA1/INT15 /P22_6 4 129 MD1SCL1 /P22_7 5 128 MD2

SDA2/INT4 /P24_4 6 127 MD3SCL2/INT5 /P24_5 7 126 P23_3 / TX1

DREQ0 /P13_0 8 125 P23_2 / RX1/INT9DACK0X /P13_1 9 124 P23_1 / TX0DEOP0 /P13_2 10 123 P23_0 / RX0/INT8

VCC3 11 122 P24_7 / INT7VCC3 12 121 P24_6 / INT6

VSS 13 120 P24_1 / INT1C_1 14 119 P24_0 / INT0

CS4X /P09_4 15 118 P22_5 / SCL0CS3X /P09_3 16 117 P22_4 / SDA0/INT14CS2X /P09_2 17 116 AVRHCS1X /P09_1 18 115 AVCC3CS0X /P09_0 19 114 AVSS/AVRL

IORDX /P11_0 20 113 P28_7 / AN15IOWRX /P11_1 21 112 P28_6 / AN14

RDY /P08_7 22 111 P28_5 / AN13BRQ /P08_6 23 110 P28_4 / AN12

BGRNTX /P08_5 24 MB91F467RA pin assignment 109 P28_3 / AN11RDX /P08_4 25 (LQFP-176) 108 P28_2 / AN10

WR1X /P08_1 26 107 P28_1 / AN9WR0X /P08_0 27 106 P28_0 / AN8

NMIX 28 105 P29_7 / AN7MCLKE /P10_6 29 104 P29_6 / AN6MCLKI /P10_5 30 103 P29_5 / AN5

MCLKO /P10_4 31 102 P29_4 / AN4WEX /P10_3 32 101 P29_3 / AN3

BAAX /P10_2 33 100 P29_2 / AN2ASX /P10_1 34 99 P29_1 AN1

SYSCLK /P10_0 35 98 P29_0 / AN0VCC3 36 97 WDRESETX

C_2 37 96 P17_7 / PPG7VSS 38 95 P17_6 / PPG6

X0 39 94 P17_5 / PPG5X1 40 93 P17_4 / PPG4

VSS 41 92 P16_7 / ATGXX0A 42 91 P05_7 / A23X1A 43 90 P05_6 / A22

VCC3 44 89 VCC3

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

VSS

P01

_0

P01

_1

P01

_2

P01

_3

P01

_4

P01

_5

P01

_6

P01

_7

P00

_0

P00

_1

P00

_2

VC

C3

VSS

P00

_3

P00

_4

P00

_5

P00

_6

P00

_7

P07

_0

P07

_1

P07

_2

P07

_3

P07

_4

P07

_5

P07

_6

P07

_7

P06

_0

VC

C3

VSS

P06

_1

P06

_2

P06

_3

P06

_4

P06

_5

P06

_6

P06

_7

P05

_0

P05

_1

P05

_2

P05

_3

P05

_4

P05

_5

VSS

/ / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / /

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

A00

A01

A02

A03

A04

A05

A06

A07

A08

A09

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

(1) (2) (3)

(4)

(5)

(4)

(4)

(4)

(5)

I/O voltage level is 3.3V

I/O voltage level depends on the voltage applied to VCC5.



5.2 Package



5.3 I/O Pins and their functions PIN No. Pin Name PFR=1 (EPFR=0) EPFR=1 (PFR=1) 1 VSS 2 P24_2 INT2 - 3 P24_3 INT3 - 4 P22_6 SDA1/INT15 - 5 P22_7 SCL1 - 6 P24_4 SDA2/INT4 - 7 P24_5 SCL2/INT5 - 8 P13_0 DREQ0 - 9 P13_1 DACK0X - 10 P13_2 DEOP0 - 11 VCC3 12 VCC3 13 VSS 14 C_1 15 P09_4 CS4X - 16 P09_3 CS3X - 17 P09_2 CS2X - 18 P09_1 CS1X - 19 P09_0 CS0X - 20 P11_0 IORDX - 21 P11_1 IOWRX - 22 P08_7 RDY - 23 P08_6 BRQ - 24 P08_5 BGRNTX - 25 P08_4 RDX - 26 P08_1 WR1X - 27 P08_0 WR0X - 28 NMIX - - 29 P10_6 MCLKE - 30 P10_5 MCLKI - 31 P10_4 MCLKO - 32 P10_3 WEX - 33 P10_2 BAAX - 34 P10_1 ASX - 35 P10_0 SYSCLK - 36 VCC3 37 C_2 38 VSS 39 X0 - 40 X1 - 41 VSS 42 X0A 43 X1A 44 VCC3 45 VSS 46 P01_0 D16 - 47 P01_1 D17 - 48 P01_2 D18 - 49 P01_3 D19 - 50 P01_4 D20 - 51 P01_5 D21 - 52 P01_6 D22 - 53 P01_7 D23 -



PIN No. Pin Name PFR=1 (EPFR=0) EPFR=1 (PFR=1) 54 P00_0 D24 - 55 P00_1 D25 - 56 P00_2 D26 - 57 VCC3 58 VSS 59 P00_3 D27 - 60 P00_4 D28 - 61 P00_5 D29 - 62 P00_6 D30 - 63 P00_7 D31 - 64 P07_0 A00 - 65 P07_1 A01 - 66 P07_2 A02 - 67 P07_3 A03 - 68 P07_4 A04 - 69 P07_5 A05 - 70 P07_6 A06 - 71 P07_7 A07 - 72 P06_0 A08 - 73 VCC3 74 VSS 75 P06_1 A09 - 76 P06_2 A10 - 77 P06_3 A11 - 78 P06_4 A12 - 79 P06_5 A13 - 80 P06_6 A14 - 81 P06_7 A15 - 82 P05_0 A16 - 83 P05_1 A17 - 84 P05_2 A18 - 85 P05_3 A19 - 86 P05_4 A20 - 87 P05_5 A21 - 88 VSS 89 VCC3 90 P05_6 A22 - 91 P05_7 A23 - 92 P16_7 ATGX 93 P17_4 PPG4 - 94 P17_5 PPG5 - 95 P17_6 PPG6 - 96 P17_7 PPG7 - 97 WDRESETX 98 P29_0 AN0 - 99 P29_1 AN1 - 100 P29_2 AN2 - 101 P29_3 AN3 - 102 P29_4 AN4 - 103 P29_5 AN5 - 104 P29_6 AN6 - 105 P29_7 AN7 - 106 P28_0 AN8 - 107 P28_1 AN9 - 108 P28_2 AN10 -



PIN No. Pin Name PFR=1 (EPFR=0) EPFR=1 (PFR=1) 109 P28_3 AN11 - 110 P28_4 AN12 - 111 P28_5 AN13 - 112 P28_6 AN14 - 113 P28_7 AN15 - 114 AVSS/AVRL 115 AVCC3 116 AVRH 117 P22_4 SDA0/ INT14 - 118 P22_5 SCL0 - 119 P24_0 INT0 - 120 P24_1 INT1 - 121 P24_6 INT6 - 122 P24_7 INT7 - 123 P23_0 RX0/ INT8 - 124 P23_1 TX0 - 125 P23_2 RX1/ INT9 - 126 P23_3 TX1 - 127 MD3 128 MD2 129 MD1 130 MD0 131 INITX 132 VSS 133 VCC5 134 P21_0 SIN0 - 135 P21_1 SOT0 - 136 P21_2 SCK0 FRCK0 137 P21_4 SIN1 - 138 P21_5 SOT1 - 139 P21_6 SCK1 FRCK1 140 P20_0 SIN2 - 141 P20_1 SOT2 - 142 P20_2 SCK2 FRCK2 143 P20_4 SIN3 - 144 P20_5 SOT3 - 145 P20_6 SCK3 FRCK3 146 VSS 147 VCC5 146 P19_0 SIN4 - 149 P19_1 SOT4 - 150 P19_2 SCK4 - 151 P19_4 SIN5 - 152 P19_5 SOT5 - 153 P19_6 SCK5 - 154 P18_0 SIN6 - 155 P18_1 SOT6 - 156 P18_2 SCK6 - 157 P15_0 OCU0 TOT0 158 P15_1 OCU1 TOT1 159 P15_2 OCU2 TOT2 160 P15_3 OCU3 TOT3 161 VSS 162 VCC5 163 P23_4 INT10 -



PIN No. Pin Name PFR=1 (EPFR=0) EPFR=1 (PFR=1) 164 P23_6 INT11 - 165 P22_0 INT12 - 166 P22_2 INT13 - 167 P22_3 - - 168 P14_0 ICU0/TIN0/PPGTRG0 TIN0/PPGTRG0 169 P14_1 ICU1/TIN1/PPGTRG1 TIN1/PPGTRG1 170 P14_2 ICU2/TIN2/PPGTRG2 TIN2/PPGTRG2 171 P14_3 ICU3/TIN3/PPGTRG3 TIN3/PPGTRG3 172 P17_0 PPG0 - 173 P17_1 PPG1 - 174 P17_2 PPG2 - 175 P17_3 PPG3 - 176 VCC5



6 Boot procedure MB91F467R does not have a boot ROM. Therefore this device does nothing at reset initialization. (This is one of differences compared to the other 460 series devices)

MB91F467R simply takes mode vetor and reset vector from 0x000FFFF8 and 0x000FFFFC respectively. Fixed Mode-Reset vector feature is not available.

MB91F467R does not have Boot security vectors (BSV1, BSV2). These vectors are not checked during boot procedure.

7 Input threshold level settings MB91F467R has different input threshold setting from other MB91460 series devices.

PILR and EPILR register settings are defined as follows:

For terminals listed below P14_0,1,2,3 / P15_0,1,2,3 / P17_0,1,2,3 / P18_0,1,2 / P19_0,1,2,4,5,6 / P20_0,1,2,4,5,6 / P21_0,1,2,4,5,6 / P22_0,2,3 / P23_0,1,2,3,4,6 / P24_0,1,2,3,6,7

input threshold level

00[default] 01 10 11 EPILRxy PILRxy CMOS HYS1 CMOS HYS2 Automotive Inhibited

For terminals listed below P22_4,5,6,7 / P24_4,5

input threshold level

0[default] 1 - PILRxy CMOS CMOS HYS3

For all other terminals input threshold level

0[default] 1

- PILRxy CMOS CMOS HYS2

Each threshold level is defined as follows:

Threshold level VIL VIH CMOS 0.3 * VCC 0.7 * VCC

CMOS HYS1 0.3 * VCC 0.7 * VCC CMOS HYS2 0.2 * VCC 0.8 * VCC CMOS HYS3 0.3 * VCC 0.7 * VCC Automotive 0.5 * VCC 0.8 * VCC



8 Shutdown mode MB91F467R has a shutdown mode. In this mode, most of the power lines are cut except D-bus RAM (32kB 1wait) and related logics. This shutdown mode operation shows low leak current. In this mode most of the registers and RAMs lose its contents except D-bus RAM (32kB) and interrupt flags. During this mode, external bus signals keep its output state while other signals go into high impedance state. A certain external interrupts and INITX can be used for waking up from shutdown mode. NMI cannot be available for waking up.

8.1 Registers 8.1.1 SHDE : shut down enable

This bit is used to set the shut-down mode.

bit 7 6 5 4 3 2 1 0 SHDE - - - - - - -

INITX / wake 0 X X X X X X X RST / INIT retained X X X X X X X

attribute (R/W)

8.1.2 EXTE : External interrupt enable

These bits are used to wake up the system from the shut-down mode. When these bits are set, any external interrupt can’t be used as an interrupt signal.

bit 7 6 5 4 3 2 1 0 RX1 RX0 INT7 INT6 INT3 INT2 INT1 INT0

INITX / wake 0 0 0 0 0 0 0 0 RST / INIT retained retained Retained retained retained retained retained retained

attribute (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)

8.1.3 EXTF : External interrupt flag

When the device wakes up from the shut-down mode by external interrupt with EXTE valid, these bits are set to "1". And these bits are cleared by the external reset(INITX) or "0"-write only.

bit 7 6 5 4 3 2 1 0 RX1 RX0 INT7 INT6 INT3 INT2 INT1 INT0

INITX 0 0 0 0 0 0 0 0 RST / INIT / wake retained retained retained retained retained retained retained retained




8.1.4 EXTLV : External interrupt Level

These bits are used to set either high or low active input, and either edge or level input.

bit 15 14 13 12 11 10 9 8 LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4

INITX / wake 0 0 0 0 0 0 0 0 RST / INIT retained retained retained retained retained retained retained retained


bit 7 6 5 4 3 2 1 0 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

INITX / wake 0 0 0 0 0 0 0 0 RST / INIT retained retained retained retained retained retained retained retained


LBxLAx Activated Request Description

00 low level request (initial value)

01 high level request

10 high edge request

11 low edge request



9 Flash memory and security MB91F467R has a embedded Flash memory with a capacity of 1MB+64Kbytes. Its features are the same as the MB91F467D’s flash memory.

Flash security vectors and features are the same as the MB91F467D’s functions.

However the boot security vectors are not supported by the MB91F467R.



10 Flash serial programming support MB91F467R has a flash serial programming support function. This is called serial download function. Serial download function downloads the data to the internal RAM and can jump to the RAM to execute the instructions downloaded.

To use this fuction several port settings and mode terminal settings are needed.

P15_2 P15_3 Serial communication mode 0 0 Asynchronous serial download 0 1 Synchronous serial download

With P15 settings and MD3,2,1,0=={0,1,0,0} , after reset (INITX) MB91F467R can enter to the serial download function.

UART ch0 is used for this function and is set as follows:

Mode Clock source Parity Stop bit Data length Direction Asynchronous Internal None 1 8 bit LSB Synchronous external none None 8 bit LSB

The Baud rate generator is set as follows:

External xtal BGR0 value Baud rate Error 4.0000MHz BGR0=19FH 9615bps 0.156%(to 9600)



11 Electrical Characteristics

11.1 Absolute Maximum Ratings Parameter Symbol min. max. Unit Condition Digital supply voltage 1 VCC3-VSS -0.3 6.0 V Digital supply voltage 2 VCC5-VSS -0.3 6.0 V Storage temperature TST -55 125 °C Power consumption PTOT 1000 mW TA = 25°C

Digital input voltage VIDIG VSS-0.3* VSS-0.3*

VCC3+0.3 VCC5+0.3

V V

Analog input voltage VIA AVSS-0.3 AVCC3+0.3 V AVCC3=AVRH Analog supply voltage AVCC3-AVSS -0.3 4.0 V AVSS=0V Analog reference voltage

AVRH – AVSS -0.3 4.0 V AVSS=0V

Static DC current into digital I/O

II/ODC -2 2 mA Σ II/ODC < ISRUN

Relationship of the supply voltages

AVCC3 VSS - 0.3 VCC5 + 0.3 V

* Making full use of the allowed static DC current into digital I/Os will lead to lower values here.



11.2 Operating Conditions Parameter Symbol min. typ. max. Unit Condition

Operating temperature TOP -40

85 °C

Supply voltage - Digital supply - External bus supply - Analog supply

VCC5-VSS VCC3-VSS AVCC3-AVSS

3.0

3.0 3.0

5.5 3.6 3.6

V V V

Internal voltage reg. VCCCORE=1.8V AVSS=0V

Current consumption -run mode -RTC mode -stop mode

Isrun IsRTC Isstop

140 100 40 30

mA μA μA μA

f = 4MHz f = < 100kHz

ADC inputs 2)

- Reference voltage input - Input voltage range - Input resistance - Input capacitance - Impedance of external output driving the ADC input - Input leakage current

AVRH AVRL Vimax Vimin RI CI IIL

AVCC3*0.75AVSS AVRL -1

AVCC3 AVCC3*0.25 AVRH

10 17 100 1

V V V V kΩ pF kΩ μA

Top=25 deg. C

Digital outputs - Output “H” voltage - Output “L” voltage

VOH VOL

VCC5-0.5 VSS

VCC5 VSS+0.4

V V

Iload = 2/ 5mA Iload = - 2/-5mA

Digital Inputs 1)

CMOS Schmitt-Trigger - High voltage range - Low voltage range CMOS Automotive Schmitt-Trigger - High voltage range - Low voltage range - hysteresis voltage - Input capacitance - Input leakage current - Pull up resistor - Pull down resistor

VIH

VIL

VIH

VIL

CIN

IIL

Rup

Rdown

0.7*VCC5 VSS 0.8*VCC5 VSS 0.2 -1

50 50

VCC5 0.3*VCC5 VCC5 0.5*VCC5 0.5 tbd 1

V V V V V pF μA kΩ kΩ

Top=25 deg. C

PPG - Output voltage - Output current

VoutHIGH VoutLOW Iout

VCC5-0.5 VSS 5

VCC5 VSS+0.5

V V mA



I2C Bus Interface4) - Output voltage - Output current

VoutHIGH VoutLOW Iout

VSS 3

VCC5 VSS+0.5

V V mA

Open Drain Output IoutLOW= 3mA

Lock-up time PLL1 (4MHz->16…100MHz)

0.1 0.2 ms

RC Oscillator fRC100KHz fRC2MHz

50 1

100 2

200 4

kHz MHz

VCC >=1.65V

1) valid for bidirectional tristate I/O PAD cell

2) The protection diodes at the analog inputs are connected to the digital supply voltage 3) The longer alarm sense time can be selected for power safe modes in order to reduce the current consumption 4) I2C IO specification guaranteed only with VDD5 > 4.5V

11.3 Converter Characteristics • A/D Converter Parameter Symbol Rating Unit Remark

Minimum Typical Maximum Resolution 10 Bit Conversion error +/- 3.0 LSB Overall

error Non-linearity +/-2.5 LSB Differential Non-linearity

+/-1.9 LSB

Zero Reading voltage

V0T AVRL -1.5 AVRL+0.5 AVRL+2.5 LSB

Full scale reading voltage

VFST AVRH-3.5 AVRH-1.5 AVRH+0.5 LSB

Input current IA @ AVCC

2.4 4.7 mA

Reference voltage current

IR 0.65 1.0 mA

mb91f467r preliminary datasheet · • 5 chip select areas with individual area size, data bus...

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