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TS9

EMBER® EM35X NCP BREAKOUT BOARD TECHNICALSPECIFICATION

The Silicon Labs’ Ember EM35x Network Co-Processor (NCP) Breakout Board contains the hardware peripherals for the development and deployment of a low-data-rate, low-power ZigBee application on a host micro interfacing via EZSP protocol to the EM300 series NCPs. The NCP Breakout Board supports SPI and UART EZSP interfaces for development flexibility. Modules separately contain the EM35x NCP and the HOST microcontroller to allow for higher degrees of freedom during application development. The modules are connected to the NCP Breakout Board though robust connectors. The EM35x NCP Breakout Board hardware stimuli include a temperature sensor, two buttons, a piezo buzzer, two LEDs, and a 1.6" x 1.8" through-hole prototyping area. The EM35x NCP Breakout Board also contains a USB transceiver with USB connector, a RS-232 transceiver with DB-9 connector, Data Emulation Interface (DEI), Packet Trace Port programming interface, and regulated power planes. The EM35x NCP Breakout Board also includes an optional host interface to 2 Mbit external DataFlash in support of the ZigBee OTA upgrade cluster for over-the-air (OTA) application bootloader purposes. You can obtain the EM35x NCP Breakout Board voltage supply from one of four sources: Debug Adapter (ISA3) (through the Packet Trace Port), external VDC supply, USB port, or AAA battery pack. The various voltage supplies offer a degree of flexibility when testing different network topologies. This document provides the technical specification for the EM35x NCP Breakout Board. It describes the board-level interfaces as well as the key performance parameters. In addition, it provides the necessary information for developer to validate their application designs using the EM35x NCP Breakout Board. New in This Revision Document renumbering. Contents 1 EM35x NCP Breakout Board Features ............................................................................................................ 3

2 Components ................................................................................................................................................... 5

2.1 Power supply and distribution ................................................................................................................... 5

2.1.1 External DC Power Supply (J1 and J32 or J3.2 and J32) ................................................................... 7

2.1.2 Battery Connector (J8) ...................................................................................................................... 7

2.1.3 Packet Trace Port (J8) ...................................................................................................................... 7

2.1.4 USB Host (J5) ................................................................................................................................... 7

2.2 NCP Current Measurements .................................................................................................................... 7

2.3 Host Current Measurements..................................................................................................................... 7

2.4 Deep Sleep Testing of the EM35x Module ................................................................................................ 7

2.5 ZigBee Application Peripherals ................................................................................................................. 8

2.5.1 Temperature Sensor (U4) .................................................................................................................. 8

2.5.2 Buttons (EM1, EM2) .......................................................................................................................... 9

Rev 0.6 Copyright © 2013 by Silicon Laboratories TS9

http://www.silabs.com/

TS9 2.5.3 Buzzer (SPK1) .................................................................................................................................. 9

2.5.4 LEDs (DS6 and DS7) ........................................................................................................................ 9

2.5.5 External DataFlash (U7) .................................................................................................................... 9

2.6 EZSP and Serial Mode Configuration Switch (SW1) ................................................................................10

2.7 Data Emulation Interface (J43) ................................................................................................................15

2.8 EM35x Module Interface Connector (J21-J24) .........................................................................................15

2.9 Host Module interface connector (J37-J38)..............................................................................................18

2.10 Prototyping Area ..................................................................................................................................20

3 EM35x NCP Breakout Board Schematic .........................................................................................................21

2 Rev. 0.6

TS9 1 EM35x NCP Breakout Board Features The EM35x NCP Breakout Board offers:

• Configurable hardware support for application development Temperature sensor (connects to host GPIO) Two buttons (connect to host GPIO) Piezo buzzer (connect to host GPIO) Two LEDs (connect to host GPIO)

• RS-232 transceiver with DB-9 connector for serial communication (with hardware (HW) handshake support)

• USB transceiver with USB connector (Type B) • 2 MB external DataFlash for ZigBee OTA Profile support • Control Interface for the EM35x Radio Communications Module (RCM)

RCM RESET and Bootload buttons Voltage Supply connection (V_NCP_EN)

• Control Interface for the Host Module RCM RESET and Bootload buttons Voltage Supply connection (V_HOST_EN)

• 1.6" x 1.8", 0.1" pitch prototyping area • 26-pin, 0.1" pitch, dual-row logic-analyzer shrouded connector • 10-pin, 0.05" pitch, dual-row Packet Trace Port connector • 12-pin, 0.1” pitch, dual-row, data emulation interface (DEI) with configuration header • 14-pin, 0.05” pitch, single-row along with a 19-pin 0.05” pitch, single-row, board-to-board connector for the

module • 16-pin, 0.1” pitch, single-row along with a 20-pin 0.1” pitch, single-row, board-to-board connector for the

host module • Selection pins for DC power source selection (either external DC power supply, USB, Debug Adapter

(ISA3), or AAA battery pack). LEDs indicate which power supply has been selected. • 2-pin module VDC pin for connection of an ammeter for EM5x module current measurements • 2-pin module VDC pin for connection of an ammeter for host module current measurements • 2-pin jumpers for each of the HW application peripherals, buzzer, buttons, piezo, temperature sensor, and

LEDs • 2-pin jumpers for connection to TTL UART for either the EM35x UART (SC1) or host UART2. The

selection jumpers route signals (RXD, TXD, nRTS, and nCTS) allow access to the TTL levels.

Rev. 0.6 3

TS9 Table 1 lists the DC electrical characteristics of the EM35x NCP Breakout Board.

Table 1. DC Electrical Characteristics Parameter Min. Typ. Max. Unit VDD supply External DC Supply (J1 / J32) 4 20 V USB Host 4.5 5 V Debug Adapter 3.1 3.3V 3.5 V Battery 2.1 3.6 External DC supply (J3.2) 3.1 3.3 3.5 V Current draw (peripherals) Piezo buzzer 10 mA Buttons (enabled) 6 mA Temperature sensor (enabled) 5 mA Current draw (miscellaneous) RS-232 transceiver 4 mA USB transceiver 15 mA LDO distribution 10 mA Operating temperature 0 + 55 C

4 Rev. 0.6

TS9 2 Components Figure 1 illustrates the components on layer 1 (top side).

Figure 1. Assembly Print for Layer 1

2.1 Power Supply and Distribution The EM35x NCP Breakout Board can be powered from one of five sources:

• 4 V to 20 V External DC Power supply (Positive connected J1 and Ground connected to J32) • Battery pack connector (J8) • USB Host (J5, via Wall wart or PC connection) • Debug Adapter (ISA3) (through Packet Trace Port, J31) • 2.1 to 3.6 V External DC Power supply (Positive connected to J3.2 and Ground connected to J32)

EM35x Radio Module

Connectors (X1: J21-J22)

Packet Trace Port (J31)

Data Emulation Interface (J28)

Data Emulation Interface Selection

Header (J27)

NCP Bootloader (EM3) and Reset

(EM4) Buttons

Host Bootloader (EM6) and Reset

(EM5) Buttons

Prototype Area

DB-9 Connector – RS-232 (J30)

TTL Access Jumpers (J25-J28)

USB Connector (J5)

Power Source LEDs

Power Source Selection Jumpers ZigBee Application

Peripherals

DataFlash & Interface Connectors

Host Module Power Isolation Jumper (J34)

NCP Module Power Isolation Jumper (J34)

Reset and Bootload Enable Jumpers

(J14, J16, J35, J40)

SPI/UART Mode Config Switch (SW1)

Host Module Connectors

(X2: J37-J38)

Rev. 0.6 5

TS9 The EM35x NCP Breakout Board contains power source selection jumpers (J2 and J3) which allows only one DC source to power the board. This eliminates the possibility of overcurrent resulting from power supply contention. Table 2 illustrates the connection scheme and LED indication for each power source.

Table 2. Power Supply connections Power Source Selection Scheme (J2 and J3) LED Indicator

High Voltage External supply (4 V to 20 V) Connect VDD to J1 and GND to J32.

VPS

VBAT

VISA

VUSB

USB Host Connect USB cable to J5.

VPS

VBAT

VISA

VUSB

Debug Adapterr (ISA3) Connect Debug Adapter (ISA3) to J31.

VPS

VBAT

VISA

VUSB

Battery pack Connect AAA battery pack (supplied by Silicon Labs) to J8.

VPS

VBAT

VISA

VUSB

Low Voltage External DC supply (3.1 to 3.5) Connect directly to J3.2 with Ground connected to J32.

VPS

VBAT

VISA

VUSB

J3

VBATT

VREG

1

3J2

VISA

J3

VBATT

VREG

1

3J2

VISA

J3

VBATT

VREG

1

3J2

VISA

J3

VBATT

VREG

1

3J2

VISA

J3

VBATT

VREG

1

3J2

VISA

6 Rev. 0.6

TS9 2.1.1 External DC Power Supply (J1 and J32 or J3.2 and J32)

The EM35x NCP Breakout Board allows two easy to use connections to an external power supply.

• The first connection (Low Voltage) allows for a 3.1 to 3.5 V DC external supply to be connected to J3.2 (positive) and J32 (Ground). The power supply should be able to source up to 250 mA at the set voltage. When using a power supply in this mode, there should be no jumpers on J2 or J3 as shown in Table 2.

• The second connection (High Voltage) allows for a 4 V to 20 V DC external supply to be connected to J1 (positive) and J32 (Ground). The power supply should be able to source up to 300 mA at the set voltage. When using a power supply in this mode, there should be a jumper connecting J3.3 and J3.2 as shown in Table 2.

2.1.2 Battery Connector (J8) The 2-pin, keyed battery connector (Hirose, P/N: DF13-2P-1.25H(50)) allows for connection to a DC power supply or battery pack. The EM35x NCP Breakout Board is shipped with a 2-AAA battery pack with appropriate mating connector for easy attachment. Batteries are sold separately. When using a battery pack, a jumper must be connected between J3.1 and J3.2 as shown in Table 2.

2.1.3 Packet Trace Port (J8) The EM35x NCP Breakout Board can also be powered from a Debug Adapter (ISA3). To enable this power supply, simply connect the Debug Adapter (ISA3) to the Packet Trace Port (J8) and connect the power selection jumper between J2 and J3.2 as shown in Table 2. In addition, the Debug Adapter (ISA3) selection toggle switch must be put in the INT. The Debug Adapter (ISA3) provides a target voltage of 3.3V and sources as much as 250 mA. See document TS7, Debug Adapter (ISA3) Technical Specification, for more details on the Debug Adapter (ISA3).

Note: If the Debug Adapter (ISA3) is connected directly to the Packet Trace Port on the Module, the jumpers at J4 and J34 must be connected as well as the jumper across J2 and J3.2.

2.1.4 USB Host (J5) The EM35x NCP Breakout Board can also be powered by a USB Host (PC or Silicon Labs-supplied USB power supply). To operate in this mode, a USB Host must be connected to J5 and the power selection jumper must be connected between J3.1 and J3.2 as shown in Table 2.

2.2 NCP Current Measurements To allow for NCP current measurements, the EM35x NCP Breakout Board isolates the NCP module VDD power supply from the regulated power domain on the Breakout Board. The only connection point between the NCP module power supply and the Breakout Board supply is through the V_NCP_EN header (J4). Remove J4 and place an ammeter across this jumper to measure the NCP current draw.

2.3 Host Current Measurements To allow for Host current measurements, the EM35x NCP Breakout Board isolates the Host module VDD power supply from the regulated power domain on the Breakout Board. The only connection point between the Host module power supply and the Breakout Board supply is through the V_HOST_EN header (J34). Remove J34 and place an ammeter across this jumper to measure the Host current draw.

2.4 Deep Sleep Testing of the EM35x Module To perform accurate deep sleep measurements of the EM35x NCP, configure the EM35x NCP Breakout Board as follows:

• Remove J4 and place ammeter across this jumper.

Rev. 0.6 7

TS9 • Remove J6 so the V_NCP LED DS4 is not driven. If supplying voltage through J8 battery connector, also

remove J7 so the V_BATT LED DS5 is not driven. • Remove J33 jumpers to isolate DataFlash IC from circuit. • Issue "shutdown" in nodetest. • Once command is issued and node is asleep, remove J25-J28 (TTL jumpers). • Make sure the Packet Trace Port cable, DEI cable, and RS-232 cable are all detached from the Breakout

Board. This connection scheme offers the highest degree of power supply flexibility. Wake the EM35x NCP from deep sleep by pressing the NCP reset button.

Note: The use of virtual UART port 4900 is not recommended when interfacing to nodetest for deep sleep testing, since this does not allow for proper configuration of the EM35x for deep sleep measurements. Therefore, please use either pass-through UART port 4901, USB, or RS-232 to interface to the nodetest application.

2.5 ZigBee Application Peripherals As previously mentioned, the EM35x NCP Breakout Board offers six host peripherals to assist in ZigBee application development including:

• Temperature sensor • Two (2) “normally open” buttons • 4 kHz piezo buzzer • Two (2) LEDs • External DataFlash

Each peripheral connects to a host GPIO through a two-pin peripheral header. Because each peripheral header on the EM35x NCP Breakout Board ships with a jumper in place, the peripherals default to “HW Enabled.” If application development does not require the peripheral, simply remove the jumper.

Note: Each peripheral consumes power. Be sure to factor this into the current consumption equations when testing the module in deep sleep mode or if using the battery pack to power the Breakout Board.

2.5.1 Temperature Sensor (U4) The temperature sensor is an off-the-shelf component from National Semiconductor (MFG P/N: LM20BIM7). The temperature sensor requires an enable signal to be asserted (active high) prior to generating an analog voltage proportional to the ambient temperature of the EM35x NCP Breakout Board. Therefore, two host GPIO signals, HGPIO7 and HGPIO8, are routed to pin 2 of peripheral headers J13 and J15, respectively.

• HGPIO7 enables the temperature sensor when asserted (active high), when a jumper is installed at J13. • HGPIO8 contains the analog temperature information from the sensor, when it is enabled and a jumper is

installed at J15. The temperature sensor output is scaled to between 0 and 1.2 V through a resistive voltage divider. If you want to connect a temperature sensor from a different manufacturer, scale the output in a similar manner. The EM35x NCP Breakout Board is shipped with a jumper installed at J13 and J15. If the jumpers are removed, a different compatible device can be attached to pin 2 of both J13 and J15. For more information on the temperature sensor, refer to its data sheet (http://www.ti.com/product/LM20).

8 Rev. 0.6

http://www.ti.com/product/LM20

TS9 2.5.2 Buttons (EM1, EM2)

Two programmable, normally-open buttons are provided for software debugging and application development. When either button is pressed, the connected net is driven low. A single-pole RC filter minimizes the effects of switching noise. These buttons map to the backchannel button commands as follows:

• EM2: controlled by the button 0 command • EM1: controlled by the button 1 command

For information about the button command, see document UG110, the EM35x Development Kit User Guide.

Two host GPIO signals, HGPIO3 and HGPIO2, are routed from the EM35x Module to pin 2 of peripheral headers J9 and J10, respectively. In the default configuration of the EM35x NCP Breakout Board, jumpers are positioned across J9 and J10 to enable buttons EM1 and EM2, respectively. If the jumpers are removed, different compatible devices can be attached to pin 2 of breakout headers J9 and J10 instead of the buttons.

2.5.3 Buzzer (SPK1) A programmable buzzer is provided for software debugging and application development. A host GPIO signal, HGPIO4, is routed to pin 2 of peripheral header J17. In the default configuration of the EM35x NCP Breakout Board, a jumper is positioned across J17 to enable use of the buzzer. The buzzer installed on the EM35x NCP Breakout Board is from CUI (MFG P/N: CEP-1160). For more information on the buzzer, refer to its datasheet (http://www.cui.com/Product/Resource/PDFRedirect/110/CEP-1160.pdf).

2.5.4 LEDs (DS6 and DS7) The EM35x NCP Breakout Board contains two LEDs for software debugging and application development. Each LED is buffered (non-inverting) to allow for connection to any host GPIO. Two host GPIOs, HGPIO0 and HGPIO1, are routed to pin 2 of headers J12 and J11 respectively. To turn on DS7 (RED) from the host module, install a jumper at J12, configure HGPIO0 as an output and drive it low. To turn on DS6 (GREEN), install a jumper at J11, configure HGPIO1 as an output and drive it low.

2.5.5 External DataFlash (U7) The external DataFlash is an off-the-shelf component from Atmel (MFG P/N: AT45DB021D-SSH-B). The DataFlash is used in cases where ZigBee OTA Profile application bootloader is required for the host. The DataFlash is connected to the host module through jumper block J33. The EM35x NCP Breakout Board is shipped with jumpers installed in a disconnected state at J33. If all six jumpers are installed properly at J33, the external DataFlash connects to the host for application bootloading. Figure 2 illustrates the J33 jumper configuration for the DataFlash interface.

12

J33

DF_3V

DF_nCS

DF_SCKDF_SO

DF_SI

3V

HGPIO12

HGPIO13HGPIO15

HGPIO14

DF_nSD HGPIO11

Figure 2. Jumper for DataFlash connections

For more information on the DataFlash, refer to its datasheet (http://www.atmel.com/Images/doc3638.pdf).

Rev. 0.6 9

http://www.cui.com/Product/Resource/PDFRedirect/110/CEP-1160.pdf

http://www.atmel.com/Images/doc3638.pdf

TS9 2.6 EZSP and Serial Mode Configuration Switch (SW1) To enhance the software development experience, the EM35x NCP Breakout Board allows for EZSP interfaces between the EM35x NCP and a host via both SPI and UART (either to the host module or an external host). A configuration switch (SW1) is used to set up EZSP mode and serial communication paths. Access to either the EM35x SC1 UART or host UART1 is available directly from the EM35x NCP Breakout Board or by telnetting into port 4901 of a Debug Adapter (ISA3) connected to an Ethernet network. On the EM35x NCP Breakout Board, it is available as RS-232, USB and TTL-compliant signal levels. To minimize current consumption and allow for the different configuration options, the EM35x NCP Breakout Board individually routes the TTL UART signals RXD, TXD nCTS, and nRTS to pin 2 of headers J25, J26, J27, and J28 respectively. To route the UART signals to the USB transceiver, move SW1 Serial to TTL and TTL Path to USB. To route the UART signals to the RS-232 transceiver, move SW1 Serial to TTL and TTL Path to 232. To access TTL signals, move SW1 Serial to TTL, remove the jumpers on J25, J26, J27 and J28 and connect to pin 2 of these jumpers. To route the UART signals to DEI, move SW1 Serial to DEI and place jumpers on the DEI jumper connector (J42) as summarized below and shown in Figure 3.

• TXD: J27.1 to J27.2 • RXD: J27.5 to J27.6 • nRTS: J27.7 to J27.8 • nCTS: J27.9 to J27.10

Each SW1 configuration is shown in Table 3. TTL Access Jumper configuration is shown in Table 4.

Table 3. EZSP and Serial Configuration Switch UART Path Selection Scheme (J22, J25, J24, and J26)

EZSP SPI Mode, Host UART2 to DEI Connect Debug Adapter (ISA3) DEI cable to J31.

RXD

1 2

TXDnCTSnRTS

J25

J26

J27

J28

EZSP MODE:UART HOST:

SERIAL:TTL PATH:

SPIMOD

DEIUSB

UARTEXTTTL232

SW1

10 Rev. 0.6

TS9 UART Path Selection Scheme (J22, J25, J24, and J26)

EZSP SPI Mode, Host UART2 to RS-232

RXD

1 2

TXDnCTSnRTS

J25

J26

J27

J28


SERIAL:TTL PATH:

SPIMOD

DEIUSB

UARTEXTTTL232

SW1

EZSP SPI Mode, Host UART2 to USB

RXD

1 2

TXDnCTSnRTS

J25

J26

J27

J28


SERIAL:TTL PATH:

SPIMOD

DEIUSB

UARTEXTTTL232

SW1

EZSP SPI Mode, Host UART2 to TTL

RXD

1 2

TXDnCTSnRTS

J25

J26

J27

J28


SERIAL:TTL PATH:

SPIMOD

DEIUSB

UARTEXTTTL232

SW1

Rev. 0.6 11


EZSP UART Mode to Host Module, Host UART2 to DEI Connect Debug Adapter (ISA3) DEI cable to J31.

RXD

1 2

TXDnCTSnRTS

J25

J26

J27

J28


SERIAL:TTL PATH:

SPIMOD

DEIUSB

UARTEXTTTL232

SW1

EZSP UART Mode to Host Module, Host UART2 to RS-232

RXD

1 2

TXDnCTSnRTS

J25

J26

J27

J28


SERIAL:TTL PATH:

SPIMOD

DEIUSB

UARTEXTTTL232

SW1

EZSP UART Mode to Host Module, Host UART2 to USB

RXD

1 2

TXDnCTSnRTS

J25

J26

J27

J28


SERIAL:TTL PATH:

SPIMOD

DEIUSB

UARTEXTTTL232

SW1

12 Rev. 0.6


EZSP UART Mode to Host Module, Host UART2 to TTL

RXD

1 2

TXDnCTSnRTS

J25

J26

J27

J28


SERIAL:TTL PATH:

SPIMOD

DEIUSB

UARTEXTTTL232

SW1

EZSP UART Mode to External Host, NCP UART to DEI Connect DEI cable to J31.

RXD

1 2

TXDnCTSnRTS

J25

J26

J27

J28


SERIAL:TTL PATH:

SPIMOD

DEIUSB

UARTEXTTTL232

SW1

EZSP UART Mode to External Host, NCP UART to RS-232

RXD

1 2

TXDnCTSnRTS

J25

J26

J27

J28


SERIAL:TTL PATH:

SPIMOD

DEIUSB

UARTEXTTTL232

SW1

Rev. 0.6 13


EZSP UART Mode to External Host, NCP UART to USB

RXD

1 2

TXDnCTSnRTS

J25

J26

J27

J28


SERIAL:TTL PATH:

SPIMOD

DEIUSB

UARTEXTTTL232

SW1

EZSP UART Mode to External Host, NCP UART to TTL

RXD

1 2

TXDnCTSnRTS

J25

J26

J27

J28


SERIAL:TTL PATH:

SPIMOD

DEIUSB

UARTEXTTTL232

SW1

Note: To connect to the UART through a Debug Adapter (ISA3), the Debug Adapter (ISA3) must be connected to an Ethernet connection. It can be accessed by issuing “Serial 1” within the Console view of the Ember Desktop or by telnetting to Port 4901.

14 Rev. 0.6

TS9

1

TXD

2

J42

HGPIO3

RXD

nRTSnCTS

HGPIO2

HOST_nRESET

SW_SPI_ENSW_UART_MOD_EN

HOST_BTL

Figure 3. Jumper Settings Required for EM35x SC1 UART Access by Debug Adapter (ISA3)

Table 4. TTL Access Jumpers Configuration Selection Scheme (J25, J26, J27, and J28)

UART via USB or Serial

RXD

1 2

TXDnCTSnRTS

J25

J26

J27

J28

UART via TTL Access

RXD

1 2

TXDnCTSnRTS

J25

J26

J27

J28

2.7 Data Emulation Interface (J43) The 12-pin, dual-row, data emulation interface contains 4 host GPIO signals, 4 host or EM35x NCP UART signals, and 2 DEI control pins, as well as voltage (VBRD) and ground (GND) connections. When connected to the Debug Adapter (ISA3), the connector provides additional debug features to software developers. One feature involves the port 4901 UART connection through Debug Adapter (ISA3). To enable the UART connection to either the host or the EM35x NCP UART signals, configure SW1 for DEI mode as shown in Table 3 and install four jumpers on J42 as shown in Figure 3 for nCTS, nRTS, RXD, and TXD. Another feature involves manipulation of BUTTON0 and BUTTON1 GPIO signals. To enable GPIO manipulation of BUTTON0 and BUTTON1, install jumpers on J42 at HGPIO2 and HGPIO3, respectively.

2.8 EM35x Module Interface Connector (J21-J24) Two single-row, 0.05” pitch, connectors make up the EM35x module interface to the EM35x NCP Breakout Board. In addition, two single-row, guide connectors assist with connecting the EM35x module to the EM35x NCP Breakout Board. The board-to-board connector scheme allows access to all EM35x GPIO as well as nRESET and the JCLK signals. The connector is illustrated in Figure 4, while the dimensions are shown in Figure 5.

Rev. 0.6 15

TS9

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

33

32

31

30

29

28

27

26

25

24

23

22

21

20

EM35x_PC5

EM35x_PC6

EM35x_PC7

EM35x_PA7

EM35x_PB3

EM35x_nRESET

EM35x_PB4

HOST_MOSI

HOST_MISO

HOST_SCK

HOST_nSS

GND

EM35x_PA4

EM35x_PA5

EM35x_PA6

EM35x_PB1

EM35x_PB2

GND

GND

GND

VDD_3V_EM35X

GND

EM35x_PB5

nWAKE

EM35x_PB7

EM35x_PC0

EM35x_PC1

nSIMRST

EM35x_PC4

EM35x_PC3

EM35x_PC2

EM35x_JCLK

GND

J21

J22

3534

3736

J23

J24

NC NC

NC NC

Figure 4. Board-to-Board Connector for the EM35x Module

Figure 5. Board-to-Board Connector Dimensions for the EM35x Module

Table 5 describes the pinout and signal names at J21-J24. The EM35x UART1 signals (PB1, PB2, PB3, PB4) are exposed on the EM35x NCP Breakout Board at the 26-pin, dual row, 0.1” pitch GPIO connector (J41) for application development.

16 Rev. 0.6

TS9

Note: Custom EM35x modules (not shipped with development kits) containing external DataFlash should NOT be connected to the EM35x NCP Breakout Board, as the EM35x SPI1 is used for the EZSP SPI interface.

For more information on the alternate functions of the GPIO connector, refer to document 120-035X-000, the EM351/7 Data Sheet.

Table 5. Pinout and Signal Names of the NCP Interface Connector Pin # Signal name Direction2 Connector Description

1 GND Power J21 Ground Connection 2 PC5 I/O J21 EM35x GPIO 3 PC6 I/O J21 EM35x GPIO 4 PC7 I/O J21 EM35x GPIO 5 PA7 I/O J21 EM35x GPIO 6 PB3 I/O J21 EM35x GPIO 7 nRESET I/O J21 Active low chip reset (internal pull-up on EM35x) 8 PB4 I/O J21 EM35x GPIO 9 PA0 I/O J21 EM35x GPIO

10 PA1 I/O J21 EM35x GPIO 11 PA2 I/O J21 EM35x GPIO 12 PA3 I/O J21 EM35x GPIO 13 GND Power J21 Ground connection 14 PA4 I/O J21 EM35x GPIO 15 PA5 I/O J21 EM35x GPIO 16 PA6 I/O J21 EM35x GPIO 17 PB1 I/O J21 EM35x GPIO 18 PB2 I/O J21 EM35x GPIO 19 GND Power J21 Ground connection 20 GND Power J22 Ground connection 21 JCLK Input J22 JTAG interface, serial clock 22 PC2 I/O J22 EM35x GPIO 23 PC3 I/O J22 EM35x GPIO 24 PC4 I/O J22 EM35x GPIO 25 PB0 I/O J22 EM35x GPIO 26 PC1 I/O J22 EM35x GPIO 27 PC0 I/O J22 EM35x GPIO 28 PB7 I/O J22 EM35x GPIO 29 PB6 I/O J22 EM35x GPIO 30 PB5 I/O J22 EM35x GPIO 31 GND Power J22 Ground connection 32 VDD Power J22 2.1 to 3.6V Module Power Domain 33 GND Power J22 Ground connection 34 NC N/A J23 Not connected; guide pin 35 NC N/A J23 Not connected; guide pin

Rev. 0.6 17

TS9 Pin # Signal name Direction2 Connector Description

36 NC N/A J24 Not connected; guide pin 37 NC N/A J24 Not connected; guide pin

2 with respect to the RCM

2.9 Host Module interface connector (J37-J38) Two single-row, 0.1” pitch, connectors make up the host module interface to the EM35x NCP Breakout Board. The board-to-board connector scheme allows access to 16 host GPIO. The connector is illustrated in Figure 6, while the dimensions are shown in Figure 7.

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

1

2

3

4

5

6

7

8

9

10

11

12

13

14

EZSP_UART2_nRTS

EZSP_UART2_nCTS

EZSP_UART2_RXD

EZSP_UART2_TXD

HGPIO7

HGPIO6

HGPIO5

HGPIO4

HGPIO15

HGPIO14

HGPIO13

HGPIO12

HGPIO3

HGPIO2

HOST_BTL

NCP_nRESET

nWAKE

N/C

VDD_3V_HOST

HGPIO10

HGPIO11

HGPIO0

HGPIO1

HOST_nRESET

HGPIO8

HGPIO9

SER_UART1_nCTS

SER_UART1_nRTS

SER_UART1_TXD

SER_UART1_RXD

HOST_nSS

HOST_SCK

HOST_MISO

J38

J37

15 HOST_MOSI

16 nHOST_INT

36GND

Figure 6. Board-to-Board Connector for the Host Module

18 Rev. 0.6

TS9

Figure 7. Board-to-Board Connector Dimensions for the Host Module

Table 6 describes the pinout and signal names at both J37 and J38. 16 host GPIOs are exposed on the EM35x NCP Breakout Board at the 26-pin, dual row, 0.1” pitch GPIO connector (J41) for application development. For more information on the alternate functions of the GPIO connector, refer to the data sheet for the host microprocessor included on the host module.

Table 6. Pinout and Signal Names of the Host Interface Connector Pin # Signal name Direction2 Connector Description

1 HGPIO10 I/O J37 Spare Host GPIO 2 HGPIO11 I/O J37 DataFlash Shutdown (DF_nSD) 3 HGPIO0 I/O J37 Application LED (LED0) 4 HGPIO1 I/O J37 Application LED (LED1) 5 HOST_nRESET I/O J37 Active low host reset

6 HGPIO8 I/O J37 Temperature Sensor ADC (TEMP_SENSOR)

7 HGPIO9 I/O J37 Spare Host GPIO 8 SER_UART1_nCTS I/O J37 Host UART1 Clear to Send 9 SER_UART1_nRTS I/O J37 Host UART1 Ready to Send 10 SER_UART1_TXD I/O J37 Host UART1 Transmit Data 11 SER_UART1_RXD I/O J37 Host UART1 Receive Data 12 HOST_nSS I/O J37 EZSP SPI Slave Select 13 HOST_SCK I/O J37 EZSP SPI Clock 14 HOST_MISO I/O J37 EZSP Master In-Slave Out 15 HOST_MOSI I/O J37 EZSP Master Out-Slave In 16 nHOST_INT I/O J37 EZSP Host Interrupt 17 VDD_3V_HOST Power J38 3.3V Connection 18 EZSP_UART2_nRTS I/O J38 EZSP UART Ready to Send 19 EZSP_UART2_nCTS I/O J38 EZSP UART Clear to Send

Rev. 0.6 19

TS9 Pin # Signal name Direction2 Connector Description

20 EZSP_UART2_RXD I/O J38 EZSP UART Receive Data 21 EZSP_UART2_TXD I/O J38 EZSP UART Transmit Data

22 HGPIO7 I/O J38 Temperature Sensor Enable (TEMP_ENABLE)

23 HGPIO6 I/O J38 Spare Host GPIO 24 HGPIO5 I/O J38 Spare Host GPIO 25 HGPIO4 I/O J38 Application Speaker (PIEZO) 26 HGPIO15 I/O J38 DataFlash SPI Serial Out (DF_SO) 27 HGPIO14 I/O J38 DataFlash SPI Serial In (DF_SI) 28 HGPIO13 I/O J38 DataFlash SPI Clock (DF_SCK) 29 HGPIO12 I/O J38 DataFlash SPI Chip Select (DF_nSS) 30 HGPIO3 I/O J38 Application Button (BUTTON1) 31 HGPIO2 I/O J38 Application Button (BUTTON0) 32 HOST_BTL I/O J38 Host Bootloader 33 NCP_nRESET I/O J38 Active low NCP reset 34 nWAKE I/O J38 EZSP SPI Wake 35 NC N/A J38 Not connected 36 GND Power J38 Ground connection

2 with respect to the host

2.10 Prototyping Area The 1.6" x 1.8" (0.1” pitch) prototyping area on the EM35x NCP Breakout Board offers software developers an extra degree of flexibility. As shown in Figure 4, it allows access to VBRD, GND, and 16 host GPIOs. Therefore, you can solder any sensor or input device to the prototyping area and connect it to the host GPIO for development and debugging. As shown in Figure 8, the leftmost column is connected to GND and the rightmost column to VBRD. The top row is connected to the host GPIOs. Included in the top row are additional GND and JCLK connections. The remainder of the array is available for application development.

20 Rev. 0.6

TS9

VB

RD

GN

D

HG

PIO

15H

GP

IO14

HG

PIO

13H

GP

IO12

HG

PIO

11H

GP

IO10

HG

PIO

0

HG

PIO

9H

GP

IO8

HG

PIO

7H

GP

IO6

HG

PIO

5H

GP

IO4

HG

PIO

3H

GP

IO2

HG

PIO

1

Figure 8. EM35x NCP Breakout Board prototyping area

3 EM35x NCP Breakout Board Schematic The EM35x NCP Breakout Board schematic is included at the end of this document.

Rev. 0.6 21

COVER SHEETEM35X NCP BREAKOUT BOARD

A0SCH0681

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The information in this document is subject to change without notice. The statements, configurations, technical data and recommendations in thisdocument are believed to be accurate and reliable, but are presented without express or implied warranty. The information in this document isthe proprietary and confidential property of Ember Corporation and is priviliged. No part of the drawing or information may be duplicated or otherwiseused without the express permission of Ember Corporation

PAGE

Silicon Labs, 25 Thomson Place, Boston, MA 02210 TEL: 617-951-0200, FAX: 617-951-0999www.silabs.com

19-09-2010_22:13

Sheet Details

EM35X NCP Breakout Board

2 POWER MANAGEMENT, MANUFACTURING

3 APPLICATIONS CIRCUITS, BREADBOARD

1 COVER SHEET

4 EM35X RCM CONNECTORS, USER INTERFACES

5 HOST MODULE CONNECTOR, INTERFACES

6 SPI/UART MUX/DEMUX CIRCUIT

7 SPI/UART BLOCK DIAGRAM

8 REVISION NOTES

A0

POWER MANAGEMENT, MANUFACTURINGEM35X NCP BREAKOUT BOARD

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19-09-2010_22:20

510R5

HEADER-2J29

12

BAT54CD1

2

1

3

L4P

DF13-2P-1.25H(50)J8

21

FID1

47PFC4

HEADER-1J2

1

NUP2301MW6T1GU2

1 3

25

Datasheet

D3

3

21

GSOT15C-GS08Datasheet

47PFC5

PCB1710-0681-000

C310uF

FID2

REDDS1

BAT54CD2

2NC

1

3

L4P

SHORTING

JUMPER

REDDS3

SHORTING

JUMPER

10NFC2

330NFC1

FID3

220NFC7

SHORTING

JUMPER

HEADER-2

J7

12

SHORTING

JUMPER

1.0KR3

SHORTING

JUMPER

BLM18PG600SN1DFB1

2.2KR2

SHORTING

JUMPER

HEADER-3J3

32

1

SHORTING

JUMPER

0_OhmR1LT1763CS8-3.3#PBF

U1

5

8

6

7

43

21

OUTSENSE

GND-1BYP

GND-3

GND-2

IN

NSHDN

Datasheet

SHORTING

JUMPER

GSOT12C-GS08D4

3

21NC

Datasheet

130-0681-000SN1

SHORTING

JUMPER

REDDS2

10NFC6

SHORTING

JUMPER

SHORTING

JUMPER

SHORTING

JUMPER

SHORTING

JUMPER

REDDS5

TEST_POINTJ1

1

SHORTING

JUMPER

510R6

SHORTING

JUMPER

GREENDS8

SHORTING

JUMPER

510

R4

HEADER-2

J6

12

SHORTING

JUMPER

TEST_POINTJ32

1

USB-B-RAJ5

4321

S2

S1SHIELD1

SHIELD2

VBUSD-D+

GND

SHORTING

JUMPER

HEADER-2J4

1 2

VIN_USB

VIN_BATT

VIN_USB

VIN_USB

VDD_3V

VDD_ISAVIN_USB

VDD_3VVIN_BATT VDD_ISAVDD_3V_EM35X

VDD_3V_BB

VDD_3V_EM35XVIN_BATT

VIN_PWR_SUPPLY

VIN_PWR_SUPPLY

VIN_PWR_SUPPLY

VIN_PWR_SUPPLY

VIN_BATT

SHORTING

JUMPER

SHORTING

JUMPER

SHORTING

JUMPER

SHORTING

JUMPER

SHORTING

JUMPER

SHORTING

JUMPER

SHORTING

JUMPER

SHORTING

JUMPER

VIN_USB

SHORTING

JUMPER

SHORTING

JUMPER

VDD_3V_HOST

GREENDS4

SHORTING

JUMPER

SHORTING

JUMPER

SHORTING

JUMPER

SHORTING

JUMPER

SHORTING

JUMPER

SHORTING

JUMPER

1uFC30

SHORTING

JUMPER

HEADER-2J34

1 2

J36

HEADER-2

12

VDD_3V_HOST

R39510

BYPASS

VOUT_SENSEVREGIN

BATTERY_IN

VBUS

USB_DP

USB_DM

The shorting jumper at J4 can be replaced with a

J27J28

J25J26

J2 and J3.2J4J6

J9J10J11J12J13

J15

J17J16

There are five possible power sources for the Breakout board.1. External 3V Supply (Connect directly to J3.2)

2. USB Bus Powered (Connect shorting jumper between J3 pins 2.3)3. Ember battery pack with 2 AAA (Connect shorting jumper between J3 pins 1.2)

4. Debug Adapter (Connect shorting jumper between J2 and J3.2)

2. External Regulated supply from 4V to 20V (Connect shorting jumper between J3 pins 2.3)

J14

Headers J2 and J3 allow the user to select the power source.USB / VIN_PWR_JACK Down Conversion

ESD Suppression (Power Supply)

USB CONNECTION (TYPE B) 5V

Kit Provide Battery Pack for 2 AAAs, voltage range 1.5V to 3.1V

20V MAX IN,3V/500mA OUT

Power Indicator LEDs

Breakout Board and Module Power Selector

X 35

FiducialsPCB Information

* Remove J6, J36 when performing a Deep Sleep Test

POWER SUPPLY, DC, 4V to 20V* Place J1 close to J31

J29 is placed close to J41

Test Equipment GND Connection

J42.1 and J42.2J42.3 and J42.4

Shorting Jumpers

Place shorting jumpers across the following connector pins;

J33.2J33.4J33.6J33.8J33.10

current meter to measure Host module current drawThe shorting jumper at J34 can be replaced with a

current meter to measure EM35x module current draw

J39.1

J34J35

J7

J36

J42.7 and J42.8J42.5 and J42.6

J42.11 and J42.12J42.9 and J42.10

J42.13 and J42.14

J40

a Deep Sleep Test with Battery* Remove J67 when performing

BATTERY INTERFACE

EM35x IC will not operate properly at voltages below 1.8V

J33.12

http://www.onsemi.com/pub_link/Collateral/NUP2301MW6T1-D.PDF

http://www.vishay.com/docs/85824/gsot03c.pdf

http://www.vishay.com/doc?85824

APPLICATIONS CIRCUITS, BREADBOARDEM35X NCP BREAKOUT BOARD

SCH0681

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J11HEADER-2

12

BAT54AWT-TPD5

2

1

3

X3

15x16_PIN_BREADBOARD_AREA

HEADER-2J16

12

HEADER-2J15

12

B3S-1000EM4

42

310_OhmR13

HEADER-2J17

12

100nFC10

100KR8

510

R11

SN74LVC2G07DBVRU3

25

6

43

1 IN1

IN2 OUT2

OUT1

VC

CG

ND

DatasheetSN74LVC2G07DBVR

100nFC9

LM20BIM7/NOPBU4

5

4 3

2

1NCNC

GND1

VOV+

GND2

DatasheetLM20BIM7/NOPB

1.0KR17

DNIJ20

16151413121110987654321

B3S-1000EM3

42

31

100KR7

CEP-1160SPK1

21 V+

V-

Datasheet

1.0KR9

HEADER-2J12

12

1.0KR12

1.0KR14

B3S-1000EM1

42

31

HEADER-2J10

12

DNIC13

100KR16

S-HEADER-26J41

262422

252321

2018161412

1917151311

108642

97531

HEADER-2J13

12

GREEN

DS6

100KR15

DNIJ19

16151413121110987654321

HEADER-2J14

12

HEADER-2J9

12

100nFC12

B3S-1000EM2

42

31

DNIJ18

16151413121110987654321

REDDS7

100nFC8

100nFC11

510R10

VDD_3V_BB

VDD_3V_BB

VDD_3V_BB

VDD_3V_BB

J40HEADER-2

12

R341.0K

J35HEADER-2

12

R311.0K

EM5B3S-1000

42

31

EM6B3S-1000

42

31

0_OhmR32

DNIR33

PIEZO

TEMP_ENABLE

LED0

LED1

BUTTON1 EM1

DS6LED_1

DS7LED_0

BUTTON0 EM2

EM3

TEMP_SENSOR

EM4

VO

TEMP_SENSE

EM35X_PB4EM35X_PB3EM35X_PB1 EM35X_PB2

EM35X_nRESET

EM35X_PA5

nSIMRST

HOST_nRESET

HOST_BTL

EM35X_nRESET_SRC

MUX_nRESET

HGPIO0

HGPIO0

HGPIO0

HGPIO1

HGPIO1

HGPIO1

HGPIO2

HGPIO2

HGPIO2

HGPIO3

HGPIO3HGPIO3

HGPIO4

HGPIO4HGPIO4

HGPIO5HGPIO5HGPIO6HGPIO6

HGPIO7

HGPIO7HGPIO7

HGPIO8

HGPIO8HGPIO8

HGPIO9

HGPIO9HGPIO10

HGPIO10

HGPIO11

HGPIO11

HGPIO12

HGPIO12

HGPIO13

HGPIO13

HGPIO14

HGPIO14

HGPIO15

HGPIO15

EM35X_nRESET_BUTTON

EM6

EM5

HOST_MOSI HOST_MISOHOST_SCK HOST_nSS

nWAKE

Buttons

Host Application LEDs

Host Temperature Sensor

Host Application Buttons

Host Piezo Speaker

Peripheral Scratch Pad (0.1" pitch)

EM35x RESET Button (Active Low)EM35x Reset Selection

EM35x Bootloader Button (Active Low)

26-Pin, Dual Row Test Connector

Host RESET Button (Active Low)

Host Bootloader Button (Active Low)

http://media.digikey.com/pdf/Data%20Sheets/Texas%20Instruments%20PDFs/sn74lvc2g07.pdf

http://www.national.com/ds/LM/LM20.pdf

http://www.cui.com/pdffiles/CEP-1160.pdf

VALUE

U5

33 262017424

911102122

3

7

6

31

8

32

2

30

16

282723

18

292513125

14

15

191 VCCIO

VCC

USBDM

USBDP

NC-6NC

NC-5NC

NC-1NC

NC-4NC

NC-3NC

RESET#

NC-2NC

OSC1NC

OSC2NC

3V3OUT

TXD

RXD

RTS#

CTS#

DTR#

DSR#

DCD#

RI#

CBUS0CBUS1CBUS2CBUS3CBUS4

AG

ND

GN

D-1

GN

D-3

GN

D-4

TE

ST

GN

D-2

DatasheetFT232RQ_R

EM35X RCM CONNECTORS, USER INTERFACES

A0EM35X NCP BREAKOUT BOARD

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19-09-2010_22:13

RCM_INTERFACEX1

37 363534

3332313029282726252423222120

19181716151413121110987654321

NCNC

NC

NC

DatasheetHEADER-19J21

DatasheetHEADER-14

J22

FT232RQ_RU5

35 38373634G

ND

-5

GN

D-7

GN

D-8

GN

D-9

GN

D-6

DNIJ23

DNIJ24

DNIR29 0_OhmR26

DNIR30

100nFC21

TP7

J25HEADER-2

12

TP8

100nFC19

C16100nF

100KR18

J26HEADER-2

12

FTSH-105-01-F-DV-KJ31

10987654321

Datasheet

C154.7UF

T491A475K020AT

TP4

100nFC22

J27HEADER-2

12

100KR19

TP3

TP2

J30

5

4NC

3

2

1NC

9NC

8

7

6NC1

2

3

4

5

6

7

8

9

RECEPTACLE_DB9

10NFC18

TP1

100nFC20

100nFC14

TP5

C17100nF

J28HEADER-2

12

TP6

Datasheet

LTC1386CS#PBFU6

6

2

147

13815

912

10

5

11

4

31

16V

CCC1+

C1-

C2+

TR1_IN

C2-

TR2_IN

RX1_OUTRX2_OUT

GNDRX2_INRX1_IN

TR2_OUTTR1_OUT

V+

V-

VDD_3V_BB

VDD_3V_BBVDD_3V_BB

VIN_USB VCC30

VCC30

VCC30VIN_USB

VDD_3V_EM35X

R36DNI

TP9

R37DNI

DNIDS10

DNIDS11

VDD_3V_BB

SW1

765

8

321

4

DatasheetADE0404

R2310K

R2410K

R2510K

R2210K

VDD_3V_BB

0_OhmR27

J44

87654321 1

2345678

DNI

USB_DP

DB9_TXDDB9_nRTS

DB9_RXDDB9_nCTS

CBUS0

CBUS0

RS232_nCTS

RS232_nRTS

FTDI_NRTS

RS232_TXD

CBUS3

CBUS3

CBUS4

CBUS4

NDSR

NDSR

CBUS1

CBUS1NRI

NRI

CBUS2

CBUS2

NDCD

NDCD

EM35X_PB4

EM35X_PB3

EM35X_PB1EM35X_PB2

EM35X_nRESET

EM35X_nRESET

EM35X_PA4

EM35X_PA4

EM35X_PA5

EM35X_PA5

EM35X_PB5

EM35X_PB5

EM35X_PB7

EM35X_PB7

EM35X_PC0

EM35X_PC0

EM35X_PC1

EM35X_PC1nSIMRST

EM35X_PC4

EM35X_PC4

EM35X_PC3

EM35X_PC3

EM35X_PC2

EM35X_PC2

EM35X_JCLK

EM35X_JCLK

NDTR

NDTR

TTL_RXD

TTL_TXD

TTL_nCTS

SERIAL_TXD

SERIAL_RXD

SERIAL_nCTS

SERIAL_nRTSTTL_nRTS

SW_UART_MOD_ENSW_SPI_EN HW_SPI_EN

HW_UART_MOD_EN

USB_EN

SPI_EN

DEI_EN

FTDI_RXD

FTDI_TXD

RS232_RXD

FTDI_NCTS

EM35X_PA6

EM35X_PA6

EM35X_PA7

EM35X_PA7

EM35X_PC5

EM35X_PC5

EM35X_PC6

EM35X_PC6

EM35X_PC7

EM35X_PC7

UART_MOD_EN

HOST_MOSIHOST_MISOHOST_SCKHOST_nSS

nWAKE

USB_DM

EM3XX RCM Interface Header

5 via grid for U5 PCB Footprint

Configuration Mode Enable Switches

Software/Hardware Enable

FROM DEI/TTL MUX <--- ---> TO USB/232 MUX

(Target Power)(JTDO/SWO)(nJRST)(JTDI)

(JTCK/SWCLK)(JTMS/SWDIO)(nRESET)(Packet Trace Frame)(Packet Trace Data)

EM35x Packet Trace Port TTL to RS-232 Transceiver

USB / UART IC FTDi GPIO Test PointsUSB IC Decoupling

TTL Signal Access

Access to unused EM35x GPIO

EM35x GPIO Header

http://www.ftdichip.com/Documents/DataSheets/DS_FT232R.pdf

http://www.newark.com/pdfs/datasheets/spc/11N6304.pdf

http://www.newark.com/pdfs/datasheets/spc/11N6304.pdf

http://www.samtec.com/documents/webfiles/pdf/FTSH_SMT.PDF

http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1007,C1016,P1044,D1590

http://www.tycoelectronics.com/industry/appliance/pdf/catalogs/1308390_Sec_A_Dip_Switches.pdf

X2

3635 NC

343332313029282726252423222120191817

16151413121110987654321

HOST_INTERFACE

DatasheetSOCKET-16J37 Datasheet

SOCKET-20J38

NDS355NQ1

1

2

3

R28100K

R35DNI

J33

11 12108642

97531

Header-12

VDD_3V_HOST

0_Ohm

R20

U7

87654

321

SISCKnRESETnCS nWP

VCCGND

SO

DatasheetAT45DB021D-SSH-B

VDD_3V_DF

0_Ohm

R21

VDD_3V_BBJ43S-HEADER-12

1211108642

97531

J42

2018161412108642

191715131197531

Header-20

VDD_3V_DF

10NFC23

VDD_3V_HOST VDD_3V_DF

VDD_3V_DF

HOST MODULE CONNECTORS, INTERFACESEM35X NCP BREAKOUT BOARD

A0

5 8

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DEI_nCTS_JMPDEI_nRTS_JMPDEI_RXD_JMP

DEI_TXD_JMP

SW_UART_MOD_ENSW_SPI_EN

HOST_nRESET

HOST_nRESET

DEI_HOST_BTL

DEI_HOST_BTL

DEI_SW_UART_MOD_EN

DEI_SW_UART_MOD_EN

DEI_SW_SPI_EN

DEI_SW_SPI_EN

DEI_HOST_nRESET

DEI_HOST_nRESET

DEI_BUTTON0

DEI_BUTTON0

DEI_nCTS

DEI_nCTS

DEI_nRTS

DEI_nRTS

DEI_RXD

DEI_RXD

DEI_BUTTON1

DEI_BUTTON1

DEI_TXD

DEI_TXD

DF_nCS

DF_nCS

DF_SCKDF_SCKDF_SO

DF_SO

DF_SI

DF_SI

DF_nWP

DF_nRESET

HOST_BTL

HOST_BTL

HGPIO0HGPIO1

HGPIO2

HGPIO2

HGPIO3

HGPIO3

HGPIO4HGPIO5HGPIO6HGPIO7

HGPIO8HGPIO9

HGPIO10

HGPIO11

HGPIO11

HGPIO12

HGPIO12

HGPIO13

HGPIO13

HGPIO14

HGPIO14

HGPIO15

HGPIO15

EZSP_UART2_RXDEZSP_UART2_nCTSEZSP_UART2_nRTS

nHOST_INTNCP_nRESETHOST_MOSI

HOST_MISOHOST_SCKHOST_nSS

nWAKE

EZSP_UART2_TXD

SER_UART1_RXDSER_UART1_TXD

SER_UART1_nCTSSER_UART1_nRTS

NDS355N

DF_nSD

DF_nSD

DataFlash (SPI Interface with Host)

Radio Modules which are expected to operate at voltages below 2.7V will require a DC to DC up-converter supply source for the AT45DB021DVoltage range of the AT45DB021D is 2.7V to 3.6V

Input data on SI is always latched on the rising edge of SCKOutput data on SO is always clocked out on the falling edge of SCK

Host DEI

Should be placed near J43

Host Module Interface Headers

Host DEI Jumpers

Host Module Application Peripheral GPIO Mapping

HOST NET NAME GPIO FUNCTION

Application LED (LED0)HGPIO0

HGPIO1 Application LED (LED1)

Application Button (BUTTON0)HGPIO2

HGPIO3 Application Button (BUTTON1)

Application Speaker (PIEZO)HGPIO4

HGPIO5 Spare GPIO

Spare GPIOHGPIO6

HGPIO7 Temperature Sensor Enable (TEMP_ENABLE)

Temperature Sensor ADC (TEMP_SENSOR)HGPIO8

HGPIO9 Spare GPIO

Spare GPIOHGPIO10

HGPIO11 DataFlash Shutdown (DF_nSD)

DataFlash SPI Chip Select (DF_nCS)HGPIO12

HGPIO13 DataFlash SPI Clock (DF_SCK)

DataFlash SPI Serial In (DF_SI)HGPIO14

HGPIO15 DataFlash SPI Serial Out (DF_SO)

J37p35 - NC, available for later use

http://www.mill-max.com/images/products/pdf/081N.PDF

http://www.mill-max.com/images/products/pdf/081N.PDF

http://www.atmel.com/dyn/resources/prod_documents/doc3638.pdf

J39

1HEADER-2

2

C24100nF

C25100nF

C27100nF

C26100nF

SPI/UART MUX/DEMUX CIRCUITEM35X NCP BREAKOUT BOARD

A0

6 8

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4 3 2 1

TITLE

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DWG

A

B B

A

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U8

4

15

816

14

76 9

1011

35

12

1312

X0X1

Y0Y1

Z0Z1

ABCnEN

VEE

X VC

CG

ND

Y

Z

DatasheetCD74HC4053M

U11

4

15

816

14

76 9

1011

35

12

1312

X0X1

Y0Y1

Z0Z1

ABCnEN

VEE

X VC

CG

ND

Y

Z


U9

4

15

816

14

76 9

1011

35

12

1312

X0X1

Y0Y1

Z0Z1

ABCnEN

VEE

X VC

CG

ND

Y

Z


U10

4

15

816

14

76 9

1011

35

12

1312

X0X1

Y0Y1

Z0Z1

ABCnEN

VEE

X VC

CG

ND

Y

Z


U12

4

15

816

14

76 9

1011

35

12

1312

X0X1

Y0Y1

Z0Z1

ABCnEN

VEE

X VC

CG

ND

Y

Z


U13

4

15

816

14

76 9

1011

35

12

1312

X0X1

Y0Y1

Z0Z1

ABCnEN

VEE

X VC

CG

ND

Y

Z


VDD_3V_BB

VDD_3V_BB

VDD_3V_BB

VDD_3V_BB

VDD_3V_BB

VDD_3V_BB

U14

5

43

2

1 1A

1B

GND 1Y

VCC

Datasheet74LX1G32STR

VDD_3V_BB

C28100nF

C29100nF

RS232_nCTS

RS232_nRTS

FTDI_nRTS

RS232_TXD

EM35X_PB4EM35X_PB3EM35X_PB1

EM35X_PB2

NDTR

TTL_RXD

TTL_TXD

TTL_nCTS

SERIAL_TXD

SERIAL_RXD

SERIAL_nCTS SERIAL_nRTS

TTL_nRTS

DEI_nCTS_JMP DEI_nRTS_JMP

DEI_RXD_JMP

DEI_TXD_JMP

USB_ENUSB_EN

SPI_EN

SPI_EN

SPI_EN

DEI_ENDEI_ENDEI_EN

DEI_EN

EM35X_PB2_UART

AorB

AorB

AorBAorBAorB

FTDI_RXD

FTDI_TXD

TXD

RS232_RXD

nCTS nRTS

FTDI_nCTS

MUX_nRESET

EZSP_UART2_RXD EZSP_UART2_nCTSEZSP_UART2_nRTS

nHOST_INT

NCP_nRESETNDTR_MUX

UART_MOD_EN

RXD

EZSP_UART2_TXD

SER_UART1_RXD

SER_UART1_TXD SER_UART1_nCTS SER_UART1_nRTS

SPI/UART Multiplexer/Demultiplexer Circuit

SPI_EN (A) or UART_MOD_EN (B)

http://focus.ti.com/lit/ds/symlink/cd74hc4051.pdf






http://www.st.com/stonline/products/literature/ds/8490/74lx1g32.pdf

SPI/UART BLOCK DIAGRAMEM35X NCP BREAKOUT BOARD

A0

7 8

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4 3 2 1

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EM

35X

HO

ST

SP

IU

AR

T EM35X_PB1 (TXD)EM35X_PB2 (RXD)EM35X_PB3 (nCTS)EM35X_PB4 (nRTS)

UA

RT

SP

I

EM35X_PB0 (nSIMRST)EM35X_PA3 (nSSEL)

EM35X_PA1 (MISO)EM35X_PA0 (MOSI)

nWAKEnHOST_INT

EM35X_PB6 (nWAKE)EM35X_PB2 (nHOST_INT)

SPI_EN (A) ||

NCP_nRESET

nSS

MISOMOSI

EM35X_PA2 (SCLK)

SCK

EZSP_UART2_nCTSEZSP_UART2_nRTSEZSP_UART2_TXDEZSP_UART2_RXD

SER_UART1_nRTSSER_UART1_nCTSSER_UART1_RXDSER_UART1_TXD

SPI_EN (A) ||UART_MOD_EN (B)

nRTSnCTSRXDTXD

DEI_RXDDEI_nCTSDEI_nRTS

DEI_TXD

TTL_nRTSTTL_nCTSTTL_RXDTTL_TXD

SERIAL_nRTSSERIAL_nCTSSERIAL_RXDSERIAL_TXD FTDI_nCTS

FTDI_nRTSFTDI_TXDFTDI_RXD

RS232_nRTSRS232_nCTSRS232_RXDRS232_TXD

UART_MOD_EN (B)

0

1

0

1 0

1

0

1

DEI_EN

USB_ENTTL signal accessby pulling 4 jumpersJ25, J26,J27,J28

EM35X NCP BREAKOUT BOARD

8 8

SCH0681 A0

REVISION NOTES

12

2

B

A

B

A

1


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DWG

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SCHEMATIC NOTES:

-- Version P0 --*Released: 2010-06-11*Initial version released, Version P0 (initial draft)

*Released: 2010-06-11

6) Corrected D5 decal error (was SOT23 instead of SOT323).

PCB LAYOUT NOTES:

*Initial version released, Version P0 (initial draft)

-- Version P0 --

8) Test point coverage for nets without probe access.

*Released: 2010-09-20*Production version release

-- Version A0 --

*Production version release

-- Version A0 --*Released: 2010-09-20

*Changes from P0 to A0: *Changes from P0 to A0:1) Swapped UART1 nets with UART2 nets based on changes for UART1 STM32 BTL.2) Renamed UART1 nets to SER_UART1_TXD, etc.3) Renamed UART2 nets to EZSP_UART1_TXD, etc.4) Updated sheet 7 chart for UART changes.5) Added SJ34-35 for J7 and J33.12.6) Removed SW_DEI_EN and DEI_SW_DEI_EN (DS9, R28, R35, R38).7) Updated J43p11 from DEI_SW_DEI_EN to DEI_HOST_BTL.8) Updated J42p19/20 from DEI_EN to HOST_BTL.9) Symbol clean-up for using PART_NUMBER rather than Manufacturer P/N.10) Replaced 570_0603_100 with _101, and _400 with _401.11) Added Q1 shutdown transistor circuit for DataFlash.12) Changed title block text from EZSP to NCP to reflect product name.13) Corrected 500_4053_001 symbol due to error with Ember P/N (-000 instead of -001).14) Added 1uF cap to input of regulator U1.15) Changed C3 from 554-106A-016 (ESR 7 ohm) to 554-106A-020 (ESR 1 ohm).

5) Added bump-on outlines in SSB and ASB.4) Corrected board outline dimensioning error.

1) Schematic changes reflected in layout.

3) Added pin1 marking for U7 SST.2) Corrected J41p15 SST error (was HGPIO1 instead of HGPIO14).

7) Updated LED0603 decal with Cathode C marking.

TS9

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Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analog-intensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team.

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

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