mcdm37 hardware and software manual - mas...

MCDM37

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MCDM37 Hardware and Software Manual

MCDM37 Hardware and software Manual

Rev. Document Code Released Written Verified Approved

1.0 20/01/12 S.Mascetti,Nicola Perrino

S.Mascetti S.Mascetti

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Revision History

Date Version Description Author(s)

20/01/12 1.0 First Release S.Mascetti

Introduction .......................................................................................................................................... 4 Features ................................................................................................................................................ 4

CPU .................................................................................................................................................. 6 LPDDR ............................................................................................................................................ 7 Nand Flash ....................................................................................................................................... 7 uSD Connector ................................................................................................................................. 7 eMMC Sandisk ................................................................................................................................ 7 Accellerometer ................................................................................................................................. 7 LAN 10/100 Mbit ............................................................................................................................ 7 CAN Controller ................................................................................................................................ 8 Touch Screen Controller .................................................................................................................. 8

Power supply ................................................................................................................................ 8 I2C mapping ......................................................................................................................................... 9 Connectors Pinout .............................................................................................................................. 10

Connector J1 .................................................................................................................................. 10 Connector J2 .................................................................................................................................. 14 J8 service connector ....................................................................................................................... 18 Solder Jumper ................................................................................................................................ 19 Dip Switch SW1 ............................................................................................................................ 19

Board layout ....................................................................................................................................... 20 Software Manual ................................................................................................................................ 22

Installation ...................................................................................................................................... 22 System Requirements ..................................................................................................................... 22 Software Requirements: ................................................................................................................. 22 Partitioning ..................................................................................................................................... 22 Environment Setup ......................................................................................................................... 23 X-loader ......................................................................................................................................... 23 U-boot ............................................................................................................................................ 24

Flashing U-boot ......................................................................................................................... 24 Linux Kernel .................................................................................................................................. 24

Flashing Kernel .......................................................................................................................... 25 Booting Linux Kernel .................................................................................................................... 25

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Boot from NAND....................................................................................................................... 25 Boot from MMC ........................................................................................................................ 26 DM37 GPIO Mappping ............................................................................................................. 27

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Introduction The MCDM37 is a CPU module based on the Texas Instruments AM37xx, DM37xx processors. It is designed to meet a wide variety of applications starting from automotive, industrial, entertainment etc.

Features The features of the MCDM37 module are:

• Supports o AM3703, o AM3715, o TMS320DM3725 o TMS320DM3730

• CPU frequencies 800Mhz and 1Ghz • POWERVR SGX™ Graphics Accelerator (only for AM3715,DM3730) • NEON SIMD Coprocessor • Up to 256Mbyte LPDDR 167Mhz • 256Mbyte Nand Flash • eMMC on board (optional only under request) • Ethernet controller 10/100 Mbit/s • 1 USB OTG 2.0 • 2 USB Host 2.0 HS • Integrated CAN Controller • Integrated resistite 4 wire Touch screen controller • Integrated LCD Controller up to 2048 x 2048, and 24bpp • TVout with NTSC and PAL support • Camera interface. • Integrated Audio Codec • Power 9 to 36VDC or 5V only

The board’s block diagram is

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MCDM37 Hardware Manual

CPUTMS320DM3730 + USBPHY +

COMPANION CHIP

POWER5V and 3V3

LPDDRUp to 256Mbyte

External busBuffers

eMMC

CPLD

Accellerometer

ETHERNETCONTROLLER

LAN9115

J7uSd channel 1

Nand Flash256Mbyte

8 bit

ADDR

CSELECT

DATA

TPO

TPI

CAN BUS

COMM

USB HOST2SPI 1

TVOUT1,2

GPIO

9-36V

5V

SERIAL1,2 (TTL)

J1J2

232TRANS

SERI

AL3

(232

)

J 6

JTAG

RESET

USB OTG

USB HOST1

SERIAL3 (232)

LCD3v3

BuffersLCD

POWER4V

Power Button

3V3

Touch screenController

SPI 4

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CPU The board supports four types of processors: AM3703 Cortex A8 800Mhz / 1Ghz without SGX and DSP AM3715 Cortex A8 800Mhz / 1Ghz with SGX and without DSP TMS320DM3725 Cortex A8 800Mhz / 1Ghz without SGX and with DSP TMS320DM3730 Cortex A8 800Mhz / 1Ghz with SGX and with DSP Some Features of this processors are:

• Compatible with OMAP™ 3 Architecture • ARM® microprocessor (MPU) Subsystem • Up to 1-GHz ARM® Cortex™-A8 Core, Also supports 300, 600, and 800-MHz • NEON SIMD Coprocessor • High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem • Up to 800-MHz TMS320C64x+™ DSP Core • Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels) • Video Hardware Accelerators • POWER SGX™ Graphics Accelerator (DM3730 and AM3715 only) • Tile Based Acrchitecture Delivering up to 20 MPoly/sec

• Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality

• Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0 • Fine Grained Task Switching, Load Balancing, and Power Management • Programmable High Quality Image Anti-Aliasing

• Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core (only DM37xx).

• Eight Highly Independent Functional Units • Six ALUs (32-/40-Bit); Each Supports Single 32- bit, Dual 16-bit, or Quad 8-bit, Arithmetic

per Clock Cycle • Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or

Eight 8 × 8-bit Multiplies (16-Bit Results) per Clock Cycle • Load-Store Architecture With Non-Aligned Support

All processors are software and pin compatible. For more info see the following links below: http://www.ti.com/product/am3703

http://www.ti.com/product/am3703

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and http://www.ti.com/product/dm3730

LPDDR The board has one 32 bit bank of LPDDR. LPDDR are DDR ram but at lower power consumption. Sizes supported are 64Mbyte, 128Mbyte and 256Mbyte. For more info about the LPDDR see the following link: http://www.micron.com/products/dram/mobile_lpdram.html

Nand Flash The board supports a 8/16 bit nand flash. Bootloader, kernel and file system reside in this memory. Sizes 1,2,4 8 Gbit are supported. For more information about the Nand Flash devices see the following link. http://www.micron.com/products/nand_flash/mass_storage.html

uSD Connector The board has a uSD on board connector. Boot from this device is possible (see section XX.X) The SD interface has full compliance with SD command/response sets as defined in the SD Memory Card Specifications, v2.0 including high-capacity SDHC cards up to 32GB.

eMMC Sandisk The board has an eMMC device, it is used to expand the storage capacity of the board (it is mounted only upon request). Supports devices up to 32 Gbyte, and has an 1,4,8 bit interface. The processor MMC interfare is channel 2.

Accellerometer The board has an LIS331DLF a MEMS digital output motion sensor ultra low-power high performance 3-axes “nano” accelerometer. It is driven through the I2C channel 1. It is capable of generating two interrupts that are connected to the GPIO2 and GPIO15 of the Omap companion chip (TPS65930). For More info follow the link below: http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00213608.pdf

LAN 10/100 Mbit The board has an Ethernet Controller LAN9115, the Ethernet signals are routed to the board to board connector and can be connected directly to an ethernet transformer.

http://www.ti.com/product/dm3730

http://www.micron.com/products/dram/mobile_lpdram.html

http://www.micron.com/products/dram/mobile_lpdram.html

http://www.micron.com/products/nand_flash/mass_storage.html

http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00213608.pdf

http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/DATASHEET/CD00213608.pdf

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CAN Controller The board has a Can controller is a stand-alone Controller Area Network (CAN) controller that implements the CAN specification, version 2.0B. It is capable of transmitting and receiving both standard and extended data and remote frames. It is connected to the SPI1 of the processor. The interface has also a dedicated reset and an interrupt connected to the processor.

Touch Screen Controller The board has a 4 wire Touch screen controller. It is connected to the processor though the SPI4. The analog signals are routed through the board to board connectors ready to be used with a touch screen. Processor companion chip The board ha a companion chip that generates all the power supply necessary for the processor to work, it also has an audio codec (I2S) , USB OTG phy and a RTC. It controls the power on and power off of the board. USB 2.0 High speed interface The board has 2 USB 2.0 high speed interfaces, the signals are routed to the board to board connectors. This interface can only be used with High speed devices. If a full speed o low speed device has to be used with this interface a USB hub must be used, or it can be connected to the USB OTG interface.

Power supply The board must be powered through the J2 board to board connector, the supply range is from 9 to 36V, power consumption is 220mA @ 12Vdc A 5V 500mA supply is available through the J2 board to board connector to power additional devices. A 3,3V 500mA supply is available through the J2 board to board connector to power additional devices.

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I2C mapping The following table shows the internal I2C device mapping.

I2C Bus address Device

1 0X48

TPS65930 (USB controller)

1 0X49

TPS65930 (Audio)

1 0X4A

TPS65930 (PWM,IRQ,GPIO)

1 0X4B TPS65930 (Power man)

1 0X30 (WRITE) 0X31 (READ)

LIS331

4 0x12h TPS65930 (Smart Reflex controller)

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Connectors Pinout

Connector J1 PIN NAME DIR DESCRIPTION LOGIC LEVEL

D1 ETH_TX+ OUT ETHERNET TRASMIT POS SIGNAL ECL

B1 ETH_RX+ IN ETHERNET RECEIVE POS SIGNAL ECL

C1 ETH_TX- OUT ETHERNET TRASMIT NEG SIGNAL ECL

A1 ETH_RX- IN ETHERNET RECEIVE NEG SIGNAL ECL

D2 GND PWR GND POWER

B2 GND PWR GND POWER

C2 FULL_DUPLEX OUT FULL DUPLEX LED SIGNAL TTL 3,3V

A2 SPI4_MISO IN SPI4 MASTER IN SLAVE OUT TTL 1,8V

D3 SPEED_100 OUT 10/100 SPEED LED SIGNAL TTL 3,3V

B3 SPI4_SPCK OUT SPI4 CLOCK TTL 1,8V

C3 LINK_ACT OUT LINK AND ACTIVITY LED SIGNAL TTL 3,3V

A3 SPI4_MOSI OUT SPI4 MASTER OUT SLAVE IN TTL 1,8V

D4 I2C2_SCL OUT I2C CHANNEL2 CLOCK TTL 1,8V

B4 SPI4_NPCS0 OUT SPI1 CHIP SELECT 0 TTL 1,8V

C4 VIN_USB IN 5V TO/FROM USB OTG CONNECTOR TTL 3,3V

A4 RXD3_232 IN SERIAL 3 RX 232 SIGNAL USED FOR CONSOLE

TTL 3,3V

D5 MMC1_D4 BI MMC1 DATA 4 TTL 3,3V

B5 TXD3_232 OUT SERIAL 3 TX 232 SIGNAL USED FOR CONSOLE

TTL 3,3V

C5 MMC1_D5 BI MMC1 DATA 5 TTL 3,3V

A5 PWM0 OUT PWM0 SIGNAL OUTPUT TTL 1,8V

D6 RXD1 IN SERIAL RXD1 SIGNAL TTL 1,8V

B6 PWM1 OUT PWM1 SIGNAL OUTPUT TTL 1,8V

C6 CTS1 IN SERIAL CTS1 SIGNAL TTL 1,8V

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PIN NAME DIR DESCRIPTION LOGIC LEVEL

A6 GPIO10 BI GPIO10 TTL 1,8V

D7 RTS1 OUT SERIAL RTS0 SIGNAL TTL 1,8V

B7 GPIO186 BI GPIO186 TTL 1,8V

C7 TXD1 OUT SERIAL TXD1 SIGNAL TTL 1,8V

A7 I2C3_SDA BI I2C CHANNEL 3 DATA SIGNAL TTL 1,8V


B8 UART2_RXD IN SERIAL 2 RXD SIGNAL TTL 1,8V

C8 SPI1_MISO IN SPI0 MASTER IN SLAVE OUT TTL 1,8V

A8 UART2_CTS IN SERIAL 2 CTS SIGNAL TTL 1,8V

D9 SPI1_MOSI OUT SPI1 MASTER OUT SLAVE IN TTL 1,8V

B9 UART2_TXD OUT SERIAL 2 TXD SIGNAL TTL 1,8V

C9 SPI1_CLK OUT SPI1 CLOCK TTL 1,8V

A9 UART2_RTS OUT SERIAL 2 RTS SIGNAL TTL 1,8V

D10 SPI1_CS0 OUT SPI1 CHIP SELECT 0 TTL 1,8V


C10 GND PWR GND POWER

A10 LCDCC OUT LCD CONTRAST CONTROL TTL 3,3V

D11 MMC1_D6 BI MMC1 DATA 6 TTL 3,3V

C11 I2C2_SDA BI I2C CHANNEL 2 DATA SIGNAL TTL 1,8V

B11 LCDVSYNC OUT LCD VERTICAL SYNC TTL 3,3V

A11 LCDHSYNC OUT LCD HORIZONTAL SYNC TTL 3,3V

D12 TVOUT1 OUT TVOUT SIGNAL TO VIDEO AMPLIFIER VIDEO


C12 TVOUT1 OUT TVOUT SIGNAL TO VIDEO AMPLIFIER VIDEO

A12 LCDDOTCK OUT LCD DOT CLOCK TTL 3,3V



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C13 MMC1_CLK OUT MMC1 CLOCK SIGNAL TTL 3,3V

A13 LCDD1 OUT LCD CONTROLLER DATA 1 TTL 3,3V

D14 MMC1_CMD IN MMC1 COMMAND SIGNAL TTL 3,3V

C14 MMC1_CD IN MMC1 CARD DETECT TTL 3,3V

B14 LCDD13 OUT LCD CONTROLLER DAT1 13 TTL 3,3V


D15 MMC1_DATA1 BI MMC1 DATA 1 TTL 3,3V

B15 LCDD14 OUT LCD CONTROLLER DATA 14 TTL 3,3V

C15 MMC1_DATA0 BI MMC1 DATA 0 TTL 3,3V


D16 MMC1_DATA2 BI MMC1 DATO 2 TTL 3,3V





B17 LCD_DEN OUT LCD DATA ENABLE TTL 3,3V





C18 CANTX OUT CAN BUS TX SIGNAL TTL 3,3V


D19 CANRX IN CAN BUS RX SIGNAL TTL 3,3V




D20 HSUSB_ID IN OTG USB_ID SIGNAL TTL 3,3V

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C20 I2C3_SDA BI I2C CHANNEL 3 DATA SIGNAL TTL 1,8V


D21 MCBSP2_DR IN MULTICHANNEL BUFFERED SERIAL PORT RECEIVE SIGNAL

TTL 1,8V


C21 MCBSP2_DX OUT MULTICHANNEL BUFFERED SERIAL PORT TRASMIT SIGNAL

TTL 1,8V


D22 MCBSP2_FS OUT MULTICHANNEL BUFFERED SERIAL PORT FRAME SINC SIGNAL

TTL 1,8V


C22 MCBSP2_CLK OUT MULTICHANNEL BUFFERED SERIAL PORT CLOCK SIGNAL

TTL 1,8V






D24 HOST2_D+ BI USB HOST 2 POSITIVE SIGNAL TTL 5V


C24 HOST2_D- BI USB HOST 2 NEGATIVE SIGNAL TTL 5V


D25 HSUSB_DP BI USB OTG POSITIVE SIGNAL TTL 5V


C25 HSUSB_DN BI USB OTG NEGATIVE SIGNAL TTL 5V


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Connector J2 PIN NAME DIR DESCRIPTION LOGIC LEVEL

D1 ADCIN0 IN ADC CHANNEL 0 INPUT ANALOG


C1 CAM_RESET OUT CAMERA INPUT RESET TTL 1,8V

A1 PWRON_BUTTON IN ON/OFF POWER BUTTON TTL 3,3V

D2 CAM_HS IN CAMERA INPUT HSYNC TTL 3,3V

B2 RESET_BUTTON IN EXTERNAL CPU RESET ACTIVE LOW TTL 3,3V

C2 GND PWR GND POWER TTL 3,3V

A2 NU BI NOT USED

D3 B_CLE OUT BUS COMMAND LATCH ENABLE TTL 3,3V


C3 B_Nbe1 OUT EXPANSION Bus nbe1 signal TTL 3,3V

A3 GND PWR GND POWER


B4 BADDR10 OUT ADDRESS 10 TTL 3,3V


A4 BADDR9 OUT ADDRESS 9 TTL 3,3V

D5 TOUCH_BUSY IN TOUCH BUSY SIGNAL FOR EXTERNAL TOUCH CONTROLLER

(NOT USED)

TTL 1,8V


C5 PREDRIV_L OUT AUDIO PREDRIVE LEFT SIGNAL FOR CLASS D AMPLIFIER

1,5VPP


D6 PREDRIV_R OUT AUDIO PREDRIVE RIGHT SIGNAL FOR CLASS D AMPLIFIER

1,5VPP


C6 AUXR IN SINGLE ENDED AUXILIARY ANALOG INPUT SIGNAL


D7 MIC_MAINM_IN IN NEGATIVE MICROPHONE INPUT SIGNAL

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C7 MIC_MAINP_IN IN POSITIVE MICROPHONE INPUT SIGNAL


D8 MICBIAS OUT MICROPHONE BIAS SIGNAL 2,2V




D9 B_ADV_ALE OUT BUS ALE SIGNAL TTL 3,3V


C9 BWAIT IN BUS WAIT SIGNAL TTL 3,3V

A9 BDATA15 BI EXPANSION DATA BIT15 TTL 3,3V

D10 CAM_D8 IN CAMERA DATA 8 INPUT TTL 1,8V

B10 BDATA14 BI EXPANSION DATA BIT14 TTL 3,3V

C10 CAM_D9 IN CAMERA DATA 9 INPUT TTL 1,8V


D11 B_RESETN OUT System Reset TTL 3,3V










C13 CAM_VS IN CAMERA VSYNC TTL 1,8V


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D14 CAM_CLKB OUT CAMERA CLOCKB OUTPUT TTL 1,8V

C14 B_CLK OUT EXTERNAL BUS CLK TTL 3,3V





C15 CAM_CLKA OUT CAMERA CLOCKA OUTPUT TTL 1,8V


D16 CAM_WEN IN CAMERA WRITE ENABLE SIGNAL TTL 1,8V


C16 CAM_PCLK OUT CAMERA PIXEL CLOCK INPUT TTL 1,8V


D17 CAM_STROBE OUT FLASH STROB CONTROL OUTPUT TTL 1,8V



A17 BWEn OUT BUS WRITE SIGNAL TTL 3,3V


B18 BRDn OUT BUS WRITE SIGNAL TTL 3,3V


A18 BCS3n OUT BUS CHIP SELECT 3 TTL 3,3V


B19 BCS4n OUT BUS CHIP SELECT 4 TTL 3,3V




B20 BCS0n OUT BUS CHIP SELECT 0 TTL 3,3V

C20 VBAT IN RTC BATT POWER 3V

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B21 ADCIN0 IN ADC CHANNEL 0 INPUT ANALOG

C21 VIN PWR VIN POWER (9 – 36VDC)

A21 TS_BOTTOM IN TOUCH SCREEN BOTTOM SIGNAL ANALOG

D22 VIN PWR VIN POWER (9 – 36VDC)

B22 TS_TOP IN TOUCH SCREEN TOP SIGNAL ANALOG

C22 VIN PWR VIN POWER (9 – 36VDC)

A22 TS_LEFT IN TOUCH SCREEN LEFT SIGNAL ANALOG

D23 3V3 PWR 3,3V OUT TO CARRIER BOARD

B23 TS_RIGHT IN TOUCH SCREEN RIGHT SIGNAL ANALOG

C23 3V3 PWR 3,3V OUT TO CARRIER BOARD


D24 3V3 PWR 3,3V OUT TO CARRIER BOARD


C24 5V PWR 5,0V OUT TO CARRIER BOARD

A24 HOST1_D- BI USB HOST 1 NEGATIVE SIGNAL TTL 5V

D25 5V PWR 5,0V OUT TO CARRIER BOARD

B25 HOST1_D+ BI USB HOST 1 POSITIVE SIGNAL TTL 5V

C25 5V PWR 5,0V OUT TO CARRIER BOARD


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J8 service connector PIN NAME DIR DESCRIPTION LOGIC LEVEL

1 VIN_USB IN USB_OTG_DETECT TTL 5V

2 3V3 PWR 3,3V POWER SIGNAL

3 HSUSB_DN BI USB OTG NEGATIVE SIGNAL TTL 5V

4 CPLD_TDO OUT CPLD JTAG DATA OUT TTL 3,3V

5 HSUSB_DP BI USB OTG POSITIVE SIGNAL TTL 5V

6 CPLD_TDI IN CPLD JTAG DATA IN TTL 3,3V

7 HSUSB_ID IN USB OTG ID SIGNAL TTL 5V

8 CPLD_TMS IN CPLD JTAG TEST MODE TTL 3,3V

9 TDI IN JTAG DATA IN TTL 1,8V

10 CPLD_TCK IN CPLD JTAG CLOCK TTL 3,3V

11 TDO OUT JTAG DATA OUT TTL 1,8V

12 TXD3_232 OUT DEBUG CONSOLE TX SIGNAL RS232

13 RTCK OUT RETURN TEST CLOCK TTL 1,8V

14 RXD3_232 IN DEBUG CONSOLE RX SIGNAL RS232

15 TCK IN JTAG CLOCK TTL 1,8V

16 TRSTn IN JTAG RESET TTL 1,8V

17 JTAG_EMU0 IN JTAG_EMU0 SIGNAL TTL 1,8V

18 TMS IN JTAG MODE SELECT TTL 1,8V

19 JTAG_EMU1 IN JTAG_EMU1 SIGNAL TTL 1,8V

20 GND POWER GND POWER

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Solder Jumper

NAME DESCRIPTION DEFAULT

JPS1 WHEN CLOSED CONNECTS THE BOARDS 3,3V TO THE B2B

CONNECTOR FOR EXTERNAL USE.

CLOSED

JPS2 FOR INTERNAL USE ONLY CLOSED

JPS3 FOR INTERNAL USE ONLY CLOSED

JPS4 JPS4 WHEN CLOSED IS USED TO CONNECT THE INTERNAL 5V REGULATOR TO THE BOARD.

WHEN OPEN, THE 5V OF THE BOARD MUST BE PROVIDED THROUGH THE

B2B CONNECTOR.

CLOSED

JPS5 FOR INTERNAL USE ONLY OPEN

JPS6 FOR INTERNAL USE ONLY OPEN

Dip Switch SW1

SW0 SW1 BOOT SEQUENCE

DEFAULT

OFF OFF NAND BOOT USB OTG

UART3 MMC1

This is the factory default setting

OFF ON MMC1 USB OTG

UART3

ON OFF USB UART3 MMC1 NAND

ON ON UART3 NAND

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Board layout

Board top Layout

Pag. 21 of 33

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Board layout bottom side

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Software Manual This document describes how to install and work with Texas Instruments' Platform Support Package (PSP) for DM37x platform running Linux. This PSP provides a fundamental software platform for development, deployment and execution on. It abstracts the functionality provided by the hardware. The product forms the basis for all application development on this platform. In this context, the document contains instructions to: • Install the release • Build the sources contained in the release The document also provides detailed description of drivers and modules specific to this platform as implemented in the PSP.

Installation

System Requirements

Software Requirements: • CodeSourcery ARM tool chain version 2009-q1

Partitioning SW components are partitioned as in the following: Primary boot loader Secondary boot loader u-boot Kernel Root file system First 4 components are stored in the internal NAND flash. 0x00020000-0x00080000 : "X-Loader" 0x00080000-0x00260000 : "U-Boot" 0x00260000-0x00280000 : "U-Boot Env" 0x00280000-0x00680000 : "Kernel" 0x00680000-0x10000000 : "Root File System"

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For the rootfs there are 3 options: In the application development phase it is mounted as a NFS file system from development host, In the release phase is stored in NAND or in MMC/SD.

Environment Setup 1. Set the environment variable PATH to contain the binaries of the CodeSourcery cross-compiler tool-chain. For example, in bash: $ export PATH=/opt/toolchain/2009-q1/bin:$PATH 2. Add location of u-boot tools to the PATH environment variable (required for mkimage utility that is built as part of u-boot) For example, in bash: $ export PATH=/opt/u-boot/tools:$PATH

X-loader Introduction X-loader is loaded by ROM boot loader into internal RAM. X-loader support boot from NAND, MMC/SD. Compiling X-Loader Change to the base of the X-Loader directory. $ cd ./x-load Remove the intermediate files generated during build. This step is not necessary when building for the first time. $ make CROSS_COMPILE=arm-none-linux-gnueabi- ARCH=arm distclean Choose the configuration for OMAP3 Beagle. $ make CROSS_COMPILE=arm-none-linux-gnueabi- ARCH=arm omap3beagle_config Initiate the build. $ make CROSS_COMPILE=arm-none-linux-gnueabi- ARCH=arm On successful completion, file x-load.bin will be created in the current directory.

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Signing x-load.bin The file x-load.bin needs to be signed before it can be used by the ROM bootloader. To sign the X-Loader binary: $ signGP x-load.bin The signing utility creates x-load.bin.ift in the current directory.

U-boot Compiling U-boot Change to the base of the u-boot directory. $ cd ./u-boot Remove the intermediate files generated during build. This step is not necessary when building for the first time. $ make CROSS_COMPILE=arm-none-linux-gnueabi- ARCH=arm distclean Choose the configuration for OMAP3 Beagle: $ make CROSS_COMPILE=arm-none-linux-gnueabi- ARCH=arm omap3_beagle_config Initiate the build: $ make CROSS_COMPILE=arm-none-linux-gnueabi- ARCH=arm On successful completion, file u-boot.bin will be created in the current directory.

Flashing U-boot To flash u-boot.bin to the NAND execute the commands listed below: OMAP3 beagleboard.org # tftp 0x82000000 u-boot.bin OMAP3 beagleboard.org # nand erase 0x00080000 0x001E0000 OMAP3 beagleboard.org # nand write 0x82000000 0x00080000 0x001E0000

Linux Kernel This chapter describes the steps required to build and configure the Linux kernel. It also provides basic steps to boot kernel on the EVM. Compiling Linux Kernel Change to the base of the Linux source directory. Choose default kernel configuration for your platform. $ make CROSS_COMPILE=arm-none-linux-gnueabi- ARCH=arm omap3_beagle_defconfig

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To change kernel configuration use the command: $ make CROSS_COMPILE=arm-none-linux-gnueabi- ARCH=arm xconfig Initiate the build. $ make CROSS_COMPILE=arm-none-linux-gnueabi- ARCH=arm uImage On successful completion, file uImage will be created in the directory ./arch/arm/boot. Copy this file to the root directory of your TFTP server.

Flashing Kernel To flash uImage to the NAND execute the commands listed below: OMAP3 beagleboard.org # tftp 0x82000000 uImage OMAP3 beagleboard.org # nand erase 0x00280000 0x00400000 OMAP3 beagleboard.org # nand write 0x82000000 0x00280000 0x00400000

Booting Linux Kernel

Boot from NAND Power on the board and wait for u-boot to come up. When kernel image and filesystem are flashed on the NAND device: NAND Boot mode $ nand read 0x82000000 280000 400000 $ setenv bootargs 'mem=128M console=ttyS0,115200n8 noinitrd root=/dev/mtdblock4 rw rootfstype=jffs2 ip=dhcp' $ bootm 0x82000000 When kernel image is flashed on the NAND device, and NFS mounted filesystem is being used: NFS Boot mode $ nand read 0x82000000 280000 400000 $ setenv bootargs 'mem=128M console=ttyS0,115200n8 noinitrd rw root=/dev/nfs nfsroot=/mnt/nfs,nolock ip=dhcp' $ bootm 0x82000000

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Boot from MMC Power on Board and wait for u-boot to come up. When kernel image and filesystem are available on the MMC card: $ mmc init $ fatload mmc 0 0x82000000 uImage $ setenv bootargs 'mem=128M console=ttyS0,115200n8 root=/dev/mmcblk0p2 rw rootfstype=ext3 rootwait ' $ bootm 0x82000000 Note Once the Linux kernel boots, login as "root". No password is required. Understanding boot arguments mpurate This argument is used to specify the MPU frequency to be set during the boot process. The desired frequency is set statically. The frequency can be specified in MHz; and it must correspond to the valid OPP for the processor. For example, to set the MPU frequency to 600MHz, add the following to the bootargs: mpurate=600 Since, the OPP definition varies across processors, the list of possible values will vary across the processors as well. The change in MPU frequency results in appropriate change in the IVA2 frequency (where available). Note Setting the frequency through mpurate is independent of cpufreq. ethaddr This argument is used to specify the eth mac address to be set during the boot process.

MCDM37

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DM37 GPIO Mappping

I/O Line Bootl Function Comments

GPIO0 SYS_IRQ0n Interrupt from TPS65930. GPIO1 CLK_REQ Clock req to TPS65930 GPIO2 SYS_BOOT0 Strap pin per config for boot GPIO3 SYS_BOOT1 Strap pin per config for boot GPIO4 SYS_BOOT2 Strap pin per config for boot GPIO5 SYS_BOOT3 Strap pin per config for boot GPIO6 SYS_BOOT4 Strap pin per config for boot GPIO7 SYS_BOOT5 Strap pin per config for boot GPIO8 SYS_BOOT6 Strap pin per config for boot GPIO9 SLEEPn Sleep request from omap GPIO10 REGEN NOT USED

GPIO11 JTAG_EMU0 Jtag Emu0 pin

GPIO12 hsusb1_stp hsusb1_stp

GPIO13 hsusb1_clk hsusb1_clk

GPIO14 hsusb1_ data0 hsusb1_ data0








GPIO22 hsusb1_ dir hsusb1_ dir

GPIO23 hsusb1_ nxt hsusb1_ nxt

GPIO24 Hsusb2_ clk USb Host 2 clock

GPIO25 Hsusb2_ stp USb Host 2 stop

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Bootl I/O Line Function Comments GPIO27 Hsusb2_ nxt USb Host 2 next

GPIO28 Hsusb2_ dat0 USb Host 2 data GPIO29 Hsusb2_ dat1 USb Host 2 data GPIO30 RESWARMn Warm Reset to system GPIO34 GPMC _A1 Local Bus address Local Bus address GPIO35 GPMC _A2 Local Bus address GPIO36 GPMC _A3 Local Bus address GPIO37 GPMC_A4 Local Bus address GPIO38 GPMC_A5 Local Bus address GPIO39 GPMC_A6 Local Bus address GPIO40 GPMC_A7 Local Bus address GPIO41 GPMC_A8 Local Bus address GPIO42 GPMC_A9 Local Bus address GPIO43 GPMC_A10 GPIO44 GPMC_D8 Local Bus data Local Bus data GPIO45 GPMC_D9 Local Bus data GPIO46 GPMC_D10 Local Bus data GPIO47 GPMC_D11 Local Bus data

GPIO48 GPMC_D12 Local Bus data GPIO49 GPMC_D13 Local Bus data GPIO50 GPMC_D14 Local Bus data GPIO51 GPMC_D15

GPIO54 GPMC_CS3 Local Bus chip select 3



GPIO57 GPMC_CS6

GPIO58 GPMC_CS7

GPIO59 GPMC_CLK NOT USED

GPIO60 GMPC_MBE0_CLE CLE nand signal

GPIO61 GPMC_nBE1 Be1 del bus dati GPIO62 GPMC_WP# Nand Write protect

LAN INTERRUPT GPIO65 IRQ_LAN_1V8

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I/O Line Bootl Function Comments

GPIO67 DSS_HSYNC LCD hsync

GPIO68 DSS_VSYNC LCD Vsync

GPIO69 DSS_ACBIAS LCD_ Denable pin

GPIO70 DSS_D0 LCD Data
























GPIO94 CAM_HS Cam Module Hsync GPIO95 CAM_VS Cam Module Vsync

GPIO96 CAM_XCLKA Cam Module ClockA

GPIO97 CAM_PCLK Cam Module Pixel Clock

GPIO98 CAM_RESET Cam Module reset

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I/O Line Bootl Function Comments GPIO99 CAM_D0 Cam Module Data

GPIO100 CAM_D1 Cam Module Data GPIO101 CAM_D2 Cam Module Data

GPIO102 CAM_D3 Cam Module Data GPIO103 CAM_D4 Cam Module Data

GPIO104 CAM_D5 Cam Module Data GPIO105 CAM_D6 Cam Module Data GPIO106 CAM_D7 Cam Module Data GPIO107 CAM_D8 Cam Module Data GPIO108 CAM_D9 Cam Module Data

GPIO109 CAM_D10 Cam Module Data GPIO110 CAM_D11 Cam Module Data GPIO111 CAM_XCLKB Cam Module clockB GPIO116 mcbsp2_fsx Codec Audio Frame Sync GPIO117 mcbsp2_ clkx Codec Audio Clock GPIO118 mcbsp2_dr Codec Audio data in GPIO119 mcbsp2_dx Codec Audio Data out GPIO120 MMC1_CLK MMC1 Clock GPIO121 MMC1_CMD MMC1 command GPIO122 MMC1_DAT0 MMC1 data GPIO123 MMC1_DAT1 MMC1 data GPIO124 MMC1_DAT2 MMC1 data GPIO125 MMC1_DAT3 MMC1 data GPIO126 MMC1_DAT4 MMC1 data GPIO127 MMC1_DAT5 MMC1 data GPIO128 MMC1_DAT6 MMC1 data GPIO129 MMC1_DAT7 MMC1 data GPIO130 MMC2_CLK Internal eMMC_CLK GPIO131 MMC2_CMD Internal eMMC_CMD GPIO132 MMC2_DAT0 Internal eMMC_DAT0 GPIO133 MMC2_DAT1 Internal eMMC_DAT1 GPIO134 MMC2_DAT2 Internal eMMC_DAT2 GPIO135 MMC2_DAT3 Internal eMMC_DAT3 GPIO136 MMC2_DAT4 Internal eMMC_DAT4 GPIO137 MMC2_DAT5 Internal eMMC_DAT5 GPIO138 MMC2_DAT6 Internal eMMC_DAT6 GPIO139 MMC2_DAT7 Internal eMMC_DAT7 GPIO140 UART2_CTS UART2_CTS GPIO141 UART2_RTS UART2_RTS GPIO142 UART2_TX UART2_TX

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I/O Line Bootl Function Comments GPIO143 UART2_RX GPIO148 UART1_TX GPIO149 UART1_RTS GPIO150 UART1_CTS GPIO151 UART1_RX Uart1 Rx signal GPIO156 SPI4_CLK Touch spi clk GPIO157 TOUCH_IRQ IN Touch screen interrupt GPIO158 SPI4_SIMO Touch spi MOSI GPIO159 SPI4_SOMI Touch spi MISO GPIO160 MCBSP_CLKS Control for 256 ´ FS CLK Input GPIO161 SPI4_CS0 Touch spi CS GPIO162 TOUCH_BUSY IN Touch Busy signal GPIO163 USB2HS_nRST USB channel 2 phy reset OUT ‘1’ GPIO164 USB1HS_nRST USB channel 1 phy reset OUT ‘1’ GPIO165 UART3_RX Uart3 RX signal GPIO166 UART3 TX Uart3 TX signal

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I/O Line Bootl Function Comments GPIO167 CAM_WEN Cam Write enable GPIO168 I2C2_SCL I2C Clock GPIO169 hsusb0_ data3 USB 0 data 3 GPIO170 NOT AVAILABLE

GPIO171 SPI1_CLK Can Bus SPI clk

GPIO172 SPI1_MOSI Can Bus SPI MOSI

GPIO173 SPI1_MISO Can Bus SPI MISO

GPIO174 SPI1_CS0 Can Bus SPI CS0

GPIO177 hsusb2_ data2

GPIO178 hsusb2_ data7 USB 2 data

GPIO179 hsusb2_ data4 USB 2 data

GPIO180 hsusb2_ data5 USB 2 data USB 2 data GPIO181 hsusb2_ data6

USB 2 data GPIO182 hsusb2_ data3 I2C2 data GPIO183 I2C2_SDA

I2C3 clock GPIO184 I2C3_SCL I2C3 data GPIO185 I2C3_SDA GPIO186 GPIO186 USB 0 data GPIO188 Hsusb0_ data4 USB 0 data GPIO189 Hsusb0_ data5 USB 0 data GPIO190 Hsusb0_ data6

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GPIO lines that come from the TPS65930

TPS65930 GPIO

I/O Line Reset State

Function Sos

Comments SOS

GPIO_0 L Card Detect1 SD Card Detect (=’0’ card inserted)

GPIO_1 L

Card Detect2 SD Card Write protect. (=’0’ card write protected)

GPIO_2 L INT1 ACC Int1

GPIO_6 PWM0 PWM0

GPIO_7 PWM1 PWM1

GPIO_13 L GPIO_13 GPIO_15 L INT2 Acc Int2

GPIO_17 L NU GPIO_16 L NU

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