mcf5307 dram ctrl - nxp semiconductors · • ras[1:0] - row address strobe - used to select 1 of 2...

MCF5307 DRAM CTRL 1- 1Motorola Cold Fire ®

MCF5307 DRAM CONTROLLER


▼ MCF5307 DRAM Controller– Supports 2 banks of DRAM– Supports External Masters– Programmable Wait States & Refresh

Timer– Supports Page Mode and Burst Page

Mode– Supports 8-, 16-, & 32-bit wide DRAM

banks– Supports Extended Data Out DRAMs– Supports Asynchronous or

Synchronous DRAMs

MCF5307 DRAM CONTROLLER

MCF5307

8KUnifiedCache

SystemBus

Controller

Interrupt CtrDUART

General Purpose

I/O

M-BusJTAG

Debug Rev BModule

4 DMA

2 Timers

DRAM Cntr &

Chip Selects

PLL

I Addr Gen

I Fetch1

I Fetch2

I Decode

Instr Buf

Dec&Sel Op

A Gen & Ex

MAC

4K SRAM


▼ THE DRAM CONTROLLER HAS 2 MAJOR MODES OF OPERATION:1) ASYNCHRONOUS. Has 4 basic modes of operation:

– Non-page mode– Burst page mode– Contiguous page mode– Extended Data Out mode

2) SYNCHRONOUS. Supports common SDRAM implementations.– Burst page mode– Continuous Page mode

▼THESE 2 MODES WORK VERY DIFFERENTLY. – The DRAM registers are used differently– The DRAM pins are used differently– Both banks of DRAM will be in the same mode of operation based on programming

the DRAM Configuration Register’s (DCR) Synchronous Operation bit (SO bit)

MCF5307 ASYNCHRONOUS & SYNCHRONOUS OPERATION


NAM- NO ADDRESS MULTIPLEXING1 - THE DRAM CONTROLLER WILL NOT MULTIPLEX THE EXTERNAL ADDRESS BUS0 - THE DRAM CONTROLLER WILL MULTIPLEX THE EXTERNAL ADDRESS BUS

MCF5307 DRAM CONTROL REGISTER: ASYNC MODE

DCR - DRAM CONTROL REGISTER

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

Master RST: 0 - - - - - - - - - - - - - - -

SO - NAM RRA RRP RC

SO- SYNCHRONOUS OPERATION1 - SYNCHRONOUS MODE0 - ASYNCHRONOUS MODE

RRA- REFRESH RAS ASSERTED00 - 2 CLOCKS01 - 3 CLOCKS10- 4 CLOCKS11- 5 CLOCKS

RRP- REFRESH RAS PRECHARGED00 - 1 CLOCK01 - 2 CLOCKS10- 3 CLOCKS11- 4 CLOCKS

RC- REFRESH COUNTCONTROLS THE FREQUENCY OF REFRESH PERFORMED BY THE DRAM CONTROLLER:(RC + 1) * 16 = REFRESH CLOCKS

▼ When DCR[SO]=0, this register is defined as follows:


MCF5307 ADDRESS & CONTROL REGISTERS: ASYNC MODE

BA BASE ADDRESS. USED IN CONJUNCTION WITH THE BAM (MASK) BITS IN THE DCMR. COMPARED WITH BUS ADDRESS & MASK TO DETERMINE DRAM HIT OR MISS.

RE REFRESH ENABLE (1 = Refresh associated DRAM bank 0 = Do not Refresh associated DRAM bank)

CAS COLUMN ADDRESS STROBE TIMING (00 = 1 CLK; 01 = 2 CLKS; 10 = 3 CLKS; 11 = 4 CLKS)

RP RAS PRECHARGE ENCODING (00 = 1 CLK; 01 = 2 CLKS; 10 = 3 CLKS; 11 = 4 CLKS)

RNCN RAS NEGATE TO CAS NEGATE (0 = RAS negated concurrently with CAS; 1= RAS negated 1 CLK before CAS)

RCD RAS TO CAS DELAY (0 = 1 CLK; 1 = 2 CLK)

EDO EXTENDED DATA OUT (0 = EDO operation disabled; 1 = EDO operation enabled)

PS PORT SIZE (00 = 32-bit port; 01 = 8-bit port; 10 =16-bit port; 11 =16-bit port)

PM PAGE MODE (00 = No page mode; 01 =Page mode or bursts only; 10 = Reserved; 11 = Continuous page mode)

ACR0[31:0] & ACR1[31:0] -ADDRESS & CONTROL REGISTERS

RST: - - - - - - - - - - - - - - - -

BA [31:18] - -B31.............................................................................................................................B18 B17 B16

RE - CAS RP RNCN RCD - EDO PS PM - -


RST: 0 - - - - - - - - - - - - - - 0



MCF5307 DRAM CONTROLLER MASK REGISTERS: ASYNC MODE

BAM BASE ADDRESS MASK. (0 =Associated address bit is compared in DRAM hit; 0 =Associated address bit is ignored in DRAM hit)

WP WRITE PROTECT. (0 =Allow write accesses; 1 =Ignore write accesses)

ADDRESS MODIFIER MASKS: (0 =Allow associated access type; 1 =Ignore associated access type)

C/I CPU SPACE/ INTERRUPT ACKNOWLEDGE)

AM ALTERNATE MASTER

SC SUPERVISOR CODE

SD SUPERVISOR DATA

UC USER CODE

UD USER DATA

V VALID BIT ENCODING 0 = DRAM Accesses not decoded; 1 = DRAM Accesses decoded)

DCMR0[31:0] & DCMR BASE[31:0] -DRAM CONTROLLER MASK REGISTERS

RST: - - - - - - - - - - - - - - - -

BAM [31:18] - -

B31.............................................................................................................................B18 B17 B16

RESERVED WP - C/I AM SC SD UC UD V


RST: - - - - - - - - - - - - - - - -



MCF5307 ASYNCHRONOUS MODE: SIGNAL DESCRIPTION

ADDR [A25-A17]

TS

RAS[1:0]

CAS[3:0]

DRAMRW

DATA [31-0]

M C F 5 3 0 7

TA

• RAS[1:0] - ROW ADDRESS STROBE - USED TO SELECT 1 OF 2 DRAM BANKS.

• CAS[3:0] - COLUMN ADDRESS STROBE - USED TO SELECT 1 OF 4-BYTE LANES IN A 32-BIT ORGANIZED MEMORY.

• DRAMRW - DRAM WRITE, ASSERTS TO SIGNIFY A WRITE OPERATION TO DRAM AND ALLOWS SEPARATE REFRESH CYCLES REGARDLESS TO R/W STATE.


MCF5307 ASYNCHRONOUS MODE: DRAM CONTROLLER INTERFACE TO 1 OF 2-BANKS

RAS CAS1

RAS CAS2

RAS CAS3 [D0:7]

[D8:15]

[D24:31]

[D16:23]

DATA [31:0]

TO OTHER DEVICES

M C F 5 3 0 7

256Kx8 DRAM

RAS CAS0

D

A

T

A

B

U

S

CAS[3:0]

WE

WE

WE

WE

DRAMW

CLOCK

TS(OPTIONAL)

ADDR

RAS

CAS

DATA

DRAMW

ROW COLUMN ROW COLUMN

TWO CONSECUTIVE READ CYCLES

ADDR_BUS

RAS

G

Data Data

1 2 3 4 1 2 3 4

RNCN =0 RNCN =0


MCF5307 ASYNC BURST PAGE MODE READ

CLOCK

TS

ADDR

RAS

CAS

DATA

DRAMW

TAINTERNAL

1 2 3 4

COLUMN COLUMNROW

RCD=0 CAS =01

1 2 3 1 2 3

COLUMN


MCF5307 ASYNC BURST PAGE MODE WRITE

CLOCK

TS

ADDR

RAS

CAS

DATA

DRAMW

TA

1 2 3 4

COLUMN COLUMNROW

RCD=0 CAS =01

1 2 3 1 2 3

DATA DATA DATA

COLUMN


MCF5307 CONTINUOUS PAGE MODE

CLOCK

AS

ADDR

RAS

CAS

DATA

DRAMW

TA

1 2 3 4

COLUMN COLUMNROW

RCD=0 CAS =01

1 2 3 1 2 3 4

DATA DATA DATA

COLUMN

RNCN=1

PAGE HIT PAGE MISS


MCF5307 EDO READ OPERATION

CLOCK

TS

ADDR

RAS

CAS

DATA

DRAMW

TAINTERNAL

1 2 3 4

COLUMNROW

RCD=0 CAS =00

1 2 1 2 1 2


MCF5307 ASYNCHRONOUS DRAM REFRESH CYCLE

CAS BEFORE RAS REFRESH TIMING

CLOCK

RAS

CAS

DRAMW


IS- INITIATE SELF REFRESH COMMAND1 - INITIATE SELF REFRESH OR STAY IN SELF REFRESH0 - TAKE NO ACTION OR EXIT SELF REFRESH

MCF5307 DRAM CONTROL REGISTER: SYNCHRONOUS MODE

DCR - DRAM CONTROL REGISTER


Master RST: 0 - - - - - - - - - - - - - - -

SO IS NAM COC IP RTIM RC

SO- SYNCHRONOUS OPERATION1 - SYNCHRONOUS MODE0 - ASYNCHRONOUS MODE

COC- COMMAND ON CLOCK ENABLE0 - CLOCK ENABLE ON SCKE PIN1 - COMMAND ON SCKE PIN

IP- INITIATE PRECHARGE ALL COMMAND0 - TAKE NO ACTION1 - INITIATE PALL COMMAND

RC- REFRESH COUNTCONTROLS THE FREQUENCY OF REFRESH PERFORMED BY THE DRAM CONTROLLER:(RC + 1) * 16 = REFRESH CLOCKS


RTIM- REFRESH TIMING (REFRESH TO ACTV, i.e. TRC)00- 3 CLOCKS01- 6 CLOCKS10,11- 9 CLOCKS


MCF5307 ADDRESS & CONTROL REGISTERS: SYNC MODE

BA BASE ADDRESS. USED IN CONJUNCTION WITH THE BAM (MASK) BITS IN THE DCMR. COMPARED WITH BUS ADDRESS & MASK TO DETERMINE DRAM HIT OR MISS.

RE REFRESH ENABLE (1 = Refresh associated DRAM bank 0 = Do not Refresh associated DRAM bank)

CASL COLUMN ADDRESS STROBE LATENCY. DETERMINES HOW LONG THE DATA IS DELAYED AFTER THE CAS SIGNAL IS ASSERTED. THIS CORRESPONDS TO THE tRCD SPECIFICATION. THIS ALSO IMPLIES OTHER TIMINGS, INCLUDING tRAS, tRP, tRWL, & tEP.

CBM COMMAND & BANK MUX. SINCE DIFFERENT DRAM CONFIGURATIONS WILL CAUSE THE BANK & COLUMN BITS TO CORRESPOND TO DIFFERENT ADDRESSES, THESE BITS DETERMINE WHICH ADDRESS BITS THESE FUNCTIONS WILL BE MULTIPLEXED TO.

PS PORT SIZE (00 = 32-bit port; 01 = 8-bit port; 10 =16-bit port; 11 =16-bit port)

PM PAGE MODE (0 =Page mode or bursts only; 1= Continuous page mode)

ACR0[31:0] & ACR1[31:0] -ADDRESS & CONTROL REGISTERS

RST: - - - - - - - - - - - - - - - -

BA [31:18] - -B31.............................................................................................................................B18 B17 B16

RE - CASL - CBM - IMRS PS1 PS0 - PM - -


RST: 0 - - - - - - - 0 0 - - - - - 0



MCF5307 DRAM CONTROLLER MASK REGISTERS: SYNC MODE

BAM BASE ADDRESS MASK. (0 =Associated address bit is compared in DRAM hit; 0 =Associated address bit is ignored in DRAM hit)

WP WRITE PROTECT. (0 =Allow write accesses; 1 =Ignore write accesses)

ADDRESS MODIFIER MASKS: (0 =Allow associated access type; 1 =Ignore associated access type)

C/I CPU SPACE/ INTERRUPT ACKNOWLEDGE)

AM ALTERNATE MASTER

SC SUPERVISOR CODE

SD SUPERVISOR DATA

UC USER CODE

UD USER DATA

V VALID BIT ENCODING 0 = DRAM Accesses not decoded; 1 = DRAM Accesses decoded)

DCMR0[31:0] & DCMR BASE[31:0] -DRAM CONTROLLER MASK REGISTERS

RST: - - - - - - - - - - - - - - - -

BAM - -B31.............................................................................................................................B18 B17 B16

RESERVED WP - C/I AM SC SD UC UD V


RST: - - - - - - - - - - - - - - - -

▼ When DCR[SO]=1, this register is defined as follows: ▼ This register is defined the same in Asynchronous & Synchronous modes


POWER ON SEQUENCE

▼ Synchronous DRAMs have a prescribed power on sequence. The 5307 DRAM Controller supports this sequence by using the following procedure:

◆ Synchronous DRAM control signals are reset to the idle state. Firmware should wait the prescribed period before taking any action on the SDRAMs.

◆ Firmware should now: - Set up the DCR, ACR, & DCMR registers in their operational

configuration. Do not yet enable refresh commands.

- Issue the PALL command to the SDRAMs by setting the associated bit in the DCR.- Enable refresh & wait a period long enough for at least 8 refreshed to take place.- Issue the MRS command by setting the IMRS bit in the ACRs.


MODE REGISTER SET (MRS) COMMAND

CLOCK

ADDR

TS

RAS

CAS

DRAMR/W

DATA

CS

MRS

▼ The DRAM Controller can configure SDRAMs with the MRS command.▼ The MRS command is used to set burst operation & CAS latency of 1, 2 or 3.▼ The MRS command should set burst operation to a burst length of 1, or no

burst. Addresses are incremented internally to the DRAM controller to allow fast accesses. Transfer size is 1, 2, 4 or 16 bytes.

▼ SDRAM mode register is written by: setting the base address & mask registers & the associated CBM bits, & setting ACR[IMRS].


BURST PAGE MODE

▼ The advantage of synchronous DRAMs is the speed of data transfer once a page is opened.

▼ Once CAS has been issued the SDRAM will accept a new address & CAS every clock for accesses on that page.

▼ In burst page mode, if the transfer size is greater than the port size of the SDRAM, there will be multiple read or write operations for every ACTV command.

▼ As soon as the transfer is completed, the PALL command is generated to prepare for the next access.

▼ Synchronous Burst Page Mode accesses always follow this sequence:

◆ ACTV command

◆ NOP commands to ensure RAS to CAS delay◆ Read or Write commands

◆ Sometimes NOPs are required here to ensure the ACTV to Precharge delay

◆ PALL command

◆ Required number of idle clocks to ensure Precharge to ACTV delay


BURST READ SDRAM ACCESS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19CLOCK

ADDR

TS

RAS

CAS

DRAMR/W

DATA

CommandAddress

CS

DQM

CAS Latency=2

ACTV NOP READ PALL


BURST WRITE SDRAM ACCESS

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19CLOCK

ADDR

TS

RAS

CAS

DRAMR/W

DATA

CommandAddress

CS

DQM

CAS Latency=2

ACTV NOP WRITE PALL


CONTINUOUS PAGE MODE

▼ Continuous Page Mode is a variation in page mode which tries to balance performance complexity and size.

▼ With the internal pipelined bus of the Core, the DRAM Controller will predict whether the next bus cycle will hit in the same SDRAM:

◆ If the next bus cycle is not pending or misses in the page, the PALL command is generated to the SDRAM. This allow the precharge to be hidden in the current cycle.

◆ If the next bus cycle is pending and hits in the page, the page is left open & the next SDRAM access will begin with a read or write command.


SYNCHRONOUS CONTINUOS PAGE MODE ACCESS-READ FOLLOWED BY READ

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19CLOCK

ADDR

TS

RAS

CAS

DRAMR/W

DATA

CommandAddress

CS

DQM

CAS Latency=2

ACTV NOP READ NOP READ PALL

▼ Note there is no precharge between the 2 accesses.▼ Also note the 2nd cycle begins with a read operation with no ACTV command.


SYNCHRONOUS CONTINUOS PAGE MODE ACCESS-WRITE FOLLOWED BY READ

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19CLOCK

ADDR

TS

RAS

CAS

DRAMR/W

DATA

CommandAddress

CS

DQM

CAS Latency=2

ACTV NOP WRITE NOP READ PALL

▼ Note that the 2nd cycle begins sooner after a write than after a read, since a read requires data to be returned before the bus cycle is terminated.

▼ In Continuous page mode, 2nd accesses will present multiplexed addresses.


AUTO-REFRESH OPERATION

▼ The DRAM Controller provides timing & control to refresh the SDRAM.▼ If the refresh counter is set & refresh is enabled, the counter counts down to zero,

an internal refresh request flag is set & the counter is reloaded & begins counting down again.

▼ When the refresh request flag is set, the DRAM Controller completes any active burst operation & then performs a precharge all operation, initiates a refresh cycle & clears the refresh request flag.


AUTO-REFRESH OPERATION0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19CLOCK

ADDR

TS

RAS

CAS

DRAMR/W

CommandAddress

CS

CAS Latency=2

PALL DESL REF DESL ACTV

▼ The request is delayed by the precharge to ACTV delay programmed into the active SDRAM bank by the CAS bits.

▼ The REF command is then generated & the delay required by the DCR[RTIM] is inserted before the next ACTV command.


SELF REFRESH OPERATION

CLOCK

RAS

CAS

DRAMR/W

CommandAddress

CS

CKE

PALL DESL SELF Self SELFX DESL FirstRefresh Possible Active ACTV

CAS Latency=2

TRC= 6

▼ Self-refresh is a method of allowing the SDRAM to enter a low power state & at the same time doing an internal refresh operation & maintaining the integrity of SDRAM data.

▼ The DCR[IS] bit turns on the Self-refresh operation.

mcf5307 dram ctrl - nxp semiconductors · • ras[1:0] - row address strobe - used to select 1 of 2...

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