mcp47cxbxx data sheet - microchip technology...mcp47cxbxx ds20006089b-page 2 2018-2019 microchip...

MCP47CXBXX81012-Bit Digital-to-Analog Converters 1 LSb INL

SingleDual Voltage Outputs with I2C Interface

Features

bull Memory Options

- Volatile Memory MCP47CVBXX

- Nonvolatile Memory MCP47CMBXX

bull Operating Voltage Range

- 27V to 55V ndash Full specifications

- 18V to 27V ndash Reduced device specifications

bull Output Voltage Resolutions

- 8-bit MCP47CXB0X (256 steps)



bull Nonvolatile Memory (MTP) Size 32 Locations

bull 1 LSb Integral Nonlinearity (INL) Specification

bull DAC Voltage Reference Source Options

- Device VDD

- External VREF pin (buffered or unbuffered)

- Internal band gap (1214V typical)

bull Output Gain Options

- 1x (Unity)

- 2x (available when not using internal VDD as voltage source)

bull Power-onBrown-out Reset (PORBOR) Protection

bull Power-Down Modes

- Disconnects output buffer (high-impedance)

- Selection of VOUT pull-down resistors (100 k or 1 k)

bull I2C Interface

- Slave address options register-defined address with two physical address select pins (package dependent)

- Standard (100 kbps) Fast (400 kbps) and High-Speed (up to 34 Mbps) modes

bull Package Types

- Dual 16-lead 3 x 3 QFN 10-lead MSOP10-lead 3 x 3 DFN

- Single 16-lead 3 x 3 QFN 10-lead MSOP10-lead 3 x 3 DFN

bull Extended Temperature Range -40degC to +125degC

Package Types

MCP47CXBX1 (Single)

VREF

A0

VOUT

SCL

LATHVC

1

VSS

SDAVDD

MCP47CXBX2 (Dual)

NC

A1

2

3

4

5

10

9

8

7

6

VREF

A0

VOUT

SCL

LATHVC

1

VSS

SD

A

VD

DN

C

A12

3

4

5 6 7 8

12

11

10

9

16

15

14

13

17 EP(1)

NC

NC

NC

NC

NC

NC

QFN-16 (3x3)

VREF

A0

VOUT0

SCL

LATHVC(2)

1

VSS

SDAVDD

VOUT1

A1

2

3

4

5

10

9

8

7

6

VREF0

A0

VOUT0

SCL

LAT0HVC

1

VSS

SD

A

VD

DV

OU

T1

A12

3

4

5 6 7 8

12

11

10

9

16

15

14

13

17 EP(1)

NC

NC

LA

T1

NC

NC

VREF1

MSOP-10 DFN-10 (3x3)

QFN-16 (3x3)

MSOP-10 DFN-10 (3x3)

Note 1 Exposed pad (substrate paddle)2 This pinrsquos signal can be connected to DAC0

andor DAC1

2018-2019 Microchip Technology Inc DS20006089B-page 1

MCP47CXBXX

General Description

The MCP47CXBXX devices are single and dualchannel 8-bit 10-bit and 12-bit buffered voltage outputDigital-to-Analog Converters (DAC) with volatile orMTP memory and an I2C serial interface

The MTP memory can be written by the user up to32 times for each specific register It requires a high-voltage level on the HVC pin typically 75V in order tosuccessfully program the desired memory locationThe nonvolatile memory includes power-up outputvalues device Configuration registers and generalpurpose memory

The VREF pin the device VDD or the internal band gapvoltage can be selected as the DACrsquos referencevoltage When VDD is selected VDD is internallyconnected to the DAC reference circuit

When the VREF pin is used with an external voltagereference the user can select between a gain of 1 or 2and can have the reference buffer enabled or disabledWhen the gain is 2 the VREF pin voltage should belimited to a maximum of VDD2

These devices have a two-wire I2C compatible serialinterface for Standard (100 kHz) Fast (400 kHz) orHigh-Speed (17 MHz and 34 MHz) modes

Applications

bull Set Point or Offset Trimming

bull Sensor Calibration

bull Low-Power Portable Instrumentation

bull PC Peripherals

bull Data Acquisition Systems

MCP47CMBX1 Block Diagram (Single-Channel Output)

VDD

VSS

Memory

SDA

SCL

VREF1VREF0

A0

A1

VOUT0

10

0k

1k

VDD PD1PD0

VREF1VREF0

OP AMP

ADDR6ADDR0

PD1PD0 and VREF1VREF0

DAC0VREFPOWER-DOWNGAINSTATUS

DAC0VREFPOWER-DOWNGAINI2C ADDRESSWiperLocktrade

VOLATILE (4x16)

NONVOLATILE (13x16)

Band Gap1214V

VDD

VIHH

LAT0

VBG

LATHVC

VREF0

Power-upBrown-out Control

I2C Serial Interface Moduleand Control Logic

(WiperLocktrade Technology)

Res

isto

rL

add

er

GAIN

DS20006089B-page 2 2018-2019 Microchip Technology Inc

MCP47CXBXX

MCP47CMBX2 Block Diagram (Dual Channel Output)

VDD

VSS

Memory

VREF0(2)

SDA

SCL

VREF1VREF0

Note 1 On dual output devices except those in a QFN16 package the LAT0 pin is internally connected to LAT1 input of DAC1

2 On dual output devices except those in a QFN16 package the VREF0 pin is internally connected to VREF1 input of DAC1

A0

A1

Res

isto

rL

add

er

VOUT0

10

0k

1k

VDD

LAT0HVC

PD1PD0

VREF1VREF0

OP AMP

ADDR6ADDR0

PD1PD0 andVREF1VREF0

DAC0 and DAC1VREFPOWER-DOWNGAINSTATUS

DAC0 and DAC1VREFPOWER-DOWNGAINI2C ADDRESSWiperLocktrade

VOLATILE (5x16)

NONVOLATILE (14x16)

Band Gap1214V

VDD

GAIN

VREF1(2)

VREF1VREF0

Re

sist

or

Lad

der

VOUT1

100

k

1k

VDD

LAT1(1)

PD1PD0

VREF1VREF0

OP AMP


VDD

GAIN

VIHH

LAT0

LAT0(1)

VBG

VBG





MCP47CXBXX

Family Device Features

Device Package Type

o

f C

ha

nn

els

Re

so

luti

on

(b

its)

DAC Output PORBOR Setting(1)

o

f V

RE

F I

np

uts

o

f L

AT

In

pu

ts(3

)

o

f A

dd

ress

Pin

s

Me

mo

ry(2

)

GP

MT

P L

oca

tio

ns

MCP47CVB01 MSOP QFN DFN 1 8 7Fh 1 1 2 RAM mdash

MCP47CVB11 MSOP QFN DFN 1 10 1FFh 1 1 2 RAM mdash


MCP47CVB02QFN 2 8 7Fh 2 2 2 RAM mdash

MSOP DFN 2 8 7Fh 1 1 2 RAM mdash

MCP47CVB12QFN 2 10 1FFh 2 2 2 RAM mdash

MSOP DFN 2 10 1FFh 1 1 2 RAM mdash



MCP47CMB01 MSOP QFN DFN 1 8 7Fh 1 1 2 MTP 8

MCP47CMB11 MSOP QFN DFN 1 10 1FFh 1 1 2 MTP 8


MCP47CMB02QFN 2 8 7Fh 2 2 2 MTP 8

MSOP DFN 2 8 7Fh 1 1 2 MTP 8

MCP47CMB12QFN 2 10 1FFh 2 2 2 MTP 8

MSOP DFN 2 10 1FFh 1 1 2 MTP 8



Note 1 The factory default value

2 Each nonvolatile memory location can be written 32 times For subsequent writes to the MTP the device will ignore the commands and the memory will not be modified

3 If the product is a dual device and the package has only one LAT pin it is associated with both DAC0 and DAC1


MCP47CXBXX

10 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings(dagger)

Voltage on VDD with respect to VSS -06V to +65V

Voltage on all pins with respect to VSS -06V to VDD + 03V

Input clamp current IIK (VI lt 0 VI gt VDD VI gt VPP on HV pins) plusmn20 mA

Output clamp current IOK (VO lt 0 or VO gt VDD)plusmn20 mA

Maximum current out of VSS pin (Single) 50 mA(Dual)100 mA

Maximum current into VDD pin (Single) 50 mA(Dual)100 mA

Maximum current sourced by the VOUT pin 20 mA

Maximum current sunk by the VOUT pin20 mA

Maximum current sourcesunk by the VREF(0) pin (in Band Gap mode) 20 mA

Maximum current sunk by the VREFx pin (when VREF is in Unbuffered mode) 175 microA

Maximum current sourced by the VREFx pin 20 microA

Maximum current sunk by the VREF pin 125 microA

Maximum input current sourcesunk by SDA SCL pins 2 mA

Maximum output current sunk by SDA output pin 25 mA

Total power dissipation(1) 400 mW

ESD protection on all pins plusmn6 kV (HBM)plusmn400V (MM)plusmn2 kV (CDM)

Latch-up (per JEDEC JESD78A) at +125degC plusmn100 mA

Storage temperature -65degC to +150degC

Ambient temperature with power applied -55degC to +125degC

Soldering temperature of leads (10 seconds) +300degC

Maximum Junction Temperature (TJ) +150degC

Note 1 Power dissipation is calculated as follows PDIS = VDD x IDD ndash IOH + (VDD ndash VOH) x IOH + (VOL x IOL)

dagger Notice Stresses above those listed under ldquoMaximum Ratingsrdquo may cause permanent damage to the device This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied Exposure to maximum rating conditions for extended periods may affect device reliability


MCP47CXBXX

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC TA +125degC (Extended) All parameters apply across the specified operating ranges unless notedVDD = +27V to 55V VREF = +1000V to VDD VSS = 0V RL = 2 k from VOUT to GND CL = 100 pF Typical specifications represent values for VDD = 55V TA = +25degC

Parameters Sym Min Typ Max Units Conditions

Supply Voltage VDD 27 mdash 55 V

18 mdash 27 V DAC operation (reduced analog specifications) and serial interface

VDD Voltage (rising) to Ensure Device Power-on Reset

VPOR mdash mdash 175 V RAM retention voltage (VRAM) lt VPORVDD voltages greater than the VPOR limit ensure that the device is out of Reset

VDD Voltage (falling) to Ensure Device Brown-out Reset

VBOR VRAM mdash 161 V RAM retention voltage (VRAM) lt VBOR

VDD Rise Rate to Ensure Power-on Reset

VDDRR Note 3 Vms

Power-on Reset to Output-Driven Delay(2)

TPOR2OD mdash mdash 130 micros VDD rising VDD gt VPOR single output

mdash mdash 145 micros VDD rising VDD gt VPOR dual output

Note 2 This parameter is ensured by characterization

Note 3 PORBOR voltage trip point is not slope-dependent Hysteresis implemented with time delay


MCP47CXBXX

DC CHARACTERISTICS (CONTINUED)



Supply Current IDD mdash mdash 230 microA Single 100 kHz(2) Serial interface active VRxBVRxA = 10(4) VOUT is unloaded VREF = VDD = 55VVolatile DAC register = Mid-Scale

mdash mdash 310 400 kHz

mdash mdash 460 17 MHz(2)


mdash mdash 330 Dual 100 kHz(2)




mdash mdash 160 Single Serial interface inactive VRxBVRxA = 10VOUT is unloaded VREF = VDD = 55VVolatile DAC register = Mid-Scale

mdash mdash 280 Dual

LATHVC Pin Write Current(2)

IDD(MTP_WR) mdash mdash 640 mA mdash Serial interface inactive (MTP write active)VRxBVRxA = 10 (valid for all modes)VDD = 55V LATHVC = VIHH write all lsquo1rsquos to nonvolatile DAC0VOUT pins are unloaded

Power-Down Current

IDDP mdash 065 380 microA mdash PDxBPDxA = 01(5) VRxBVRxA = 10VOUT not connected


Note 4 Supply current is independent of current through the resistor ladder in mode VRxBVRxA = 10

Note 5 The PDxBPDxA = 01 10 and 11 configurations should have the same current


MCP47CXBXX




Resistor Ladder Resistance(6)

RL 639 71 781 k VRxBVRxA = 10VREF = VDD

Resolution ( of resistors and of taps) (see C1 ldquoResolutionrdquo)

N 256 Taps 8-bit No missing codes

1024 Taps 10-bit No missing codes


Nominal VOUT Match(10) |VOUT ndash VOUTMEAN|VOUTMEAN

mdash 0016 0300 18V VDD 55V(2)

VOUT Tempco(2) (see C19 ldquoVOUT Temperature Coefficientrdquo)

VOUTT mdash 3 mdash ppmdegC Code = Mid-Scale VRxBVRxA = 00 10 and 11

VREF Pin Input Voltage Range(1)

VREF VSS mdash VDD V 18V VDD 55V

Note 1 This parameter is ensured by design


Note 6 Resistance is defined as the resistance between the VREF pin (mode VRxBVRxA = 10) to the VSS pinFor dual channel devices (MCP47CXBX2) this is the effective resistance of each resistor ladder Theresistance measurement is one of the two resistor ladders measured in parallel

Note 10 Variation of one output voltage to mean output voltage for dual devices only


MCP47CXBXX




Zero-Scale Error(Code = 000h)(see C5 ldquoZero-Scale Error (EZS)rdquo)

EZS mdash mdash 0375 LSb 8-bit VRxBVRxA = 10 G = 0VREF = VDD no load

mdash mdash 15 LSb 10-bit VRxBVRxA = 10 G = 0VREF = VDD no load


See Section 20 ldquoTypical Performance Curvesrdquo(2)

LSb VRxBVRxA = 10 G = 1 VREF = 05 X VDD no load


LSb VRxBVRxA = 01 G = 0 G = 1VDD = 18V-55V no load

Offset Error (see C7 ldquoOffset Error (EOS)rdquo)

EOS -6 plusmn04 +6 mV VRxBVRxA = 10 Gx = 0 no load8-bit Code = 4 10-bit Code = 16 12-bit Code = 64

Offset Voltage Temperature Coefficient(29)

VOSTC mdash plusmn5 mdash microVdegC

Full-Scale Error (see C4 ldquoFull-Scale Error (EFS)rdquo)

EFS mdash mdash 25 LSb 8-bit VRxBVRxA = 10 G = 0 VREF = VDD no load

mdash mdash 9 LSb 10-bit VRxBVRxA = 10 G = 0 VREF = VDD no load






Gain Error (see C9 ldquoGain Error (EG)rdquo)(7)

EG -1 plusmn01 +1 of FSR

8-bitVRxBVRxA = 10 G = 0 Code = 252 VREF = VDD no load

-1 plusmn01 +1 of FSR




Gain Error Drift(29) (see C10 ldquoGain Error Drift (EGD)rdquo)

GdegC mdash -6 mdash ppmdegC


Note 7 This gain error does not include the offset error

Note 9 Code range dependent on resolution 8-bit codes 4 to 252 10-bit codes 16 to 1008 12-bit codes 64 to4032


MCP47CXBXX




Total Unadjusted Error(29) (see C6 ldquoTotal Unadjusted Error (ET)rdquo)

ET -25 mdash 075 LSb 8-bit VRxBVRxA = 10 G = 0 VREF = VDD no load

-9 mdash 3 LSb 10-bit VRxBVRxA = 10 G = 0 VREF = VDD no load






Integral Nonlinearity (see C11 ldquoIntegral Nonlinearity (INL)rdquo)(9)

INL -01 mdash +01 LSb 8-bit VRxBVRxA = 10 G = 0 VREF = VDD no load

-025 mdash +025 LSb 10-bit VRxBVRxA = 10 G = 0 VREF = VDD no load






Differential Nonlinearity (see C12 ldquoDifferential Nonlinearity (DNL)rdquo)(9)

DNL -01 mdash +01 LSb 8-bit VRxBVRxA = 10 G = 0 VREF = VDD no load










MCP47CXBXX




-3 dB Bandwidth (see C16 ldquo-3 dB Bandwidthrdquo)

BW mdash 60 mdash kHz VREF = 300V plusmn 2V VRxBVRxA = 10 Gx = 0mdash 35 mdash VREF = 350V plusmn 15V VRxBVRxA = 10

Gx = 1Output Amplifier (Op Amp)

Phase Margin(1) PM mdash 58 mdash degC RL = infin

Slew Rate SR mdash 015 mdash Vmicros RL = 2 k

Load Regulation mdash mdash 130 mdash microVmA 1 mA I mA VDD = 55VDAC code = Mid-Scalemdash 320 mdash microVmA -6 mA I-1 mA

Short-Circuit Current ISC_OA 6 10 14 mA Short to VSS DAC code = Full Scale

6 10 14 mA Short to VDD DAC code = Zero Scale

Settling Time(8) tSETTLING mdash 16 mdash micros RL = 2 k

Internal Band Gap

Band Gap Voltage VBG 1180 1214 1260 V 18V VDD 55V

Short-Circuit Current ISC_BG 6 10 14 mA Short to VSS

6 10 14 mA Short to VDD

Band Gap Voltage Temperature Coefficient

VBGTC mdash 16 mdash ppmdegC 18V VDD 55V

Band Gap mode VREF Pin Load Regulation

IBG mdash 30 mdash microVmA 1 mA I6 mA VDD = 55V

mdash 390 mdash microVmA -6 mA I-1 mA


Note 8 Within 12 LSb of the final value when code changes from 14 to 34 of FSR (Example 400h to C00h in 12-bit device)


MCP47CXBXX




External Reference (VREF)

Input Range(1) VREF VSS mdash VDD V VRxBVRxA = 10 (Unbuffered mode)

Input Capacitance CREF mdash 29 mdash pF VRxBVRxA = 10(Unbuffered mode)

Input Impedance RL See Resistor Ladder Resistance(6)

k 27V VDD 55VVRxBVRxA = 10 VREF VDD

Current through VREF(1) IVREF mdash mdash 17215 microA Mathematically from RVREF(min)

spec (at 55V)

Total Harmonic Distortion(1)

THD mdash -76 mdash dB VREF = 2048V plusmn 01V VRxBVRxA = 10 Gx = 0 Frequency = 1 kHz

Dynamic Performance

Major Code Transition Glitch (see C14 ldquoMajor Code Transition Glitchrdquo)

mdash mdash 10 mdash nV-s 1 LSb change around major carry (7FFh to 800h)

Digital Feedthrough (see C15 ldquoDigital Feedthroughrdquo)

mdash mdash lt2 mdash nV-s




MCP47CXBXX




Digital InputsOutputs (LAT0HVC LAT1 A0 A1)

Schmitt Trigger High Input Threshold

VIH 045 VDD mdash mdash V 18V VDD 55V (allows 27V digital VDD with 55V analog VDD or 18V digital VDD with 30V analog VDD)

Schmitt Trigger Low Input Threshold

VIL mdash mdash 02 VDD V

Hysteresis of Schmitt Trigger Inputs

VHYS mdash 01 VDD mdash V

Input Leakage Current IIL -1 mdash 1 microA VIN = VDD and VIN = VSS

Pin Capacitance CIN COUT mdash 10 mdash pF

Digital Interface (SDA SCL)

Output Low Voltage VOL mdash mdash 04 V VDD 20V IOL = 3 mA

mdash mdash 02 VDD V VDD lt 20V IOL = 1 mA

Input High Voltage (SDA and SCL pins)

VIH 07 VDD mdash mdash V 18V VDD 55V

Input Low Voltage (SDA and SCL pins)

VIL mdash mdash 03 VDD V 18V VDD 55V

Input Leakage IL -1 mdash 1 microA SCL = SDA = VSS or SCL = SDA = VDD

Pin Capacitance CPIN mdash 10 mdash pF

RAM Value

Value Range N 0h mdash FFh Hex 8-bit

mdash 3FFh 10-bit

mdash FFFh 12-bit

DAC Register PORBOR Value

N See Table 4-2 Hex 8-bit

10-bit

12-bit

PDCON Initial Factory Setting

mdash See Table 4-2 Hex

Power Requirements

Power Supply Sensitivity (C17 ldquoPower Supply Sensitivity (PSS)rdquo)

PSS mdash 00010 00035 8-bit Code = Mid-Scale

mdash 10-bit

mdash 12-bit


MCP47CXBXX




Multi-Time Programming Memory (MTP)

MTP Programming Voltage(1)

VPG_MTP 20 mdash 55 V HVC = VIHH -20degC TA +125degC

LATHVC Pin Voltage for MTP Programming (high-voltage commands)

VIHH 725 75 775V V The LATHVC pin will be at one of the three input levels (VIL VIH or VIHH)(111)

the LATHVC pin must supply the required MTP programming current (up to 64 mA)

Writes Cycles mdash mdash mdash 32(12) Cycles Note 1

Data Retention DRMTP 10 mdash mdash Years At +85degC(1)

MTP Range N 0h mdash FFh Hex 8-bit

0h mdash 3FFh Hex 10-bit

0h mdash FFFh Hex 12-bit

0000h 7FFFh Hex All general purpose memory

Initial Factory Setting N See Table 4-2 mdash

MTP Programming Write Cycle Time(1)

tWC(MTP) mdash mdash 250 micros VDD = +20V to 55V -20degC TA +125degC


Note 11 High-voltage on the LATHVC pin must be limited to the command + programming time After the programming cycle the LATHVC pin voltage must be returned to 55V or lower

Note 12 After 32 MTP write cycles writes are inhibited and the 32nd write value is retained (not corrupted)


MCP47CXBXX

DC Notes

1 This parameter is ensured by design

2 This parameter is ensured by characterization

3 PORBOR voltage trip point is not slope-dependent Hysteresis implemented with time delay

4 Supply current is independent of current through the resistor ladder in mode VRxBVRxA = 10

5 The PDxBPDxA = 01 10 and 11 configurations should have the same current

6 Resistance is defined as the resistance between the VREF pin (mode VRxBVRxA = 10) to the VSS pin For dual channel devices (MCP47CXBX2) this is the effective resistance of each resistor ladder The resistance measurement is one of the two resistor ladders measured in parallel

7 This gain error does not include the offset error

8 Within 12 LSb of the final value when code changes from 14 to 34 of FSR (Example 400h to C00h in 12-bit device)

9 Code range dependent on resolution 8-bit codes 4 to 252 10-bit codes 16 to 1008 12-bit codes 64 to 4032

10 Variation of one output voltage to mean output voltage for dual devices only

11 High-voltage on the LATHVC pin must be limited to the command + programming time After the programming cycle the LATHVC pin voltage must be returned to 55V or lower

12 After 32 MTP write cycles writes are inhibited and the 32nd write value is retained (not corrupted)


MCP47CXBXX

11 Timing Waveforms and Requirements

111 WIPER SETTLING TIME

FIGURE 1-1 VOUT Settling Time Waveforms

112 LATCH PIN (LAT) TIMING

FIGURE 1-2 LAT Pin Waveforms

VOUT

plusmn 05 LSb

Old Value

New Value

TABLE 1-1 WIPER SETTLING TIMING

Timing Characteristics

Standard Operating Conditions (unless otherwise specified)Operating Temperature -40degC TA +125degC (Extended)

All parameters apply across the specified operating ranges unless notedVDD = +27V to 55V VSS = 0V RL = 2 k from VOUT to GND CL = 100 pF Typical specifications represent values for VDD = 55V TA = +25degC


VOUT Settling Time (see C13 ldquoSettling Timerdquo)

tS mdash 16 mdash micros 12-bit Code = 400h C00h C00h 400h(2)

Note 2 Within 12 LSb of final value when code changes from 14 to 34 of FSR

LATx

SCL

tLAT

Wx

TABLE 1-2 LAT PIN TIMING



All parameters apply across the specified operating ranges unless noted VDD = +27V to 55V VSS = 0V RL = 2 k from VOUT to GND CL = 100 pF Typical specifications represent values for VDD = 55V TA = +25degC


LATx pin pulse width tLAT 20 mdash mdash ns


MCP47CXBXX

12 I2C Mode Timing Waveforms and Requirements

FIGURE 1-3 Power-on and Brown-out Reset Waveforms

FIGURE 1-4 I2C Power-Down Command Timing

VDD

tBORD

VOUT

VBOR

VOUT at High-Z

SPI Interface is Operational

VPOR

tPOR2SIA = tPOR2OD

SDA

SCL

ACK Stop Start ACK

VOUT

tPDD tPDE

TABLE 1-3 RESET TIMING





Power-on Reset Delay(1) tPOR2SIA mdash mdash 130 micros Single Monitor ACK bit response to ensure the device responds to commandmdash mdash 145 Dual

Brown-out Reset Delay tBORD mdash 30 mdash micros VDD transitions from VDD(MIN) gt VPOR VOUT driven to VOUT disabled

Power-Down Output Enable Time Delay

TPDE mdash 15 mdash micros PDxBPDxA = 11 10 or 01 00 started from the rising edge of the SCL at the end of the 8th clock cycle Volatile DAC register = FFFh VOUT = 10 mV VOUT not connected

Power-Down Output Disable Time Delay

TPDD mdash 0025 mdash micros PDxBPDxA = 00 11 10 or 01 started from the rising edge of the SCL at the end of the 8th clock cycle VOUT = VOUT ndash 10 mVVOUT not connected

Note 1 Not tested This parameter is ensured by characterization


MCP47CXBXX

FIGURE 1-5 I2C Bus StartStop Bits and HVC Timing Waveforms

SCL

SDA

StartCondition

StopCondition

VIH

111

VIL

VIH VIHH

VIHHVC94

Note 1 The HVC pin must be at VIHH until the MTP write cycle is complete

9091 93

92


MCP47CXBXX

TABLE 1-4 I2C BUS STARTSTOP BITS AND LAT REQUIREMENTS

I2C AC CharacteristicsStandard Operating Conditions (unless otherwise specified)Operating Temperature -40C TA +125C (Extended) The operating voltage range is described in DC Characteristics

Param No

Sym Characteristic Min Max Units Conditions

mdash FSCL SCL Pin Frequency Standard mode 0 100 kHz Cb = 400 pF 18V-55V(1)

Fast mode 0 400 kHz Cb = 400 pF 27V-55V

High Speed 17 0 17 MHz Cb = 400 pF 45V-55V(1)


90 TSUSTA Start Condition Setup Time(only relevant for Repeated Start condition)

100 kHz mode 4700 mdash ns Note 1

400 kHz mode 600 mdash ns

17 MHz mode 160 mdash ns Note 1

34 MHz mode 160 mdash ns

91 THDSTA Start ConditionHold Time(after this period the first clock pulse is generated)





92 TSUSTO Stop ConditionSetup Time





93 THDSTO Stop ConditionHold Time





94 THVCSU HVC High to Start Condition(setup time)

0 mdash micros Not tested specification ensured by Master



MCP47CXBXX

FIGURE 1-6 I2C Bus Data Timing Waveforms

TABLE 1-5 I2C BUS REQUIREMENTS (SLAVE MODE)


Param No


100 THIGH Clock High Time 100 kHz mode 4000 mdash ns 18V-55V(1)

400 kHz mode 600 mdash ns 27V-55V

17 MHz mode 120 mdash ns 45V-55V(1)


101 TLOW Clock Low Time 100 kHz mode 4700 mdash ns 18V-55V(1)




102A(10) TRSCL SCL Rise Time 100 kHz mode mdash 1000 ns Cb is specified to be from 10 to 400 pF (100 pF maximum for 34 MHz mode)

400 kHz mode 20 + 01Cb(4) 300 ns

17 MHz mode 20 80 ns

17 MHz mode 20 160 ns After a Repeated Start condition or an Acknowledge bit



102B(10) TRSDA SDA Rise Time 100 kHz mode mdash 1000 ns Cb is specified to be from 10 to 400 pF (100 pF maximum for 34 MHz mode)

400 kHz mode 20 + 01Cb 300 ns



103A(10) TFSCL SCL Fall Time 100 kHz mode mdash 300 ns Cb is specified to be from 10 to 400 pF (100 pF maximum for 34 MHz mode)(4)

400 kHz mode 20 + 01Cb 300 ns




Note 4 Use Cb in pF for the calculations

Note 10 Not tested This parameter is ensured by design

9091 92

100101

103

106107

109 109 110

102

SCL

SDA In

SDA Out


MCP47CXBXX

TABLE 1-5 I2C BUS REQUIREMENTS (SLAVE MODE) (CONTINUED)


Param No


103B(10) TFSDA SDA Fall Time 100 kHz mode mdash 300 ns Cb is specified to be from 10 to 400 pF (100 pF maximum for 34 MHz mode)(4)

400 kHz mode 20 + 01Cb 300 ns



106 THDDAT Data Input Hold Time

100 kHz mode 0 mdash ns 18V-55V(15)




107 TSUDAT Data Input Setup Time

100 kHz mode 250 mdash ns Notes 1 6


17 MHz mode 10 mdash ns Notes 1 6


109 TAA Output Valid from Clock

100 kHz mode mdash 3450 ns Notes 1 5 7 9

400 kHz mode mdash 900 ns Notes 5 7 9

17 MHz mode mdash 310 ns Cb = 400 pF(19)


110 TBUF Bus Free Time 100 kHz mode 4700 mdash ns Time the bus must be free before a new transmission can start(1)


17 MHz mode NA mdash ns


111 TSP Input Filter Spike Suppression (SDA and SCL)

100 kHz mode mdash 50 ns NXP Spec states NA(1)

400 kHz mode mdash 50 ns NXP Spec states NA

17 MHz mode mdash 10 ns NXP Spec states NA(1)




Note 5 A Master transmitter must provide a delay to ensure that the difference between SDA and SCL fall times doesnot unintentionally create a Start or Stop condition

Note 6 A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system but therequirement tSUDAT 250 ns must then be met This will automatically be the case if the device does notstretch the Low period of the SCL signal If such a device does stretch the Low period of the SCL signal itmust output the next data bit to the SDA line TR max+ tSUDAT = 1000 + 250 = 1250 ns (according to theStandard mode I2C bus specification) before the SCL line is released

Note 7 As a transmitter the device must provide this internal minimum delay time to bridge the undefined region(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions

Note 8 Ensured by the TAA 34 MHz specification test

Note 9 The specification is not part of the I2C specification TAA = THDDAT + TFSDA (or TRSDA)



MCP47CXBXX

Timing Notes

1 Not tested This parameter is ensured by characterization

2 Within 12 LSb of final value when code changes from 14 to 34 of FSR

3 The transition of the LAT signal between 10 ns before the rising edge (Spec 94) and 250 ns after the rising edge (Spec 95) of the SCL signal is indeterminate whether the change in VOUT is delayed or not

4 Use Cb in pF for the calculations

5 A Master transmitter must provide a delay to ensure that the difference between SDA and SCL fall times does not unintentionally create a Start or Stop condition

6 A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system but the requirement tSUDAT 250 ns must then be met This will automatically be the case if the device does not stretch the Low period of the SCL signal If such a device does stretch the Low period of the SCL signal it must output the next data bit to the SDA line TR max+ tSUDAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released

7 As a transmitter the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions

8 Ensured by the TAA 34 MHz specification test

9 The specification is not part of the I2C specification TAA = THDDAT + TFSDA (or TRSDA)

10 Not tested This parameter is ensured by design


MCP47CXBXX

TEMPERATURE SPECIFICATIONS

Electrical Specifications Unless otherwise indicated VDD = +27V to +55V VSS = GND

Parameters Sym Min Typical Max Units Conditions

Temperature Ranges

Specified Temperature Range TA -40 mdash +125 degC

Operating Temperature Range TA -40 mdash +125 degC

Storage Temperature Range TA -65 mdash +150 degC

Thermal Package Resistances

Thermal Resistance 10L-MSOP JA mdash 206 mdash degCW

Thermal Resistance 10L-DFN (3x3) JA mdash 91 mdash degCW

Thermal Resistance 16L-QFN (3x3) JA mdash 58 mdash degCW


MCP47CXBXX

NOTES


MCP47CXBXX

20 TYPICAL PERFORMANCE CURVES

21 Electrical DataNote Unless otherwise indicated TA = +25degC VDD = 55V

FIGURE 2-1 Average Device Supply Current vs FSCL Frequency Voltage and Temperature ndash Active Interface VRxBVRxA = 00 (VDD Mode)

FIGURE 2-2 Average Device Supply Current vs FSCL Frequency Voltage and Temperature ndash Active Interface VRxBVRxA = 01 (Band Gap Mode)

FIGURE 2-3 Average Device Supply Current vs FSCL Frequency Voltage and Temperature ndash Active Interface VRxBVRxA = 11 (VREF Buffered Mode)

FIGURE 2-4 Average Device Supply Current ndash Inactive Interface (SCL = VIH or VIL) vs Voltage and Temperature VRxBVRxA = 00 (VDD Mode)

FIGURE 2-5 Average Device Supply Current ndash Inactive Interface (SCL = VIH or VIL) vs Voltage and Temperature VRxBVRxA = 01 (Band Gap Mode)

FIGURE 2-6 Average Device Supply Current ndash Inactive Interface (SCL = VIH or VIL) vs Voltage and Temperature VRxBVRxA = 11 (VREF Buffered Mode)

Note The graphs and tables provided following this note are a statistical summary based on a limited number ofsamples and are provided for informational purposes only The performance characteristics listed hereinare not tested or guaranteed In some graphs or tables the data presented may be outside the specifiedoperating range (eg outside specified power supply range) and therefore outside the warranted range


MCP47CXBXX

Note Unless otherwise indicated TA = +25degC VDD = 55V

FIGURE 2-7 Average Device Supply Current vs FSCL Frequency Voltage and Temperature ndash Active Interface VRxBVRxA = 10 (VREF Unbuffered Mode)

FIGURE 2-8 Average Device Supply Active Current (IDDA) (at 55V and FSCL = 34 MHz) vs Temperature and DAC Reference Voltage Mode

FIGURE 2-9 Average Device Supply Current ndash Inactive Interface (SCL = VIH or VIL) vs Voltage and Temperature VRxBVRxA = 10 (VREF Unbuffered Mode)


MCP47CXBXX

22 Linearity Data

221 TOTAL UNADJUSTED ERROR (TUE) ndash MCP47CXB2X (12-BIT) VREF = VDD (VRXBVRXA = 10) GAIN = 1x CODE 64-4032


FIGURE 2-10 Total Unadjusted Error (VOUT) vs DAC Code and Temperature (Single Channel ndash MCP47CXB21) VDD = 55V



FIGURE 2-13 Total Unadjusted Error (VOUT) vs DAC Code and Temperature (Dual Channel ndash MCP47CXB22) VDD = 55V




MCP47CXBXX

222 INTEGRAL NONLINEARITY (INL) ndash MCP47CXB2X (12-BIT) VREF = VDD (VRXBVRXA = 10) GAIN = 1x CODE 64-4032


FIGURE 2-16 INL Error vs DAC Code and Temperature (Single Channel ndash MCP47CXB21) VDD = 55V



FIGURE 2-19 INL Error vs DAC Code and Temperature (Dual Channel ndash MCP47CXB22) VDD = 55V

FIGURE 2-20 INL Error vs DAC Code and Temperature (Code 100-4000) (Dual Channel ndash MCP47CXB22) VDD = 27V



MCP47CXBXX

223 DIFFERENTIAL NONLINEARITY (DNL) ndash MCP47CXB2X (12-BIT) VREF = VDD (VRXBVRXA = 10) GAIN = 1x CODE 64-4032


FIGURE 2-22 DNL Error vs DAC Code and Temperature (Single Channel ndash MCP47CXB21) VDD = 55V



FIGURE 2-25 DNL Error vs DAC Code and Temperature (Dual Channel ndash MCP47CXB22) VDD = 55V




MCP47CXBXX

224 TOTAL UNADJUSTED ERROR (TUE) ndash MCP47CXB2X (12-BIT) EXTERNAL VREF = 05 VDD (VRXBVRXA = 10) UNBUFFERED CODE 64-4032


FIGURE 2-28 Total Unadjusted Error (VOUT) vs DAC Code and Temperature (Single Channel ndash MCP47CXB21) VREF = 05 x VDD = 275V Gain = 2x


FIGURE 2-30 Total Unadjusted Error (VOUT) vs DAC Code and Temperature (Dual Channel ndash MCP47CXB22) VREF = 05 x VDD = 275V Gain = 2x



MCP47CXBXX

225 INTEGRAL NONLINEARITY (INL) ndash MCP47CXB2X (12-BIT) EXTERNAL VREF = 05 VDD (VRXBVRXA = 10) UNBUFFERED CODE 64-4032


FIGURE 2-32 INL Error vs DAC Code and Temperature (Single Channel ndash MCP47CXB21) VREF = 05 x VDD = 275V Gain = 2x


FIGURE 2-34 INL Error vs DAC Code and Temperature (Dual Channel ndash MCP47CXB22) VREF = 05 x VDD = 275V Gain = 2x



MCP47CXBXX

226 DIFFERENTIAL NONLINEARITY ERROR (DNL) ndash MCP47CXB2X (12-BIT) EXTERNAL VREF = 05 VDD (VRXBVRXA = 10) UNBUFFERED CODE 64-4032


FIGURE 2-36 DNL Error vs DAC Code and Temperature (Single Channel ndash MCP47CXB21) VDD = 55V VREF = 05 x VDD = 275V


FIGURE 2-38 DNL Error vs DAC Code and Temperature (Dual Channel ndash MCP47CXB22) VDD = 55V VREF = 05 x VDD = 275V



MCP47CXBXX

227 TOTAL UNADJUSTED ERROR (TUE) ndash MCP47CXB2X (12-BIT) VREF = INTERNAL BAND GAP (VRXBVRXA = 01) CODE 64-4032


FIGURE 2-40 Total Unadjusted Error (VOUT) vs DAC Code and Temperature (Single Channel ndash MCP47CXB21) VDD = 55V Gain = 1x



FIGURE 2-43 Total Unadjusted Error (VOUT) vs DAC Code and Temperature (Dual Channel ndash MCP47CXB22) VDD = 55V Gain = 1x




MCP47CXBXX




FIGURE 2-48 Total Unadjusted Error (VOUT) vs DAC Code 25degC Gain = 1x





MCP47CXBXX


FIGURE 2-52 Total Unadjusted Error (VOUT) vs DAC Code +25degC Gain = 1x and 2x


MCP47CXBXX

228 INTEGRAL NONLINEARITY ERROR (INL) ndash MCP47CXB2X (12-BIT) VREF = INTERNAL BAND GAP (VRXBVRXA = 01) CODE 64-4032


FIGURE 2-53 INL Error vs DAC Code and Temperature (Single Channel ndash MCP47CXB21) VDD = 55V Gain = 1x



FIGURE 2-56 INL Error vs DAC Code and Temperature (Dual Channel ndash MCP47CXB22) VDD = 55V Gain = 1x




MCP47CXBXX




FIGURE 2-61 INL Error vs DAC Code +25degC Gain = 1x





MCP47CXBXX


FIGURE 2-65 INL Error vs DAC Code +25degC Gain = 1x and 2x


MCP47CXBXX

229 DIFFERENTIAL NONLINEARITY ERROR (DNL) ndash MCP47CXB2X (12-BIT) VREF = INTERNAL BAND GAP (VRXBVRXA = 01) CODE 64-4032


FIGURE 2-66 DNL Error vs DAC Code and Temperature (Single Channel ndash MCP47CXB21) VDD = 55V Gain = 1x



FIGURE 2-69 DNL Error vs DAC Code and Temperature (Dual Channel ndash MCP47CXB22) VDD = 55V Gain = 1x




MCP47CXBXX




FIGURE 2-74 DNL Error vs DAC Code +25degC Gain = 1x





MCP47CXBXX


FIGURE 2-78 DNL Error vs DAC Code +25degC Gain = 1x and 2x


MCP47CXBXX

NOTES


MCP47CXBXX

30 PIN DESCRIPTIONS

Overviews of the pin functions are provided inSection 31 ldquoPositive Power Supply Input (VDD)rdquothrough Section 39 ldquoNo Connect (NC)rdquo

The descriptions of the pins for the single DAC outputdevice are listed in Table 3-1 and descriptions for thedual DAC output device are listed in Table 3-2

TABLE 3-1 MCP47CXBX1 (SINGLE DAC) PIN FUNCTION TABLE

Pin

Symbol IOBuffer Type

DescriptionMSOP10L

DFN10L

QFN16L

1 1 16 VDD mdash P Supply Voltage Pin

2 2 1 A0 I ST I2C Slave Address Bit 0 Pin

3 3 2 VREF A Analog Voltage Reference InputOutput Pin

4 4 3 VOUT A Analog Buffered Analog Voltage Output Pin

5 5 456781415

NC mdash mdash Not Internally Connected

6 6 9 LATHVC I ST DAC Wiper Register LatchHigh-Voltage Command Pin

The Latch pin allows the value in the Volatile DAC registers (Wiper and Configuration bits) to be transferred to the DAC output (VOUT)

High-voltage commands allow the user MTP Configuration bits to be written

7 7 10 VSS mdash P Ground Reference Pin for all circuitries on the device


9 9 12 SCL I ST I2C Serial Clock Pin

10 10 13 SDA IO ST I2C Serial Data Pin

mdash mdash 17 EP mdash P Exposed Thermal Pad Pin must be connected to VSS

Note 1 A = Analog I = Input ST = Schmitt Trigger O = Output IO = InputOutput P = Power


MCP47CXBXX

TABLE 3-2 MCP47CXBX2 (DUAL DAC) PIN FUNCTION TABLE

Pin


DescriptionMSOP10L

DFN10L

QFN16L



3 3 mdash VREF A Analog Voltage Reference InputOutput Pin

mdash mdash 2 VREF0 A Analog Voltage Reference InputOutput Pin for DAC0


4 4 3 VOUT0 A Analog Buffered Analog Voltage Output 0 Pin


mdash mdash 671415


6 6 mdash LATHVC I ST DAC Wiper Register LatchHigh-Voltage Command Pin



mdash mdash 9 LAT0HVC I ST DAC0 Wiper Register LatchHigh-Voltage Command Pin

The Latch pin allows the value in the Volatile DAC0 registers (Wiper and Configuration bits) to be transferred to the DAC0 output (VOUT0)


mdash mdash 8 LAT1 I ST DAC1 Wiper Register Latch Pin








MCP47CXBXX

31 Positive Power Supply Input (VDD)

VDD is the positive supply voltage input pin The inputsupply voltage is relative to VSS

The power supply at the VDD pin should be as clean aspossible for good DAC performance It is recom-mended to use an appropriate bypass capacitor ofabout 01 microF (ceramic) to ground as close as possibleto the pin An additional 10 microF capacitor (tantalum) inparallel is also recommended to further attenuate noisepresent in application boards

32 Ground (VSS)

The VSS pin is the device ground reference

The user must connect the VSS pin to a ground planethrough a low-impedance connection If an analogground path is available in the application PCB (PrintedCircuit Board) it is highly recommended that the VSS

pin be tied to the analog ground path or isolated withinan analog ground plane of the circuit board

33 Voltage Reference Pin (VREF)

The VREF pin is either an input or an output When theDACrsquos voltage reference is configured as the VREF pinthe pin is an input When the DACrsquos voltage reference isconfigured as the internal band gap the pin is an output

When the DACrsquos voltage reference is configured as theVREF pin there are two options for this voltage inputVREF pin voltage is buffered or unbuffered Thebuffered option is offered in cases where the externalreference voltage does not have sufficient currentcapability to not drop its voltage when connected to theinternal resistor ladder circuit

When the DACrsquos voltage reference is configured as thedevice VDD the VREF pin is disconnected from theinternal circuit

When the DACrsquos voltage reference is configured as theinternal band gap the VREF pinrsquos drive capability isminimal so the output signal should be buffered

See Section 52 ldquoVoltage Reference Selectionrdquo andRegister 4-2 for more details on the Configuration bits

34 Analog Output Voltage Pins (VOUT0 VOUT1)

VOUT0 and VOUT1 are the DAC analog voltage outputpins Each DAC output has an output amplifier The DACoutput range is dependent on the selection of the voltagereference source (and potential output gain selection)These are

bull Device VDD ndash The Full-Scale Range (FSR) of the DAC output is from VSS to approximately VDD

bull VREF pin ndash The Full-Scale Range of the DAC output is from VSS to G x VRL where G is the gain selection option (1x or 2x)

bull Internal Band Gap ndash The Full-Scale Range of the DAC output is from VSS to G X VBG where G is the gain selection option (1x or 2x)

In Normal mode the DC impedance of the output pin isabout 1 In Power-Down mode the output pin isinternally connected to a known pull-down resistor of1 k 100 k or open The power-down selection bitssettings are shown in Register 4-3 (Table 5-5)

35 LatchHigh-Voltage Command Pin (LATHVC)

The DAC output value update event can be controlledand synchronized using the LAT pin for one or bothchannels on single or different devices

The LAT pin controls the effect of the Volatile Wiperregisters VRxBVRxA and PDxBPDxA and the Gx bitson the DAC output If the LAT pin is held at VIH thevalues sent to the Volatile Wiper registers and Configu-ration bits have no effect on the DAC outputs After theVolatile Wiper registers and Configuration bits havebeen loaded with the desired data once the voltage onthe pin transitions to VIL the values in the Volatile Wiperregisters and Configuration bits are transferred to theDAC outputs Pulsing LAT low during writes to theregisters could lead to unpredictable DAC output voltagevalues until the next pulse is issued and should beavoided The pin is level-sensitive so writing to theVolatile Wiper registers and Configuration bits while it isbeing held at VIL will trigger an immediate change in theoutputs

For dual output devices in MSOP and DFN packagesthe LAT pin controls both channels at the same timeThe HVC pin allows the devicersquos MTP memory to beprogrammed for the MCP47CMBXX devices Theprogramming voltage supply should provide 75V andat least 64 mA

Note The HVC pin should have voltagesgreater than 55V present only during theMTP programming operation Usingvoltages greater than 55V for anextended time on the pin may causedevice reliability issues


MCP47CXBXX

36 I2C ndash Serial Clock Pin (SCL)

The SCL pin is the serial clock pin of the I2C interfaceThe MCP47CXBXX I2C interface only acts as a Slaveand the SCL pin accepts only external serial clocksThe input data from the Master device are shifted intothe SDA pin on the rising edges of the SCL clock andoutput from the device occurs at the falling edges of theSCL clock The SCL pin is an open-drain N-channeldriver Therefore it needs an external pull-up resistorfrom the VDD line to the SCL pin Refer to Section 60ldquoI2C Serial Interface Modulerdquo for more details on theI2C serial interface communication

37 I2C ndash Serial Data Pin (SDA)

The SDA pin is the serial data pin of the I2C interfaceThe SDA pin is used to write or read the DAC registersand Configuration bits The SDA pin is an open-drainN-channel driver Therefore it needs an externalpull-up resistor from the VDD line to the SDA pin Exceptfor Start and Stop conditions the data on the SDA pinmust be stable during the high period of the clock Thehigh or low state of the SDA pin can only change whenthe clock signal on the SCL pin is low See Section 60ldquoI2C Serial Interface Modulerdquo

38 I2C Slave Address Pins (A0A1)

The state of these pins will determine the devicersquos I2CSlave Address bit 0 value (overriding the ADD0 bit andthe ADD1 bit in Register 4-5)

39 No Connect (NC)

The NC pin is not internally connected to the device


MCP47CXBXX

40 GENERAL DESCRIPTION

The MCP47CXBX1 (MCP47CXB01 MCP47CXB11and MCP47CXB21) devices are single-channel voltageoutput devices

MCP47CXBX2 (MCP47CXB02 MCP47CXB12 andMCP47CXB22) are dual channel voltage output devices

These devices are offered with 8-bit (MCP47CXB0X)10-bit (MCP47CXB1X) and 12-bit (MCP47CXB2X)resolutions

The family offers two memory options theMCP47CVBXX devices have volatile memory whilethe MCP47CMBXX have 32-times programmablenonvolatile memory (MTP)

All devices include an I2C serial interface and a writelatch (LAT) pin to control the update of the analog out-put voltage value from the value written in the VolatileDAC Output register

The devices use a resistor ladder architecture Theresistor ladder DAC is driven from a software-selectable voltage reference source The source canbe either the devicersquos internal VDD an external VREFpin voltage (buffered or unbuffered) or an internalband gap voltage source

The DAC output is buffered with a low-power andprecision output amplifier This output amplifier pro-vides a rail-to-rail output with low offset voltage andlow noise The gain (1x or 2x) of the output buffer issoftware configurable

The devices operate from a single supply voltage Thisvoltage is specified from 27V to 55V for full specifiedoperation and from 18V to 55V for digital operationThe device operates between 18V and 27V butsome device parameters are not specified

The MCP47CMBXX devices also have user-programmable nonvolatile configuration memory(MTP) This allows the devicersquos desired POR values tobe saved or the I2C address to be changed Thedevice also has general purpose MTP memorylocations for storing system-specific information(calibration data serial numbers system ID informa-tion) A high-voltage requirement for programming onthe HVC pin ensures that these device settings are notaccidentally modified during normal system operationTherefore it is recommended that the MTP memoryshould only be programmed at the userrsquos factory

The main functional blocks are

bull Power-on ResetBrown-out Reset (PORBOR)

bull Device Memory

bull Resistor Ladder

bull Output BufferVOUT Operation

bull I2C Serial Interface Module

41 Power-on ResetBrown-out Reset (PORBOR)

The internal Power-on Reset (POR)Brown-out Reset(BOR) circuit monitors the power supply voltage (VDD)during operation This circuit ensures correct devicestart-up at system power-up and power-down events

The devicersquos RAM Retention Voltage (VRAM) is lowerthan the PORBOR Voltage Trip Point (VPORVBOR)The maximum VPORVBOR voltage is less than 18V

The POR and BOR trip points are at the same voltageand the condition is determined by whether the VDDvoltage is rising or falling (see Figure 4-1) What occursis different depending on whether the Reset is a PORor BOR Reset

POR occurs as the voltage rises (typically from 0V)while BOR occurs as the voltage falls (typically fromVDD(MIN) or higher)

When VPORVBOR lt VDD lt 27V the electrical perfor-mance may not meet the data sheet specifications Inthis region the device is capable of reading and writingto its volatile memory if the proper serial command isexecuted

411 POWER-ON RESET

The Power-on Reset is the case where the devicersquosVDD has power applied to it from the VSS voltage levelAs the device powers up the VOUT pin floats to anunknown value When the devicersquos VDD is above thetransistor threshold voltage of the device the outputstarts to be pulled low

After the VDD is above the PORBOR trip point(VBORVPOR) the resistor networkrsquos wiper is loadedwith the POR value The POR value is either mid-scale(MCP47CVBXX) or the userrsquos MTP programmed value(MCP47CMBXX)

Note In order to have the MCP47CMBXXdevices load the values from nonvolatilememory locations at POR they have to beprogrammed at least once by the userotherwise the loaded values will be thedefault ones After MTP programming aPOR event is required to load the writtenvalues from the nonvolatile memory


MCP47CXBXX

Volatile memory determines the Analog Output (VOUT)pin voltage After the device is powered up the usercan update the device memory

When the rising VDD voltage crosses the VPOR trippoint the following occur

bull The default DAC POR value is latched into the Volatile DAC register

bull The default DAC POR Configuration bit values are latched into the Volatile Configuration bits

bull POR status bit is set (lsquo1rsquo)bull The Reset Delay Timer (tPORD) starts when the

Reset Delay Timer (tPORD) times out the I2C serial interface is operational During this delay time the I2C interface will not accept commands

bull The Device Memory Address Pointer is forced to 00h

The Analog Output (VOUT) state is determined by thestate of the Volatile Configuration bits and the DACregister This is called a Power-on Reset (event)

Figure 4-1 illustrates the conditions for power-up andpower-down events under typical conditions

FIGURE 4-1 Power-on Reset Operation

VPOR

TPORD2OD

VDD(MIN)

BOR Reset Volatile DAC Register = 000hVolatile VRxBVRxA = 00

VRAM

Volatile Gx = 0 Volatile PDxBPDxA = 11

VBOR

POR starts Reset Delay TimerWhen timer times out the I2C interfacecan operate (if VDD VDD(MIN))

VDD(MIN)

TPOR2OD

VBOR VPOR

VRAM

Case 1 VDD Ramp

Case 2 VDD Step

Volatile MemoryRetains Data Value

POR ResetForce Active

Device in Unknown Devicein PORState

Normal OperationState

Below MinOperatingVoltage

Device inPower-Down State

Device inUnknownState

Default device configurationlatched into Volatile Configurationbits and DAC registerPOR status bit is set (lsquo1rsquo)

Volatile Memorybecomes Corrupted




Normal Operation Below MinOperatingVoltage

Device in UnknownState

Device inKnown State


POR Event


MCP47CXBXX

412 BROWN-OUT RESET

A Brown-out Reset occurs when a device had powerapplied to it and that power (voltage) drops below thespecified range

When the falling VDD voltage crosses the VPOR trippoint (BOR event) the following occurs

bull Serial interface is disabled

bull MTP writes are disabled

bull Device is forced into a power-down state (PDxBPDxA = 11) Analog circuitry is turned off

bull Volatile DAC register is forced to 000h

Volatile Configuration bits VRxBVRxA and Gx areforced to lsquo0rsquo

If the VDD voltage decreases below the VRAM voltageall volatile memory may become corrupted

As the voltage recovers above the VPORVBOR voltagesee Section 411 ldquoPower-on Resetrdquo for further details

Serial commands not completed due to a brown-outcondition may cause the memory location to becomecorrupted


42 Device Memory

User memory includes the following types

bull Volatile Register Memory (RAM)bull Nonvolatile Register Memory (MTP)

MTP memory is present just for the MCP47CMBXXdevices and has three groupings

bull NV DAC Output Values (loaded on POR event)

bull Device Configuration Memory

bull General Purpose NV Memory

Each memory location is up to 16 bits wide Thememory-mapped register space is shown in Table 4-1

The I2C interface depends on how this memory is readand written Refer to Section 60 ldquoI2C Serial InterfaceModulerdquo and Section 70 ldquoDevice Commandsrdquo formore details on reading and writing the devicersquosmemory

421 VOLATILE REGISTER MEMORY (RAM)

The MCP47CXBXX devices have volatile memory todirectly control the operation of the DACs There areup to five volatile memory locations

bull DAC0 and DAC1 Output Value registers

bull VREF Select register

bull Power-Down Configuration register

bull Gain and Status register

The volatile memory starts functioning when thedevice VDD is at (or above) the RAM retention voltage(VRAM) The volatile memory will be loaded with thedefault device values when the VDD rises across theVPORVBOR voltage trip point

After the device is powered-up the user can update thedevice memory Table 4-2 shows the volatile memorylocations and their interaction due to a POR event


MCP47CXBXX

TABLE 4-1 MCP47CXBXX MEMORY MAP (16-BIT)A

dd

res

s

Function

Sin

gle

Du

al

Ad

dre

ss

Function

Sin

gle

(1)

Du

al(1

)

00h Volatile DAC Wiper Register 0 Y Y 10h Nonvolatile DAC Wiper Register 0 Y Y

01h Volatile DAC Wiper Register 1 mdash Y 11h Nonvolatile DAC Wiper Register 1 mdash Y

02h Reserved mdash mdash 12h Reserved mdash mdash






08h Volatile VREF Register Y Y 18h Nonvolatile VREF Register Y Y

09h Volatile Power-Down Register Y Y 19h Nonvolatile Power-Down Register Y Y

0Ah Volatile Gain and Status Register Y Y 1Ah NV Gain and I2C 7-Bit Slave Address Y Y

0Bh Reserved mdash mdash 1Bh NV WiperLocktrade Technology Register Y Y

0Ch General Purpose MTP (1) 1Ch General Purpose MTP (1)

0Dh General Purpose MTP (1) 1Dh General Purpose MTP (1)

0Eh General Purpose MTP (1) 1Eh General Purpose MTP (1)

0Fh General Purpose MTP (1) 1Fh General Purpose MTP (1)

Legend

Volatile Memory Addresses

MTP Memory Addresses

Memory Locations Not Implemented on this Device Family

Note 1 On nonvolatile memory devices only (MCP47CMBXX)


MCP47CXBXX

422 NONVOLATILE REGISTER MEMORY (MTP)

This memory option is available only for theMCP47CMBXX devices

MTP memory starts functioning below the devicersquosVPORVBOR trip point and once the VPOR eventoccurs the Volatile Memory registers are loaded withthe corresponding MTP register memory values

Memory addresses 0Ch through 1Fh are nonvolatilememory locations These registers contain the DACPORBOR wiper values the DAC PORBOR Configura-tion bits the I2C Slave address and eight generalpurpose memory addresses for storing user-defineddata as calibration constants or identification numbersThe Nonvolatile DAC Wiper registers and Configurationbits contain the userrsquos DAC Output and configurationvalues for the POR event

The Nonvolatile DAC Wiper registers contain the userrsquosDAC output and configuration values for the PORevent These nonvolatile values will overwrite thefactory default values If these MTP addresses areunprogrammed the factory default values define theoutput state

The Nonvolatile DAC registers enable the stand-aloneoperation of the device (without microcontroller control)after being programmed to the desired values

To program nonvolatile memory locations a high-voltage source on the LATHVC pin is required EachregisterMTP location can be programmed 32 timesAfter 32 writes a new write operation will not bepossible and the last successful value written willremain associated with the memory location

The device starts writing the MTP memory cells at thecompletion of the serial interface command at the risingedge of the last data bit The high voltage shouldremain present on the LATHVC pin until the write cycleis complete otherwise the write is unsuccessful andthe location is compromised (cannot be used again andthe number of available writes decreases by one)

To recover from an aborted MTP write operation thefollowing procedure must be used

bull Write again any valid value to the same address

bull Force a POR condition

bull Write again the desired value to the MTP location

It is recommended to keep high voltage on only duringthe MTP write command and programming cycleotherwise the reliability of the device could be affected

423 PORBOR OPERATION WITH WIPERLOCK TECHNOLOGY ENABLED

Regardless of the WiperLock technology state a PORevent will load the Volatile DACx Wiper register valuewith the Nonvolatile DACx Wiper register value Referto Section 41 ldquoPower-on ResetBrown-out Reset(PORBOR)rdquo for further information

424 UNIMPLEMENTED LOCATIONS

4241 Unimplemented Register Bits

When issuing read commands to a valid memory loca-tion with unimplemented bits the unimplemented bitswill be read as lsquo0rsquo

4242 Unimplemented (RESERVED) Locations

There are a number of unimplemented memorylocations that are reserved for future use Normal(voltage) commands (read or write) to any unimple-mented memory address will result in a commanderror condition (I2C NACK)

High-voltage commands to any unimplementedConfiguration bit(s) will also result in a command errorcondition


MCP47CXBXX

TABLE 4-2 FACTORY DEFAULT PORBOR VALUES (MTP MEMORY UNPROGRAMMED)A

dd

ress

Function

PORBOR Value

Ad

dre

ss

Function

PORBOR Value

8-B

it

10-B

it

12-B

it

8-B

it

10-B

it

12-B

it

00h Volatile DAC0 Register 7Fh 1FFh 7FFh 10h Nonvolatile DAC0 Wiper Register(1)

7Fh 1FFh 7FFh


7Fh 1FFh 7FFh

02h Reserved(3) mdash mdash mdash 12h Reserved(3) mdash mdash mdash






08h Volatile VREF Register 0000h 0000h 0000h 18h Nonvolatile VREF Register(1) 0000h 0000h 0000h

09h Volatile Power-Down Register

0000h 0000h 0000h 19h Nonvolatile Power-Down Register(1)

0000h 0000h 0000h

0Ah Volatile Gain and Status Register(4)

0080h 0080h 0080h 1Ah NV Gain and I2C 7-Bit Slave Address(12)

0060h 0060h 0060h

0Bh Reserved(3) 0000h 0000h 0000h 1Bh NV WiperLocktrade Technology Register(1)

0000h 0000h 0000h

0Ch General Purpose MTP(1) 0000h 0000h 0000h 1Ch General Purpose MTP(1) 0000h 0000h 0000h

0Dh General Purpose MTP(1) 0000h 0000h 0000h 1Dh General Purpose MTP(1) 0000h 0000h 0000h

0Eh General Purpose MTP(1) 0000h 0000h 0000h 1Eh General Purpose MTP(1) 0000h 0000h 0000h

0Fh General Purpose MTP(1) 0000h 0000h 0000h 1Fh General Purpose MTP(1) 0000h 0000h 0000h

Legend

Volatile Memory Address Range

Nonvolatile Memory Address Range

Not Implemented

Note 1 On nonvolatile devices only (MCP47CMBXX)2 Default I2C 7-bit Slave address is lsquo110 0000rsquo (lsquo110 00xxrsquo when A1A0 bits are determined from the A1 and A0 pins) 3 Reading a reserved memory location will result in the I2C command to Not ACK the command byte The device data

bits will output all lsquo1rsquos A Start condition will reset the I2C interface 4 The lsquo1rsquo bit is the POR status bit which is set after the POR event and cleared after address 0Ah is read


MCP47CXBXX

12-b

10-b

8-b

425 DEVICE REGISTERS

Register 4-1 shows the format of the DAC Output Valueregisters for the volatile memory locations Theseregisters will be either 8 bits 10 bits or 12 bits wide Thevalues are right justified

REGISTER 4-1 DAC0 (00h10h) AND DAC1 (01h11h) OUTPUT VALUE REGISTERS (VOLATILENONVOLATILE)

U-0 U-0 U-0 U-0 RW-n RW-n RW-n RW-n RW-n RW-n RW-n RW-n RW-n RW-n RW-n RW-n

it mdash mdash mdash mdash D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

it mdash mdash mdash mdash mdash mdash D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

it mdash mdash mdash mdash mdash mdash mdash mdash D07 D06 D05 D04 D03 D02 D01 D00

bit 15 bit 0

Legend

R = Readable bit W = Writable bit U = Unimplemented bit read as lsquo0rsquo -n = Value at POR lsquo1rsquo = Bit is set lsquo0rsquo = Bit is cleared x = Bit is unknown

= 12-bit device = 10-bit device = 8-bit device

12-bit 10-bit 8-bit

bit 15-12 bit 15-10 bit 15-8 Unimplemented Read as lsquo0rsquo

bit 11-0 mdash mdash D11D00 DAC Output Value bits ndash 12-bit devices

FFFh = Full-scale output value7FFh = Mid-scale output value000h = Zero scale output value

mdash bit 9-0 mdash D09D00 DAC Output Value bits ndash 10-bit devices

3FFh = Full-scale output value1FFh = Mid-scale output value000h = Zero scale output value

mdash mdash bit 7-0 D07D00 DAC Output Value bits ndash 8-bit devices

FFh = Full-scale output value7Fh = Mid-scale output value00h = Zero scale output value


MCP47CXBXX

Sing

Du

Register 4-2 shows the format of the Voltage Refer-ence Control register Each DAC has two bits to controlthe source of the voltage reference of the DAC Thisregister is for the volatile memory locations The widthof this register is two times the number of DACs for thedevice

REGISTER 4-2 VOLTAGE REFERENCE (VREF) CONTROL REGISTERS (08h18h)(VOLATILENONVOLATILE)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 RW-n RW-n RW-n RW-n

le mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash(1) mdash(1) VR0B VR0A

al mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash VR1B VR1A VR0B VR0A

bit 15 bit 0

Legend


= Single channel device = Dual channel device

Single Dual

bit 15-2 bit 15-4 Unimplemented Read as lsquo0rsquo

bit 1-0 bit 3-0 VRxBVRxA DAC Voltage Reference Control bits

11 = VREF pin (buffered) VREF buffer enabled10 = VREF pin (unbuffered) VREF buffer disabled01 = Internal band gap (1214V typical) VREF buffer enabled VREF voltage driven when

powered down(2)

00 = VDD (unbuffered) VREF buffer disabled use this state with power-down bits for lowest current

Note 1 Unimplemented bit read as lsquo0rsquo

2 When the internal band gap is selected the band gap voltage source will continue to output the voltage on the VREF pin in any of the Power-Down modes To reduce the power consumption to its lowest level (band gap disabled) after selecting the desired Power-Down mode the voltage reference should be changed to VDD or the VREF pin unbuffered (lsquo00rsquo or lsquo10rsquo) which turns off the Internal band gap circuitry After wake-up the user needs to reselect the internal band gap (lsquo01rsquo) for the voltage reference source


MCP47CXBXX

Sing

Du

Register 4-3 shows the format of the Power-DownControl register Each DAC has two bits to control thepower-down state of the DAC This register is for thevolatile memory locations and the nonvolatile memorylocations The width of this register is two times thenumber of DACs for the device

REGISTER 4-3 POWER-DOWN CONTROL REGISTERS (09h19h)(VOLATILENONVOLATILE)


le mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash(1) mdash(1) PD0B PD0A

al mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash PD1B PD1A PD0B PD0A

bit 15 bit 0

Legend



Single Dual


bit 1-0 bit 3-0 PDxBPDxA DAC Power-Down Control bits(2)

11 = Powered down ndash VOUT is open circuit10 = Powered down ndash VOUT is loaded with a 100 k resistor to ground01 = Powered down ndash VOUT is loaded with a 1 k resistor to ground00 = Normal operation (not powered down)


2 See Table 5-5 for more details


MCP47CXBXX

Sing

Du

Register 4-4 shows the format of the Gain Control andSystem Status register Each DAC has one bit tocontrol the gain of the DAC and two Status bits

REGISTER 4-4 GAIN CONTROL AND SYSTEM STATUS REGISTER (0Ah)(VOLATILE)

U-0 U-0 U-0 U-0 U-0 U-0 RW-n RW-n RC-1 R U-0 U-0 U-0 U-0 U-0 U-0

le mdash mdash mdash mdash mdash mdash mdash(1) G0 POR MTPMA mdash mdash mdash mdash mdash mdash

al mdash mdash mdash mdash mdash mdash G1 G0 POR MTPMA mdash mdash mdash mdash mdash mdash

bit 15 bit 0

Legend

R = Readable bit W = Writable bit C = Clearable bit U = Unimplemented bit read as lsquo0rsquo -n = Value at POR lsquo1rsquo = Bit is set lsquo0rsquo = Bit is cleared x = Bit is unknown


Single Dual


mdash bit 9 G1 DAC1 Output Driver Gain Control bit

1 = 2x gain not applicable when VDD is used as VRL(2)

0 = 1x gain

bit 8 bit 8 G0 DAC0 Output Driver Gain Control bit


0 = 1x gain

bit 7 bit 7 POR Power-on Reset (Brown-out Reset) Status bit

This bit indicates if a POR or BOR event has occurred since the last read command of this register Reading this register clears the state of the POR Status bit

1 = A POR (BOR) event occurred since the last read of this register reading this register clearsthis bit

0 = A POR (BOR) event has not occurred since the last read of this register

bit 6 bit 6 MTPMA MTP Memory Access Status bit(3)

This bit indicates if the MTP memory access is occurring

1 = An MTP memory access is currently occurring (during the POR MTP read cycle or an MTPwrite cycle is occurring) only serial commands addressing the volatile memory are allowed

0 = An MTP memory access is NOT currently occurring



2 The DACrsquos Gain bit is ignored and the gain is forced to 1x (Gx = 0) when the DAC voltage reference is selected as VDD (VRxBVRxA = 00)

3 For devices configured as volatile memory this bit is read as lsquo0rsquo


MCP47CXBXX

Sing

Du

Register 4-5 shows the format of the Nonvolatile GainControl and Slave Address register Each DAC hasone bit to control the gain of the DAC I2C devices alsohave seven bits that are the I2C Slave address

REGISTER 4-5 GAIN CONTROL AND SLAVE ADDRESS REGISTER (1Ah)(NONVOLATILE)

U-0 U-0 U-0 U-0 U-0 U-0 RW-n RW-n U-0 RW-n RW-n RW-n RW-n RW-n RW-n RW-n

le mdash mdash mdash mdash mdash mdash G1 G0 mdash ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

al mdash mdash mdash mdash mdash mdash G1 G0 mdash ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

bit 15 bit 0

Legend


= Single-channel device = Dual-channel device

Single Dual


bit 9-8 bit 9-8 Gx DAC Output Driver Gain Control bits(1)

1 = 2x gain0 = 1x gain

bit 7 bit 7 Unimplemented Read as lsquo0rsquo

bit 6-0 bit 6-0 ADD6ADD0 I2C 7-Bit Slave Address bits(2)

Note 1 When the DAC voltage reference is selected as VDD (VRxBVRxA = 00) the DACrsquos Gain bit is ignored and the gain is forced to 1x (Gx = 0)

2 For I2C devices that have the A1 and A0 pins the 7-bit Slave address is ADD6ADD2 + A1A0 For devices without the A1 and A0 pins the 7-bit Slave address is ADD6ADD0


MCP47CXBXX

Singl

Dua

Register 4-6 shows the format of the DAC WiperLockTechnology Status register The width of this register istwo times the number of DACs for the device

WiperLock technology bits only control access tovolatile memory Nonvolatile memory write access iscontrolled by the requirement of high voltage on theHVC pin which is recommended to not be availableduring normal device operation

REGISTER 4-6 WiperLocktrade TECHNOLOGY CONTROL REGISTER (1Bh) (NONVOLATILE)


e mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash(1) mdash(1) WL0B WL0A

l mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash mdash WL1B WL1A WL0B WL0A

bit 15 bit 0

Legend



Single Dual


bit 1-0 bit 3-1 WLxBWLxA WiperLocktrade Technology Status bits(2)

11 = Volatile DAC Wiper register and Volatile DAC Configuration bits are locked10 = Volatile DAC Wiper register is locked and Volatile DAC Configuration bits are unlocked01 = Volatile DAC Wiper register is unlocked and Volatile DAC Configuration bits are locked00 = Volatile DAC Wiper register and Volatile DAC Configuration bits are unlocked


2 The Volatile PDxBPDxA bits are NOT locked due to the requirement of being able to exit Power-Down mode


MCP47CXBXX

50 DAC CIRCUITRY

The Digital-to-Analog Converter circuitry converts adigital value into its analog representation Thisdescription describes the functional operation of thedevice

The DAC circuit uses a resistor ladder implementationDevices have up to two DACs Figure 5-1 shows thefunctional block diagram for the MCP47CXBXX DACcircuitry

The functional blocks of the DAC include


bull Voltage Reference Selection


bull Latch Pin (LAT)

bull Power-Down Operation

FIGURE 5-1 MCP47CXBXX DAC Module Block Diagram

RS(2)

VREF

DACOutput

RS(1)

RS(2n ndash 1)

RS(2n ndash 2)

RS(2n ndash 3)

RS(2n)

VDD

VRL

VOUT

PD1PD0

VDD

PD1PD0

VDD

VW

Band Gap(1214V typical)

VREF1VREF0and PD1PD0

Selection

Internal Band GapVoltageReferenceSelection

ResistorLadder

Output BufferVOUT Operation

Power-DownOperation

Power-DownOperation

Power-DownOperation

A (RL)

B

VREF1VREF0

Where

Resistors in Resistor Ladder = 256 (MCP47CXB0X)

1024 (MCP47CXB1X)

4096 (MCP47CXB2X)

VWDAC Register Value

Resistor in Resistor Ladder---------------------------------------------------------------------- VRL=

VDD

(~71 k)RRL

1kΩ

100

kΩ

Gain(1x or 2x)



MCP47CXBXX

51 Resistor Ladder

The resistor ladder is a digital potentiometer with theA Terminal connected to the selected reference voltageand the B Terminal internally grounded (see Figure 5-2)The Volatile DAC register controls the wiper positionThe Wiper Voltage (VW) is proportional to the DACregister value divided by the number of ResistorElements (RS) in the ladder (256 1024 or 4096) relatedto the VRL voltage

The output of the resistor network will drive the input ofan output buffer

The resistor network is made up of three parts

bull Resistor Ladder (string of RS elements) bull Wiper Switchesbull DAC Register Decode

The resistor ladder has a typical impedance (RRL) ofapproximately 71 k This Resistor Ladder Resistance(RRL) may vary from device to device up to plusmn10Since this is a voltage divider configuration the actualRRL resistance does not affect the output given a fixedvoltage at VRL

Equation 5-1 shows the calculation for the stepresistance

If the unbuffered VREF pin is used as the VRL voltagesource the external voltage source should have a lowoutput impedance

When the DAC is powered down the resistor ladder isdisconnected from the selected reference voltage

FIGURE 5-2 Resistor Ladder Model Block Diagram

EQUATION 5-1 RS CALCULATION

Note The maximum wiper position is 2n ndash 1while the number of resistors in theresistor ladder is 2n This means thatwhen the DAC register is at full scalethere is one Resistor Element (RS)between the wiper and the VRL voltage

VW

Analog MUX

Note 1 The analog Switch Resistance (RW) does not affect performance due to the voltage divider configuration

RS(2)

DACRegister

RS(1)

RS(2n ndash 1)

RS(2n ndash 2)

RS(2n ndash 3)

RS(2n)

VRL

RRL

RW(1)

RW(1)

RW(1)

RW(1)

RW(1)

RW(1)

2n ndash 1

2n ndash 2

1

0

2

2n ndash 3

RS

RRL256

--------------=

RS

RRL1024

------------------=

8-Bit Device

10-Bit Device

RS

RRL4096

------------------= 12-Bit Device


MCP47CXBXX

52 Voltage Reference Selection

The resistor ladder has up to four sources for the refer-ence voltage The selection of the voltage referencesource is specified with the Volatile VREF1VREF0Configuration bits (see Register 4-2) The selectedvoltage source is connected to the VRL node (seeFigure 5-3 and Figure 5-4)

The four voltage source options for the Resistor Ladderare

1 VDD pin voltage

2 Internal Band Gap Voltage Reference (VBG)

3 VREF pin voltage ndash unbuffered

4 VREF pin voltage ndash internally buffered

On a PORBOR event the default configuration state orthe value written in the Nonvolatile register is latched intothe Volatile VREF1VREF0 Configuration bits

If the VREF pin is used with an external voltage sourcethen the user must select between Buffered orUnbuffered mode

FIGURE 5-3 Resistor Ladder Reference Voltage Selection Block Diagram

FIGURE 5-4 Reference Voltage Selection Implementation Block Diagram

521 USING VDD AS VREF

When the user selects the VDD as reference the VREFpin voltage is not connected to the resistor ladder TheVDD voltage is internally connected to the resistorladder

522 USING AN EXTERNAL VREF SOURCE IN UNBUFFERED MODE

In this case the VREF pin voltage may vary from VSS toVDD The voltage source should have a low outputimpedance If the voltage source has a high outputimpedance then the voltage on the VREF pin could belower than expected The resistor ladder has a typicalimpedance of 71 k and a typical capacitance of 29 pF

If a single VREF pin is supplying multiple DACs theVREF pin source must have adequate current capabilityto support the number of DACs It must be assumedthat the Resistor Ladder Resistance (RRL) of each DACis at the minimum specified resistance and theseresistances are in parallel

If the VREF pin is tied to the VDD voltage selectingthe VDD Reference mode (VREF1VREF0 = 00) isrecommended

VRL

VDD

Buffer

Re

fere

nce

VREF1VREF0

Se

lect

ion

VREF

Band Gap

Note 1 The Band Gap Voltage (VBG) is 1214V typical The band gap output goes through the buffer with a 2x gain to create the VRL voltage See Table 5-1 for additional information on the band gap circuit

VDD

VRL

Band Gap(1)

(1214V typical)

VDD

VDD

VREF





MCP47CXBXX

523 USING AN EXTERNAL VREF SOURCE IN BUFFERED MODE

The VREF pin voltage may be from 0V to VDD The inputbuffer (amplifier) provides low offset voltage low noiseand a very high input impedance with only minorlimitations on the input range and frequency response

Any variation or noises on the reference source candirectly affect the DAC output The reference voltageneeds to be as clean as possible for accurate DACperformance

524 USING THE INTERNAL BAND GAP AS VOLTAGE REFERENCE

The internal band gap is designed to drive the resistorladder buffer

If the internal band gap is selected then the band gapvoltage source will drive the external VREF pins TheVREF0 pin can source up to 1 mA of current withoutaffecting the DAC output specifications The VREF1 pinmust be left unloaded in this mode The voltage refer-ence source can be independently selected on deviceswith two DAC channels but restrictions apply

bull The VDD mode can be used without issues on any channel

bull When the internal band gap is selected as the voltage source all the VREF pins are connected to its output The use of the Unbuffered mode is only possible on VREF0 because itrsquos the only one that can be loaded

bull When using the Internal Band Gap mode on Channel 0 Channel 1 must be put in Buffered External VREF mode or VDD Reference mode and the VREF1 pin must be left unloaded

The resistance of the Resistor Ladder (RRL) is targetedto be 71 k (10) which means a minimumresistance of 639 k

The band gap selection can be used across the VDDvoltages while maximizing the VOUT voltage rangesFor VDD voltages below the Gain VBG voltage theoutput for the upper codes will be clipped to the VDDvoltage Table 5-1 shows the maximum DAC registercode given device VDD and Gain bit setting

53 Output BufferVOUT Operation

The output driver buffers the Wiper Voltage (VW) of theresistor ladder

The DAC output is buffered with a low-power precisionoutput amplifier with selectable gain This amplifier pro-vides a rail-to-rail output with low offset voltage and lownoise The amplifierrsquos output can drive the resistive andhigh-capacitive loads without oscillation The amplifierprovides a maximum load current which is enough formost programmable voltage reference applicationsRefer to Section 10 ldquoElectrical Characteristicsrdquo forthe specifications of the output amplifier

Figure 5-5 shows a block diagram of the output drivercircuit

FIGURE 5-5 Output Driver Block Diagram

Power-down logic also controls the output bufferoperation (see Section 55 ldquoPower-Down Operationrdquofor additional information on power-down) In any of thethree Power-Down modes the output amplifier ispowered down and its output becomes a high-impedanceto the VOUT pin

531 PROGRAMMABLE GAIN

The amplifierrsquos gain is controlled by the Gain (G)Configuration bit (see Register 4-4) and the VRLreference selection (see Register 4-2)

The Gain options are

a) Gain of 1 with either the VDD or VREF pin usedas the reference voltage

b) Gain of 2 only when the VREF pin or the internalband gap is used as the reference voltage TheVREF pin voltage should be limited to VDD2When the Reference Voltage Selection (VRL) isthe devicersquos VDD voltage the Gx bit is ignoredand a gain of 1 is used

TABLE 5-1 VOUT USING BAND GAP

VD

D

DA

C G

ain Max DAC Code(1)

Comment12-Bit 10-Bit 8-Bit

551 FFFh 3FFh FFh VOUT(max) = 1214V(3)



2 FFFh 3FFh FFh VOUT(max) = 2428V


2(2) BBCh 2EFh BBh 18V

Note 1 Without the VOUT pin voltage being clipped2 Recommended to use the Gain = 1 setting3 When VBG = 1214V typical

Note The load resistance must be kept higherthan 2 k to maintain stability of theanalog output and have it meet electricalspecifications

VWVOUT

PD1PD0

VDD

PD1PD0

1kΩ

100

kΩ

Gain(1x or 2x)


MCP47CXBXX

Table 5-2 shows the gain bit operation

The volatile G bit value can be modified by

bull POR Event

bull BOR Event

bull I2C Write Commands

bull I2C General Call Reset Command

532 OUTPUT VOLTAGE

The Volatile DAC register values along with thedevicersquos Configuration bits control the analog VOUTvoltage The Volatile DAC registerrsquos value is unsignedbinary The formula for the output voltage is provided inEquation 5-2 Examples of Volatile DAC register valuesand the corresponding theoretical VOUT voltage for theMCP47CXBXX devices are shown in Table 5-6

EQUATION 5-2 CALCULATING OUTPUT VOLTAGE (VOUT)

When Gain = 2 (VRL = VREF) if VREF gt VDD2 the VOUTvoltage is limited to VDD So if VREF = VDD the VOUTvoltage does not change for Volatile DAC registervalues mid-scale and greater since the output amplifieris at full-scale output

The following events update the DAC register valueand therefore the analog Voltage Output (VOUT)

bull Power-on Resetbull Brown-out Resetbull I2C write command (to Volatile registers) on the

rising edge of the last write command bitbull I2C General Call Reset command the output is

updated with default POR data or MTP valuesbull I2C general call wake-up command the output is

updated with default POR data or MTP values

Next the VOUT voltage starts driving to the new valueafter the event has occurred

533 STEP VOLTAGE (VS)

The step voltage depends on the device resolution andthe calculated output voltage range One LSb isdefined as the ideal voltage difference between twosuccessive codes The step voltage can easily be cal-culated by using Equation 5-3 (the DAC register valueis equal to lsquo1rsquo) Theoretical step voltages are shown inTable 5-3 for several VREF voltages

EQUATION 5-3 VS CALCULATION

TABLE 5-3 THEORETICAL STEP VOLTAGE (VS)(1)

TABLE 5-2 OUTPUT DRIVER GAIN

Gain Bit Gain Comment

0 1

1 2 Limits VREF pin voltages relative to device VDD voltage

Where

Resistors in R-Ladder = 4096 (MCP47CXB2X)

1024 (MCP47CXB1X)

256 (MCP47CXB0X)

VOUT

VRL DAC Register Value Resistor in Resistor Ladder---------------------------------------------------------------------- Gain=

Where

Resistors in R-Ladder = 4096 (12-bit)

1024 (10-bit)

256 (8-bit)

VS

VRL

Resistor in Resistor Ladder---------------------------------------------------------------------- Gain=

StepVoltage

VREF

50 27 18 15 10

VS

122 mV 659 uV 439 uV 366 uV 244 uV 12-bit

488 mV 264 mV 176 mV 146 mV 977 uV 10-bit

195 mV 105 mV 703 mV 586 mV 391 mV 8-bit

Note 1 When Gain = 1x VFS = VRL and VZS = 0V


MCP47CXBXX

534 OUTPUT SLEW RATE

Figure 5-6 shows an example of the slew rate of the VOUTpin The slew rate can be affected by the characteristicsof the circuit connected to the VOUT pin

FIGURE 5-6 VOUT Pin Slew Rate

5341 Small Capacitive Load

With a small capacitive load the output bufferrsquos currentis not affected by the Capacitive Load (CL) But still theVOUT pinrsquos voltage is not a step transition from one out-put value (DAC register value) to the next output valueThe change of the VOUT voltage is limited by the outputbufferrsquos characteristics so the VOUT pin voltage willhave a slope from the old voltage to the new voltageThis slope is fixed for the output buffer and is referredto as the Buffer Slew Rate (SRBUF)

5342 Large Capacitive Load

With a larger capacitive load the slew rate isdetermined by two factors

bull The output bufferrsquos Short-Circuit Current (ISC)

bull The VOUT pinrsquos external load

IOUT cannot exceed the output bufferrsquos Short-CircuitCurrent (ISC) which fixes the output Buffer Slew Rate(SRBUF) The voltage on the Capacitive Load (CL) VCLchanges at a rate proportional to IOUT which fixes aCapacitive Load Slew Rate (SRCL)

The VCL voltage slew rate is limited to the slower of theoutput bufferrsquos internally Set Slew Rate (SRBUF) andthe Capacitive Load Slew Rate (SRCL)

535 DRIVING RESISTIVE AND CAPACITIVE LOADS

The VOUT pin can drive up to 100 pF of capacitive loadin parallel with a 5 k resistive load (to meet electricalspecifications) VOUT drops slowly as the load resis-tance decreases after about 35 k It is recommendedto use a load with RL greater than 2 k

Refer to Section 20 ldquoTypical Performance Curvesrdquo fora detailed VOUT vs Resistive Load characterizationgraph

Driving large capacitive loads can cause stabilityproblems for voltage feedback output amplifiers As theload capacitance increases the feedback looprsquos phasemargin decreases and the closed-loop bandwidth isreduced This produces gain peaking in the frequencyresponse with overshoot and ringing in the stepresponse That is since the VOUT pinrsquos voltage doesnot quickly follow the bufferrsquos input voltage (due to thelarge capacitive load) the output buffer will overshootthe desired target voltage Once the driver detects thisovershoot it compensates by forcing it to a voltagebelow the target This causes voltage ringing on theVOUT pin

So when driving large capacitive loads with the outputbuffer a small Series Resistor (RISO) at the output (seeFigure 5-7) improves the output bufferrsquos stability(feedback looprsquos phase margin) by making the outputload resistive at higher frequencies The bandwidth willbe generally lower than the bandwidth with nocapacitive load

FIGURE 5-7 Circuit to Stabilize Output Buffer for Large Capacitive Loads (CL)

The RISO resistor value for your circuit needs to beselected The resulting frequency response peakingand step response overshoot for this RISO resistorvalue should be verified on the bench Modify theRISOrsquos resistance value until the output characteristicsmeet your requirements

A method to evaluate the systemrsquos performance is toinject a step voltage on the VREF pin and observe theVOUT pinrsquos characteristics

Time

DACx = A

VO

UT

VOUT(A)

VOUT(B)

DACx = B

Slew RateVOUT B VOUT A ndash

T--------------------------------------------------=

Note Additional insight into circuit design fordriving capacitive loads can be found inAN884 ldquoDriving Capacitive Loads WithOp Ampsrdquo (DS00884)

Gain

VOUT RISO

RL CL

VCL

VW


MCP47CXBXX

54 Latch Pin (LAT)

The Latch pin controls when the Volatile DAC registervalue is transferred to the DAC wiper This is useful forapplications that need to synchronize the wiper(s)updates to an external event such as zero-crossing orupdates to the other wipers on the device The LAT pinis asynchronous to the serial interface operation

When the LAT pin is high transfers from the VolatileDAC register to the DAC wiper are inhibited The VolatileDAC register value(s) can continue to be updated

When the LAT pin is low the Volatile DAC registervalue is transferred to the DAC wiper

Figure 5-8 shows the interaction of the LAT pin and theloading of the DAC Wiper x (from the Volatile DACRegister x) The transfers are level-driven If the LATpin is held low the corresponding DAC wiper isupdated as soon as the Volatile DAC register value isupdated

FIGURE 5-8 LAT and DAC Interaction

The LAT pin allows the DAC wiper to be updated to anexternal event and to have multiple DACchannelsdevices update at a common event

Since the DAC Wiper x is updated from the VolatileDAC Register x all DACs that are associated with agiven LAT pin can be updated synchronously

If the application does not require synchronization thenthis signal should be tied low

Figure 5-9 shows two cases of using the LAT pin tocontrol when the Wiper register is updated relative tothe value of a sine wave signal

FIGURE 5-9 Example Use of LAT Pin Operation

Note This allows both the Volatile DAC0 andDAC1 registers to be updated while theLAT pin is high and to have outputssynchronously updated as the LAT pin isdriven low

Write CommandRegister Address

DAC Wiper x

16 Clocks

LATSYNC

Transfer

Serial Shift Reg

Data(internal signal)

LAT SYNCTransfer

DataComment

1 1 0 No Transfer

1 0 0 No Transfer

0 1 1 Vol DAC Register x DAC Wiper x

0 0 0 No Transfer

Vol DAC Register x

Case 1 Zero-Crossing of Sine Wave to Update the Volatile DAC0 Register (using LAT pin)

Case 2 Fixed-Point Crossing of Sine Wave to Update the Volatile DAC0 Register (using LAT pin)

Indicates where LAT pin pulses are active (Volatile DAC0 register updated)


MCP47CXBXX

55 Power-Down Operation

To allow the application to conserve power when DACoperation is not required three Power-Down modesare available On devices with multiple DACs eachDACrsquos Power-Down mode is individually controllable

All Power-Down modes do the following

bull Turn off most of the DAC modulersquos internal circuitsbull Op amp output becomes high-impedance to the

VOUT pinbull Retain the value of the Volatile DAC register and

Configuration bits

Depending on the selected Power-Down mode thefollowing will occur

bull VOUT pin is switched to one of the two resistive pull-downs- 100 k (typical) - 1 k (typical)

bull Op amp is powered down and the VOUT pin becomes high-impedance

The Power-Down Configuration bits (PD1PD0) controlthe power-down operation (Table 5-4)

TABLE 5-4 POWER-DOWN BITS AND OUTPUT RESISTIVE LOAD

There is a delay (TPDD) between the PD1PD0 bitschanging from lsquo00rsquo to either lsquo01rsquo lsquo10rsquo or lsquo11rsquo and theop amp no longer driving the VOUT output and thepull-down resistorsrsquo sinking current

In any of the Power-Down modes where the VOUT pinis not externally connected (sinking or sourcing cur-rent) as the number of DACs increases the devicersquospower-down current will also increase

Table 5-5 shows the current sources for the DAC basedon the selected source of the DACrsquos reference voltageand if the device is in normal operating mode or one ofthe Power-Down modes

The power-down bits are modified by using a writecommand to the Volatile Power-Down register or a PORevent which transfers the Nonvolatile Power-Downregister to the Volatile Power-Down register

Section 70 ldquoDevice Commandsrdquo describes the I2Ccommands for writing the power-down bits Thecommands that can update the volatile PD1PD0 bits are

bull Writebull General Call Resetbull General Call Wake-up

551 EXITING POWER-DOWN

The following events change the PD1PD0 bits to lsquo00rsquoand therefore exit the Power-Down mode These are

bull Any I2C Write Command where the PD1PD0 bits are lsquo00rsquo

bull I2C General Call Wake-up Command


When the device exits Power-Down mode thefollowing occurs

bull Disabled internal circuits are turned on

bull Resistor ladder is connected to the selected Reference Voltage (VRL)

bull Selected pull-down resistor is disconnected

bull The VOUT output is driven to the voltage represented by the Volatile DAC registerrsquos value and Configuration bits

The DAC Wiper register and DAC wiper value may bedifferent due to the DAC Wiper register being modifiedwhile the LAT pin was driven to (and remaining at) VIH

The VOUT output signal requires time as these circuitsare powered up and the output voltage is driven to thespecified value as determined by the Volatile DACregister and Configuration bits

PD1 PD0 Function

0 0 Normal operation

0 1 1 k resistor to ground


1 1 Open circuit

TABLE 5-5 DAC CURRENT SOURCES

Device VDD Current Source

PDxBxA = 00 VREFxBxA =

PDxBxA 00 VREFxBxA =

00 01 10 11 00 01 10 11Output Op Amp Y Y Y Y N N N N

Resistor Ladder Y Y N(1) Y N N N(1) N

VREF Selection Buffer N Y N Y N N N N

Band Gap N Y N N N(2) Y(2) N(2) N(2)

Note 1 The current is sourced from the VREF pin not the device VDD

2 If DAC0 and DAC1 are in one of the Power-Down modes MTP write operations are not recommended

Note 1 The I2C serial interface circuit is notaffected by the Power-Down mode Thiscircuit remains active in order to receiveany command that might come from theI2C Master device

2 A General Call Reset will do the PORevent sequence except that the MTPshadow memory values will be transferedto the Volatile Memory registers

Note Since the op amp and resistor ladder werepowered off (0V) the op amprsquos InputVoltage (VW) can be considered as 0VThere is a delay (TPDE) between thePD1PD0 bits updating to lsquo00rsquo and theop amp driving the VOUT output Theop amprsquos settling time (from 0V) needs tobe taken into account to ensure the VOUTvoltage reflects the selected value


MCP47CXBXX

TABLE 5-6 DAC INPUT CODE VS CALCULATED ANALOG OUTPUT (VOUT) (VDD = 50V)

DeviceVolatile DAC

Register ValueVRL

(1)LSb Gain

Selection (2)

VOUT(3)

Equation microV Equation VM

CP

47C

VB

2X (

12

-bit)

1111 1111 1111 50V 50V4096 12207 1x VRL (40954096) 1 4998779

25V 25V4096 6104 1x VRL (40954096) 1 2499390

2x(2) VRL (40954096) 2) 4998779

0111 1111 1111 50V 50V4096 12207 1x VRL (20474096) 1) 2498779

25V 25V4096 6104 1x VRL (20474096) 1) 1249390

2x(2) VRL (20474096) 2) 2498779

0011 1111 1111 50V 50V4096 12207 1x VRL (10234096) 1) 1248779

25V 25V4096 6104 1x VRL (10234096) 1) 0624390

2x(2) VRL (10234096) 2) 1248779

0000 0000 0000 50V 50V4096 12207 1x VRL (04096) 1) 0

25V 25V4096 6104 1x VRL (04096) 1) 0

2x(2) VRL (04096) 2) 0

MC

P47

CV

B1X

(1

0-b

it)

11 1111 1111 50V 50V1024 48828 1x VRL (10231024) 1 4995117

25V 25V1024 24414 1x VRL (10231024) 1 2497559

2x(2) VRL (10231024) 2 4995117

01 1111 1111 50V 50V1024 48828 1x VRL (5111024) 1 2495117

25V 25V1024 24414 1x VRL (5111024) 1 1247559

2x(2) VRL (5111024) 2 2495117

00 1111 1111 50V 50V1024 48828 1x VRL (2551024) 1 1245117

25V 25V1024 24414 1x VRL (2551024) 1 0622559

2x(2) VRL (2551024) 2 1245117

00 0000 0000 50V 50V1024 48828 1x VRL (01024) 1 0

25V 25V1024 24414 1x VRL (01024) 1 0

2x(2) VRL (01024) 1 0

MC

P4

7CV

B0X

(8

-bit)

1111 1111 50V 50V256 195313 1x VRL (255256) 1 4980469

25V 25V256 97656 1x VRL (255256) 1 2490234

2x(2) VRL (255256) 2 4980469

0111 1111 50V 50V256 195313 1x VRL (127256) 1 2480469

25V 25V256 97656 1x VRL (127256) 1 1240234

2x(2) VRL (127256) 2 2480469

0011 1111 50V 50V256 195313 1x VRL (63256) 1 1230469

25V 25V256 97656 1x VRL (63256) 1 0615234

2x(2) VRL (63256) 2 1230469

0000 0000 50V 50V256 195313 1x VRL (0256) 1 0

25V 25V256 97656 1x VRL (0256) 1 0

2x(2) VRL (0256) 2 0

Note 1 VRL is the resistor ladderrsquos reference voltage It is independent of the VREF1VREF0 selection 2 Gain selection of 2x (Gx = 1) requires the voltage reference source to come from the VREF pin

(VREF1VREF0 = 10 or 11) and requires VREF pin voltage (or VRL) le VDD2 or from the internal band gap (VREF1VREF0 = 01)

3 These theoretical calculations do not take into account the offset gain and nonlinearity errors


MCP47CXBXX

NOTES


MCP47CXBXX

60 I2C SERIAL INTERFACE MODULE

The MCP47CXBXXrsquos I2C serial interface modulesupports the I2C serial protocol specification This I2Cinterface is a two-wire interface (clock and data)Figure 6-1 shows a typical I2C interface connection

The I2C specification only defines the field typeslengths timings etc of a frame The frame contentdefines the behavior of the device The frame content(commands) for the MCP47CXBXX is defined inSection 70 ldquoDevice Commandsrdquo

An overview of the I2C protocol is available inAppendix B ldquoI2C Serial Interfacerdquo

FIGURE 6-1 Typical I2C Interface

61 Overview

This section discusses some of the specific character-istics of the MCP47CXBXX devicesrsquo I2C serial interfacemodule This is to assist in the development of yourapplication

The following sections discuss some of thesedevice-specific characteristics

bull Interface Pins (SCL and SDA)

bull Communication Data Rates

bull PORBOR

bull Device Memory Address

bull General Call Commands

bull Device I2C Slave Addressing

bull Slope Control

611 INTERFACE PINS (SCL AND SDA)

The MCP47CXBXX I2C module SCL pin does notgenerate the serial clock since the device operates inSlave mode Also the MCP47CXBXX will not stretchthe clock signal (SCL) since memory read accessoccurs fast enough

The MCP47CXBXX I2C module implements slopecontrol on the SDA pin output driver

62 Communication Data Rates

The I2C interface specifies different communication bitrates These are referred to as Standard Fast or High-Speed modes The MCP47CXBXX supports thesethree modes The clock rates (bit rate) of these modesare

bull Standard mode Up to 100 kHz (kbits)

bull Fast mode Up to 400 kHz (kbits)

bull High-Speed mode (HS mode) Up to 34 MHz (Mbits)

A description on how to enter High-Speed mode isdescribed in Section 68 ldquoSlope Controlrdquo

63 PORBOR

On a PORBOR event the I2C serial interface modulestate machine is reset which includes forcing thedevicersquos Memory Address Pointer to 00h

64 Device Memory Address

The memory address is the 5-bit value that specifiesthe location in the devicersquos memory that the specifiedcommand will operate on

On a PORBOR event the devicersquos Memory AddressPointer is forced to 00h

The MCP47CXBXX retains the last received ldquoDeviceMemory Addressrdquo That is the MCP47CXBXX does notldquocorruptrdquo the ldquodevice memory addressrdquo after RepeatedStart or Stop conditions

65 General Call Commands

The general call commands utilize the I2C specificationreserved general call command address and commandcodes The MCP47CXBXX also implements anonstandard general call command

The general call commands are

bull General Call Reset bull General Call Wake-up (MCP47CXBXX defined)

The general call wake-up command will cause all theMCP47CXBXX devices to exit their power-down state

66 Multi-Master Systems

The MCP47CXBXX is not a Master device (generatesthe interface clock) but it can be used in Multi-Masterapplications

SCLSCL

MCP47CVBXX

SDASDA

HostController

Typical I2C Interface Connections

Other Devices

(Master)(Slave)


MCP47CXBXX

67 Device I2C Slave Addressing

The address byte is the first byte received following theStart (or Repeated Start) condition from the Master device(see Figure 6-2) For nonvolatile devices the seven bits ofthe I2C Slave address are user-programmable Thedefault address is lsquo110 0000rsquo If the address pins arepresent on the specific package the lower two bits ofthe address are determined by the state of the A1 andA0 pins

For volatile devices (MCP47CVBXX) the I2C Slaveaddress bits A6A0 are fixed (lsquo110 0000rsquo) The userstill has Slave address programmability with the A1A0address pins (if available on the package)

FIGURE 6-2 Slave Address Bits in the I2C Control Byte

Table 6-1 shows the four standard orderable I2C Slaveaddresses and their respective device order codes

671 CUSTOM I2C SLAVE ADDRESS OPTIONS

Custom I2C Slave address options can be requestedUsers can request the custom I2C Slave address viathe Nonstandard Customer Authorization Request(NSCAR) process

68 Slope Control

The slope control on the SDA output is differentbetween the FastStandard Speed and the High-SpeedClock modes of the interface

69 Pulse Gobbler

The pulse gobbler on the SCL pin is automaticallyadjusted to suppress spikes lt10 ns during HS mode

Note Address bits A6A0 are MTP and canbe programmed during the userrsquosmanufacturing flow

Start BitReadWrite Bit

Address Byte

RW ACK

Acknowledge Bit

Slave Address

A6 A5 A4 A3

Slave Address (7 bits)

A2 A1 A0

1 1 0 0 0 0 0DefaultFactoryAddress(Note 1)

Note 1 Address bits (A6A0) can be programmed by the user (MCP47CMBXX devices) Bits A1 and A0 are determined by either the MTP bits or the A0 and A1 pin values if present on the package

TABLE 6-1 I2C ADDRESSORDER CODE

Default7-Bit I2C Address

Device Order Code(1)

Memory Tape and ReelVOL NV

lsquo1100000rsquoMCP47CXBXX-EXX Y Y N

MCP47CXBXXT-EXX Y Y Y

Note 1 Nonvolatile devicesrsquo I2C Slave address can be reprogrammed by the end user

Note Non-Recurring Engineering (NRE) chargesand minimum ordering requirements forcustom orders Please contact Microchipsales for additional information

A custom device will be assigned customdevice marking


MCP47CXBXX

610 Entering High-Speed (HS) Mode

The I2C specification requires that a High-Speed modedevice be lsquoactivatedrsquo to operate in High-Speed(34 Mbits) mode This is done by the Master sendinga special address byte following the Start bit This byteis referred to as the High-Speed Master Mode Code(HSMMC)

The device can now communicate at up to 34 Mbitson SDA and SCL lines The device will switch out of theHS mode on the next Stop condition

The Master code is sent as follows

1 Start condition (S)

2 High-Speed Master Mode Code (lsquo0000 1xxxrsquo)the lsquoxxxrsquo bits are unique to the High-Speed (HS)Master mode

3 No Acknowledge (A)

After switching to High-Speed mode the next trans-ferred byte is the I2C control byte which specifies thedevice to communicate with and any number of databytes plus Acknowledgments The Master device canthen either issue a Repeated Start bit to address adifferent device (at High-Speed mode) or a Stop bit toreturn to the bus FastStandard Speed mode After theStop bit any other Master device (in a Multi-Mastersystem) can arbitrate for the I2C bus

The MCP47CXBXX device does not Acknowledge theHS select byte However upon receiving thiscommand the device switches to HS mode

See Figure 6-3 for an illustration of the HS modecommand sequence

For more information on the HS mode or other I2Cmodes refer to the ldquoNXP I2C Specificationrdquo

FIGURE 6-3 HS Mode Sequence

S Alsquo0000 1xxxrsquobrsquo Sr ASlave Address AAData

P

S = Start bitSr = Repeated Start bitA = Acknowledge bitA = Not Acknowledge bit

RW = ReadWrite bit

RW

P = Stop bit (Stop condition terminates HS mode)

FS Mode HS Mode

HS Mode Continues

FS Mode

ASlave Address RWHS Select Byte Control Byte CommandData Byte(s)

Control Byte

Sr


MCP47CXBXX

NOTES


MCP47CXBXX

70 DEVICE COMMANDS

The I2C protocol does not specify how commands areformatted so this section specifies the MCP47CXBXXdevicersquos I2C command formats and operation

The commands can be grouped into the followingcategories

bull Write Commands (C1C0 = 00) bull Read Commands (C1C0 = 11) bull General Call Commands

The supported commands are shown in Table 7-1These commands allow both single data or continuousdata operation Continuous data operation means thatthe I2C Master does not generate a Stop bit but repeatsthe required dataclocks This allows faster updatessince the overhead of the I2C control byte is removedTable 7-1 also shows the required number of bit clocksfor each commandrsquos different mode of operation

71 Write Commands

Write commands are used to transfer data to thedesired memory location (from the Host controller) Themodes are Single or Continuous The Continuousmode format allows the fastest data update rate for thedevicersquos memory locations

See Section 75 ldquoWrite Commandrdquo for a full descriptionof the write commands

72 Read Commands

Read commands are used to transfer data from thedesired memory location to the Host controller Theread command format writes two bytes (Control byte(RW bit) = 0) and the read command byte (desiredmemory address and the read command) Then aRestart condition is followed by a second control bytebut this control byte indicates an I2C read operation(RW bit = 1) The Master will then supply 16 clocks sothe specified address data are transfered SeeSection 76 ldquoRead Commandrdquo for full a description ofthe read commands

Note The 8-bit data devices use the sameformat as 10-bit and 12-bit devices Thisallows code migration compatibility at thecost of nine extra clock cycles per databyte transferred

TABLE 7-1 DEVICE COMMANDS ndash NUMBER OF CLOCKS

Command

of Bit Clocks(1)

Data Update Rate (8-bit10-bit12-bit)

(Data WordsSecond) CommentsOperation

CodeMode

C1 C0 100 kHz 400 kHz 34 MHz (3)

Write Command(4) 0 0 Single 38 2632 10526 89474

0 0 Continuous 27n + 11 3559 14235 120996 For ten data words

Read Command 1 1 Random 48 2083 8333 70833


1 1 Last Address 29 3448 13793 117241

General Call Reset Command

mdash mdash Single 20 5000 20000 170000 Note 2

General Call Wake-up Command


Note 1 ldquonrdquo indicates the number of times the command operation is to be repeated2 Determined by general call command byte after the I2C general call address 3 There is a minimal overhead to enter into 34 MHz mode4 This command can be at either normal or high voltage A high-voltage command requires the HVC pin to be at

VIHH for the entire command until the completion of the MTP cycle


MCP47CXBXX


The general call commands utilize the I2C specificationreserved general call command address and commandcodes The General Call Reset command format isspecified by the ldquoNXP I2C Specificationrdquo The generalcall wake-up command is a Microchip-defined format

I2C devices Acknowledge the general call addresscommand (0x00 in the first byte) The meaning of thegeneral call address is always specified in the secondbyte The I2C specification does not allow lsquo00000000rsquo(00h) in the second byte Also the lsquo00000100rsquo andlsquo00000110rsquo functionality is defined by the ldquoNXP I2CSpecificationrdquo Lastly a data byte with a lsquo1rsquo in the LSbindicates a ldquoHardware General Callrdquo

Please refer to the ldquoNXP I2C Specificationrdquo for moredetails on the general call specifications

The MCP47CXBXX devices support the following I2Cgeneral calls

bull General Call Reset

bull General Call Wake-up

See Section 771 ldquoGeneral Call Resetrdquo for a fulldescription of the General Call Reset command andthe general call wake-up command

74 Aborting a Transmission

A Restart or Stop condition in an expected data bitposition will abort the current command sequence andif the command is a write that data word will not be writ-ten to the MCP47CXBXX Also the I2C state machinewill be reset

75 Write Command

The write command can be issued to both the volatileand nonvolatile memory locations Write commandscan also be structured as either single or continuousThe continuous format allows the fastest data updaterate for the devicersquos memory locations

The format of the command is shown in Figure 7-1 TheMCP47CXBXX generates the AA bits The format ofthe command is shown in Figure 7-1 (single) andFigure 7-3 (continuous) for example ACKNACKbehavior (see Figure 7-2)

A write command to a volatile memory locationchanges that location after a properly formatted writecommand and the rising edge of the D00 bit (last databit) clock has been detected

A write command to a nonvolatile memory location willonly start a write cycle after a properly formatted writecommand has been received and the Stop conditionhas occurred

751 SINGLE WRITE TO VOLATILE MEMORY

For volatile memory locations data are written to theMCP47CXBXX after every data word transfer (16 bits)during the rising edge of the last data bit If a Stop orRestart condition is generated during a data transfer(before the last data bit is received) the data will not bewritten to the MCP47CXBXX After the A bit the Mastercan initiate the next sequence with a Stop or Restartcondition (See Figure 7-1 for the write sequence)

752 SINGLE WRITE TO NONVOLATILE MEMORY (HVC PIN = VIL OR VIH)

In normal user mode the MTP memory addresscannot be written Writing to the MTP address spacewhile the HVC pin is not at VIHH will not have anyeffect the command is Acknowledged but the memoryis not modified

Note 1 Writes to volatile memory locations willbe dependent on the state of theirrespective WiperLock Technology bits

2 During device communication if thedevice addresscommand combination isinvalid or an unimplemented deviceaddress is specified then the MCP47CX-BXX will NACK that byte To reset the I2Cstate machine the I2C communicationmust detect a Start bit

3 Writes to volatile memory locations willbe dependent on the state of theirrespective WiperLock Technology bits

Note Writes to a Volatile DAC register will nottransfer to the output register until the LAT(HVC) pin is transitioned to the VILvoltage


MCP47CXBXX

753 SINGLE WRITE TO NONVOLATILE MEMORY (HVC PIN = VIHH)

The sequence to write to a single nonvolatile memorylocation is the same as a single write to volatile memorywith the exception that the MTP Write Cycle (twc) isstarted after a properly formatted command includingthe Stop bit is received After the Stop condition occursthe serial interface may immediately be re-enabled byinitiating a Start condition

The HVC pin must be at VIHH until the completion of theMTP Write Cycle (twc)

During an MTP write cycle access to the volatile mem-ory is allowed when using the appropriate commandsequence Commands that address nonvolatile memoryare ignored until the MTP Write Cycle (twc) completesThis allows the Host controller to operate on the VolatileDAC registers

Once a write command to a nonvolatile memorylocation has been received no other commands shouldbe received before the Stop condition occurs

Writes to a NV memory location while an MTP writecycle is occurring will force an error condition (A) AStart bit is required to reset the command statemachine

Figure 7-1 shows the waveform for a single write

FIGURE 7-1 Write Random Address Command

Note Writes to MTP memory require the HVCpin at 75V This is not the normal operat-ing conditions of the device it is designedfor factory programming of configurationparameters

Note If a Stop condition does not occur then theNV Write does not occur and all followingcommand(s) will have an error condition(A) A Start bit is required to reset the com-mand state machine

Memory Address

I2C ACK bit(1)

Note 1 The Acknowledge bit is generated by the MCP47CXBXX

2 At the rising edge of the SCL signal for the last bit (D00) of the write command the device updates the value of the specified device register For DAC Output registers the output voltage depends on the state of the LAT pin

3 This command sequence does not need to terminate (using the Stop bit) and the write command can be repeated (see continuous write format Section 754 ldquoContinuous Writes to Volatile Memoryrdquo)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

0 0 x A

ADn

D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA

A

P

S xSAn

0 0

I2C Start Bit

I2C Slave Address

I2C Write Bit Write Command

Reserved should be Set to lsquo0rsquo

I2C Stop Bit(3)

Dnn Register Data (to be written)(2)

Control Byte Write Command

Data to Write MSB Data to Write LSB

Legend


MCP47CXBXX

754 CONTINUOUS WRITES TO VOLATILE MEMORY

A Continuous Write mode of operation is possible whenwriting to the devicersquos Volatile Memory registers (seeTable 7-2) This Continuous Write mode allows writeswithout a Stop or Restart condition or repeated trans-missions of the I2C control byte Figure 7-3 shows thesequence for three continuous writes The writes do notneed to be to the same volatile memory address Thesequence ends with the Master sending a Stop orRestart condition

755 CONTINUOUS WRITES TO NONVOLATILE MEMORY

If a continuous write is attempted on nonvolatilememory the missing Stop condition will cause thecommand to be an error condition (A) on all followingbytes A Start bit is required to reset the command statemachine

FIGURE 7-2 I2C ACKNACK Behavior (Write Command Example)

TABLE 7-2 VOLATILE MEMORY ADDRESSES

Address Single Channel Dual Channel

00h Yes Yes

01h No Yes

08h Yes Yes

09h Yes Yes

0Ah Yes Yes

Note All bytes are ignored and not transferredto memory

Write 1 Word Command

S Slave Address

RW

AC

K

Command

AC

K

Data Byte

AC

K

Data Byte

AC

K

P

Master S

SA

6S

A5

SA

4S

A3

SA

2S

A1

SA

0

0 AA

AD

4A

D3

AD

2A

D1

AD

0C

1C

0 x AA

D15

D14

D13

D12

D11

D10

D09

D08 AA

D07

D06

D05

D04

D03

D02

D01

D00 AA P

Example 1 (No Command Error)

Master S 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 x 1 d d d d d d d d 1 d d d d d d d d 1 P

MCP47CXBXX 0 0 0 0

I2C Bus S 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 x 0 d d d d d d d d 0 d d d d d d d d 0 P

Example 2 (Command Error)


MCP47CXBXX 0 1 1 1


Note Once a command error has occurred (Example 2) the MCP47CVBXX will NACK until a Start condition occurs


MCP47CXBXX

FIGURE 7-3 Continuous Write Commands (Volatile Memory Only)


2 At the falling edge of the SCL pin for the write command ACK bit the MCP47CXBXX device updates the value of the specified device register


4 Only functions when writing to Volatile registers (AD4AD0 = 00h through 0Ah)

D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


AD4

AD3

AD2

AD1

AD0

0 0 x A

Write Command

P

AD4

AD3

AD2

AD1

AD0

0 0 x A

Write Command

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0 AAD4

AD3

AD2

AD1

AD0

0 0 x A


Memory Address

I2C ACK Bit (1)

0

ADn

A

P

S x

SAn

0 0

I2C Start Bit

I2C Slave Address



I2C Stop Bit(3)


Legend


MCP47CXBXX

76 Read Command

Read commands are used to transfer data from thespecified memory location to the Host controller

The read command can be issued to both the volatileand nonvolatile memory locations During an MTPmemory write cycle the read command can only readthe volatile memory locations By reading the StatusRegister (0Ah) the Host controller can determinewhen the Write Cycle (twc) has been completed (viathe state of the MTPMA bit)

The read command formats include

bull Single Read

- Single Memory Address

- Last Memory Address Accessed

bull Continuous Reads

The MCP47CXBXX retains the last received devicememory address This means the MCP47CXBXX doesnot corrupt the device memory address after RepeatedStart or Stop conditions

761 SINGLE READ

The read command format writes two bytes the controlbyte and the read command byte (desired memoryaddress and the read command) and then has aRestart condition Then a second control byte istransmitted but this control byte indicates an I2C readoperation (RW bit = 1)

7611 Single Memory Address

Figure 7-4 shows the sequence for reading a specifiedmemory address

7612 Last Memory Address Accessed

This is useful for checking the status of the MTPMA bitor when writes to other I2C devices on the bus mustoccur between these memory reads The Master mustsend a Stop or Restart condition after the data word issent from the Slave Figure 7-5 shows the waveformsfor a single read of the last memory location accessed

762 CONTINUOUS READS

Continuous reads allow the devicersquos memory to beread quickly and are valid for all memory locations

Figure 7-7 shows the sequence for three continuousreads

For continuous reads instead of transmitting a Stop orRestart condition after the data transfer the Mastercontinually reads the data byte The sequence endswith the Master Not Acknowledging and then sending aStop or Restart

763 IGNORING AN I2C TRANSMISSION AND ldquoFALLING OFFrdquo THE BUS

The MCP47CXBXX expects to receive complete validI2C commands and will assume any command notdefined as a valid command is due to a bus corruptionthus entering a passive high condition on the SDAsignal All signals will be ignored until the next validStart condition and control byte are received

Note 1 During device communication if thedevice addresscommand combination isinvalid or an unimplemented address isspecified the MCP47CXBXX will NACKthat byte To reset the I2C state machinethe I2C communication must detect aStart bit

2 If the LAT pin is high (VIH) reads of theVolatile DAC register return the currentoutput value not the internal registervalue

3 The read commands operate the sameregardless of the state of the High-VoltageCommand (HVC) signal


MCP47CXBXX

FIGURE 7-4 Read Command ndash Single Memory Address

Note 1 The Master device is responsible for the AA signal If an A signal occurs the MCP47CXBXX will abort this transfer and release the bus

2 This Acknowledge bit is generated by the Master device

3 This command sequence does not need to terminate (using the Stop bit) and the read command can be repeated (see Section 762 ldquoContinuous Readsrdquo)

4 The Master device will Not Acknowledge and the MCP47CXBXX will release the bus so the Master device can generate a Stop or Repeated Start condition

5 The MCP47CXBXX retains the last received ldquodevice memory addressrdquo

6 The non-data bits of the Read Data Word will be output as lsquo0rsquosfor 12-bit devices bits D15D12 are lsquo0rsquosfor 10-bit devices bits D15D10 are lsquo0rsquosfor 8-bit devices bits D15D08 are lsquo0rsquos

Memory Address(5)

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

1 1 x A

ADn

A

A

PS

x

SAn

1 1

I2C Start Bit

I2C Slave Address

I2C Write Bit

Read Command

Reserved Set to lsquo0rsquo

I2C Stop Bit(3)

Dnn

Data (read from memory)

Control Byte Read Command

Legend

Sr

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA

Data Read MSB Data Read LSB

SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

Control Byte

A I2C ACK Bit(2)

I2C NACK Bit(4)A

1 I2C Read Bit

Sr I2C Start Bit Repeated


MCP47CXBXX

FIGURE 7-5 Read Command ndash Last Memory Address Accessed





5 The MCP47CXBXX retains the last received ldquoDevice Memory Addressrdquo


7 If the last device address written (via the read or write command) is invalid for a read then the read last memory address command will NACK due to the invalid device memory address

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

1 A

A

P

S

SAn

I2C Start Bit

I2C Slave Address I2C Stop Bit(3)Dnn Data (read from memory)

Control Byte

Legend

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


A I2C ACK Bit(2)

I2C NACK Bit(4)A1 I2C Read Bit


MCP47CXBXX

FIGURE 7-6 I2C ACKNACK Behavior (Read Command Example)

Read 1 Word Command

S Slave Address

RW

AC

K Command

AC

K

Master SS

A6

SA

5S

A4

SA

3S

A2

SA

1S

A0 0 1

AD

4A

D3

AD

2A

D1

AD

0C

1C

0x

1

Sr

Slave Address RW

AC

K

Data Byte AC

K

Data Byte AC

K

P

Master (Continued) Sr

SA

6S

A5

SA

4S

A3

SA

2S

A1

SA

0

1 1

D1

5D

14

D1

3D

12

D11

D1

0D

09

D0

8 1

D0

7D

06

D0

5D

04

D0

3D

02

D0

1D

00 1 P


Master S 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 x 1

MCP47CXBXX 0 0

I2C Bus S 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 x 0

Master (Continued) S 0 0 0 0 1 0 0 1 1 1 1 P

MCP47CXBXX (Continued) 0 d d d d d d d d 0 d d d d d d d d 0

I2C Bus (Continued) S 0 0 0 0 0 0 0 1 0 d d d d d d d d 0 d d d d d d d d 0 P


Master S 1 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 x 1

MCP47CXBXX 0 1

I2C Bus S 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 x 1


MCP47CXBXX (Continued) 0 0 1

I2C Bus (Continued) S 1 1 0 0 0 0 0 1 0 0 1 P

Note 1 Once a command error has occurred (Example 2) the MCP47CXBXX will NACK until a Start condition occurs

2 For command error case (Example 2) the data read is from the register of the last valid address loaded into the device


MCP47CXBXX

FIGURE 7-7 Continuous Read Command of Specified Address







Memory Address(5)

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

1 1 x A

ADn

A

A

PS

x

SAn

1 1

I2C Start Bit

I2C Slave Address

I2C Write Bit

Read Command


I2C Stop Bit(3)

Dnn Data (read from memory)


Legend

Sr

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

Control Byte

A I2C ACK Bit(2)

I2C NACK Bit(4)A

1 I2C Read Bit


0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A



MCP47CXBXX


The MCP47CXBXX Acknowledges the general calladdress command (00h in the first byte) General callcommands can be used to communicate to all deviceson the I2C bus (at the same time) that understand thegeneral call command The meaning of the general calladdress is always specified in the second byte (seeFigure 7-8)

If the second byte has a lsquo1rsquo in the LSb the specificationintends this to indicate a ldquoHardware General Callrdquo TheMCP47CXBXX will ignore this byte and all followingbytes (and A) until a Stop bit (P) is encountered

The MCP47CXBXX devices support the following I2Cgeneral call commands

bull General Call Reset (06h)

bull General Call Wake-up (0Ah)

The General Call Reset command format is specifiedby the I2C Specification The general call wake-upcommand is a Microchip-defined format The generalcall wake-up command will have all devices wake-up(that is exit the Power-Down mode)

The other two I2C specification command codes (04hand 00h) are not supported and therefore thosecommands are Not Acknowledged

If these 7-bit commands conflict with other I2C deviceson the bus the user will need two I2C buses to ensurethat the devices are on the correct bus for their desiredapplication functionality

FIGURE 7-8 General Call Formats

Note Refer to the ldquoNXP SpecificationrdquoUM10204 Rev 03 19 June 2007 docu-ment for more details on the general callspecifications The I2C specification doesnot allow lsquo00000000rsquo (00h) in the secondbyte

S 0 A 0 x x 0 A

General Call Address 7-Bit Command

0 00 0 0 0 0 x P000

I2C ACK Bit(1)A PS x xI2C Start Bit GC Command I2C Stop Bit(23)

Legend

x


2 This command sequence does not need to terminate (using the Stop bit) and the general call com-mand can be repeated or another general call command can be sent Only the first command will be accepted by the MCP47CXBXX


MCP47CXBXX

771 GENERAL CALL RESET

The I2C General Call Reset command forces a resetevent This is similar to the Power-On Reset exceptthat the reset delay timer is not started This commandallows multiple devices to be reset synchronously

The device performs General Call Reset if the secondbyte is lsquo00000110rsquo (06h) At the acknowledgment ofthis byte the device will perform the following tasks

bull Internal reset similar to a POR The contents of the MTP are loaded into the DAC registers

bull Analog output (VOUT) is available after the POR sequence has been completed

772 GENERAL CALL WAKE-UP

The I2C General Call Wake-Up command forces thedevice to exit from its Power-Down state (forces thePDxBPDxA bits to lsquo00rsquo) This command allows multipleMCP47CXBXX devices to wake up synchronously

The device performs General Call Wake-Up if thesecond byte (after the General Call Address) islsquo00001010rsquo (0Ah) At the acknowledgment of this bytethe device will perform the following task

bull The devicersquos volatile power-down bits (PDxBPDxA) are forced to lsquo00rsquo

FIGURE 7-9 General Call Reset Command

FIGURE 7-10 General Call Wake-up Command


2 At the falling edge of the SCL pin for the General Call Reset command ACK bit theMCP47CXBXX device is reset

3 This command sequence does not need to terminate (using the Stop bit) and the General Call Reset command can be repeated or the general call wake-up command can be sent Only the first command will be accepted by the MCP47CXBXX

S 0 A 0 1 1 0 A


0 00 0 0 0 0 0 P000

I2C ACK Bit(1) A PS 1 1I2C Start Bit Reset Command I2C Stop Bit(23)

Legend

0


2 At the rising edge of the last data bit for the general call wake-up command the volatile Power-Down bits (PDxBPDxA) are forced to lsquo00rsquo

3 This command sequence does not need to terminate (using the Stop bit) and the general call wake-up command can be repeated or the General Call Reset command can be sent

S 0 A 0 0 1 0 A


0 00 0 0 0 0 1 P000

I2C ACK Bit(1)A PS 0 1I2C Start Bit Reset Command I2C Stop Bit(3)

Legend

1


MCP47CXBXX

80 TYPICAL APPLICATIONS

The MCP47CXBXX devices are general purposesingledual channel voltage output DACs for variousapplications where a precision operation with lowpower is needed

Applications generally suited for the devices are



bull Portable Instrumentation (Battery-Powered)

bull Motor Control

81 Connecting to the I2C Bus Using Pull-up Resistors

The SCL and SDA pins of the MCP47CXBXX devicesare open-drain configurations These pins require apull-up resistor as shown in Figure 8-2

The pull-up resistor values (R1 and R2) for SCL andSDA pins depend on the operating speed (standardfast and high speed) and loading capacitance of the I2Cbus line A higher value of the pull-up resistor consumesless power but increases the signal transition time(higher RC time constant) on the bus line therefore itcan limit the bus operating speed The lower resistorvalue on the other hand consumes higher power butallows higher operating speed If the bus line has highercapacitance due to long metal traces or multiple deviceconnections to the bus line a smaller pull-up resistor isneeded to compensate for the long RC time constantThe pull-up resistor is typically chosen between 1 kand 10 kranges for Standard and Fast modes andless than 1 kfor High-Speed mode

811 DEVICE CONNECTION TEST

The user can test the presence of the device on the I2Cbus line using a simple I2C command This test can beachieved by checking an Acknowledge response fromthe device after sending a read or write commandFigure 8-1 shows an example with a read commandThe steps are

1 Set the RW bit ldquoHighrdquo in the devicersquos address byte

2 Check the ACK bit of the address byte If the device Acknowledges (ACK = 0) thecommand then the device is connectedotherwise it is not connected

3 Send Stop bit

FIGURE 8-1 I2C Bus Connection Test

1 2 3 4 5 6 7 8 9SCL

SDA A2 A1 A0 1StartBit

Address Byte

Address Bits

RW

StopBit

Device

AC

K

Response

A3A4A5A6


MCP47CXBXX

82 Power Supply Considerations

The power source should be as clean as possible Thepower supply to the device is also used for the DACvoltage reference internally if the internal VDD isselected as the resistor ladderrsquos reference voltage(VRxBVRxA = 00)

Any noise induced on the VDD line can affect the DACperformance Typical applications will require a bypasscapacitor in order to filter out high-frequency noise onthe VDD line The noise can be induced onto the powersupplyrsquos traces or as a result of changes on the DAC out-put The bypass capacitor helps to minimize the effect ofthese noise sources on signal integrity Figure 8-2shows an example of using two bypass capacitors (a10 microF tantalum capacitor and a 01 microF ceramic capaci-tor) in parallel on the VDD line These capacitors shouldbe placed as close to the VDD pin as possible (within4 mm) If the application circuit has separate digital andanalog power supplies the VDD and VSS pins of thedevice should reside on the analog plane

FIGURE 8-2 Example Circuit

5

Analog

VDD

1

2

3

8

6

VDD SDA

SCL

VSS

VOUT0

7

R1 R2

To MCU

R1 and R2 are I2C pull-up resistors

R1 and R2

5 k-10 k for fSCL = 100 kHz to 400 kHz

~700 for fSCL = 34 MHz

C1 01 microF capacitor = Ceramic

C2 10 microF capacitor = Tantalum

C3 ~ 01 microF = Optional to reduce noise in VOUT pin




C2C1

MCP47CVBX2

Optional

(a) Circuit when VDD is selected as reference

Note VDD is connected to the reference circuit internally

(b) Circuit when external reference is used

Output

VREF

4 5

LATHVC

VOUT1

C4C3

Analog

VDD

1

2

3

8

6

VDD SDA

SCL

VSS

VOUT0

7To MCU

C2C1

MCP47CVBX2

Optional

Output

VREF

4

LATHVC

VOUT1

C5

Optional

VREF

C6

R1 R2

C4C3


MCP47CXBXX

83 Application Examples

The MCP47CXBXX devices are rail-to-rail outputDACs designed to operate with a VDD range of 27V to55V The internal output amplifier is robust enough todrive common small signal loads directly thuseliminating the cost and size of the external buffers formost applications The user can use the gain of 1 or 2of the output op amp by setting the Configurationregister bits The internal VDD or an external referencecan be used There are various user options and easy-to-use features that make the devices suitable forvarious modern DAC applications

Application examples include

bull Decreasing Output Step-Size

bull Building a ldquoWindowrdquo DAC

bull Bipolar Operation

bull Selectable Gain and Offset Bipolar Voltage Output

bull Designing a Double Precision DAC

bull Building Programmable Current Source

bull Serial Interface Communication Times

bull Software I2C Interface Reset Sequence

bull Power Supply Considerations

bull Layout Considerations

831 DC SET POINT OR CALIBRATION

A common application for the devices is a digitallycontrolled set point andor calibration of variableparameters such as sensor offset or slope Forexample the MCP47CVB2X provides 4096 outputsteps If the voltage reference is 4096V (where Gx = 0)the LSb size is 1 mV If a smaller output step-size isdesired a lower external voltage reference is needed

8311 Decreasing Output Step-Size

If the application is calibrating the bias voltage of adiode or transistor a bias voltage range of 08V may bedesired with about 200 microV resolution per step Twocommon methods to achieve small step-size are to usea lower VREF pin voltage or a voltage divider on theDACrsquos output

Using an external Voltage Reference (VREF) is anoption if the external reference is available with thedesired output voltage range However when using alow-voltage reference voltage occasionally the noisefloor causes an SNR error that is intolerable Using avoltage divider method is another option and providessome advantages when external voltage referenceneeds to be very low or when the desired outputvoltage is not available In this case a larger valuereference voltage is used while two resistors scale theoutput range down to the precise desired level

Figure 8-3 illustrates this concept A bypass capacitoron the output of the voltage divider plays a criticalfunction in attenuating the output noise of the DAC andthe induced noise from the environment

FIGURE 8-3 Example Circuit of Set Point or Threshold Calibration

EQUATION 8-1 VOUT AND VTRIP CALCULATIONS

R1

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

VOR2 C1

RSENSE

Comp

VDD

VTRIP

Vtrip VOUT

R2R1 R2+--------------------

=

VOUT = VREF bull G bull DAC Register Value

2N


MCP47CXBXX

8312 Building a ldquoWindowrdquo DAC

When calibrating a set point or threshold of a sensortypically only a small portion of the DAC output range isutilized If the LSb size is adequate enough to meet theapplicationrsquos accuracy needs the unused range issacrificed without consequences If greater accuracy isneeded then the output range will need to be reducedto increase the resolution around the desired threshold

If the threshold is not near VREF 2 bull VREF or VSS thencreating a ldquowindowrdquo around the threshold has severaladvantages One simple method to create this ldquowindowrdquois to use a voltage divider network with a pull-up andpull-down resistor Figure 8-4 and Figure 8-6 illustratethis concept

FIGURE 8-4 Single-Supply ldquoWindowrdquo DAC


84 Bipolar Operation

Bipolar operation is achievable by utilizing an externaloperational amplifier This configuration is desirabledue to the wide variety and availability of op amps Thisallows a general purpose DAC with its cost andavailability advantages to meet almost any desiredoutput voltage range power and noise performance

Figure 8-5 illustrates a simple bipolar voltage sourceconfiguration R1 and R2 allow the gain to be selectedwhile R3 and R4 shift the DACs output to a selectedoffset Note that R4 can be tied to VDD instead of VSS ifa higher offset is desired

FIGURE 8-5 Digitally Controlled Bipolar Voltage Source Example Circuit

EQUATION 8-3 VOUT VOA+ AND VO CALCULATIONS

R1

VCC+

VCC-

VO

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

VOUTR2 C1

R3

VCC+

VCC-

RSENSE

CompVTRIP

R23

R2R3

R2 R3+-------------------=

V23

VCC+R2 VCC-R3 +

R2 R3+------------------------------------------------------=

VTRIP

VOUTR23 V23R1+

R1 R23+---------------------------------------------------=

TheveninEquivalent

R1

R23

V23

VOUT VTRIP


2N

R3

VCC+

VCC-

VO

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

R2

VOUT

VIN

R1

R4 C1

VOA+

VOA+ = VOUT bull R4

R3 + R4


2N

VO = VOA+ bull (1 + ) ndash VDD bull ( ) R2

R1

R2

R1


MCP47CXBXX

85 Selectable Gain and Offset Bipolar Voltage Output

In some applications precision digital control of theoutput range is desirable Figure 8-6 illustrates how touse the DAC devices to achieve this in a bipolar orsingle-supply application

This circuit is typically used for linearizing a sensorwhose slope and offset varies

The equation to design a bipolar ldquowindowrdquo DAC wouldbe utilized if R3 R4 and R5 are populated

851 BIPOLAR DAC EXAMPLE

An output step-size of 1 mV with an output range ofplusmn205V is desired for a particular application

The equation can be simplified to

EQUATION 8-4

EQUATION 8-5

FIGURE 8-6 Bipolar Voltage Source with Selectable Gain and Offset


EQUATION 8-7 BIPOLAR ldquoWINDOWrdquo DAC USING R4 AND R5

Step 1 Calculate the range +205V ndash (-205V) = 41V

Step 2 Calculate the resolution needed

41V1 mV = 4100

Since 212 = 4096 12-bit resolution is desired

Step 3 The amplifier gain (R2R1) multiplied byfull-scale VOUT (4096V) must be equal tothe desired minimum output to achieve bipo-lar operation Since any gain can be realizedby choosing resistor values (R1 + R2) theVREF value must be selected first If a VREFof 4096V is used solve for the amplifierrsquosgain by setting the DAC to 0 knowing thatthe output needs to be -205V

Step 4 Next solve for R3 and R4 by setting theDAC to 4096 knowing that the outputneeds to be +205V

R2ndash

R1---------

205ndash4096V-----------------=

If R1 = 20 k and R2 = 10 k the gain will be 05

R2

R1------

12---=

R4

R3 R4+ ------------------------

205V 05 4096V +15 4096V

-------------------------------------------------------23---= =

If R4 = 20 k then R3 = 10 k

R3

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

R2

VO

VIN

R1

R4C1

R5

Optional

VOA+

VCC+

VCC-

C1 = 01 microF

Offset Adjust Gain Adjust


2N

VOA+ = VOUT bull R4 + VCC- bull R5

R3 + R4

VO = VOA+ bull (1 + ) ndash VIN bull ( ) R2

R1

R2

R1

TheveninEquivalent V45

VCC+R4 VCC-R5+

R4 R5+---------------------------------------------=

VIN+

VOUTR45 V45R3+

R3 R45+---------------------------------------------=

R45

R4R5

R4 R5+-------------------=

VO VIN+ 1R2

R1------+

VA

R2

R1------ ndash=



MCP47CXBXX

86 Designing a Double Precision DAC

Figure 8-7 shows an example design of a single-supplyvoltage output capable of up to 24-bit resolution Thisrequires two 12-bit DACs This design is simply avoltage divider with a buffered output

As an example if a similar application to the onedeveloped in Section 851 ldquoBipolar DAC Examplerdquorequired a resolution of 1 microV instead of 1 mV and arange of 0V to 41V then 12-bit resolution would not beadequate

FIGURE 8-7 Simple Double Precision DAC Using MCP47CVBX2

EQUATION 8-8 VOUT CALCULATION

87 Building Programmable Current Source

Figure 8-8 shows an example of building aprogrammable current source using a voltage followerThe current sensor resistor is used to convert the DACvoltage output into a digitally-selectable current source

The smaller RSENSE is the less power is dissipatedacross it However this also reduces the resolution thatthe current can be controlled at

FIGURE 8-8 Digitally-Controlled Current Source

88 Serial Interface Communication Times

Table 7-1 shows the timefrequency of the supportedoperations of the I2C serial interface for the differentserial interface operational frequencies This alongwith the VOUT output performance (such as slew rate)would be used to determine your applicationrsquos VolatileDAC register update rate


41V1 microV = 41 x 106 Since 222 = 42 x 106 a 22-bit resolution isdesired Since DNL = plusmn10 LSb this designcan be attempted with the 12-bit DAC

Step 2 Since DAC1rsquos VOUT1 has a resolution of1 mV its output only needs to be ldquopulledrdquo11000 to meet the 1 microV target DividingVOUT0 by 1000 would allow the applicationto compensate for DAC1rsquos DNL error

Step 3 If R2 is 100 then R1 needs to be 100 k

Step 4 The resulting transfer function is shown inEquation 8-8

R1

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBX2

VDD

I2C2-Wire

VREF

Optional

MCP47CVBX2

VDD

R2

01 microF

VOUT0

VOUT1

(DAC0)

(DAC1)

VOUT =

Gx = Selected Op Amp Gain

VOUT0 R2 + VOUT1 R1

R1 + R2

VOUT0 = (VREF Gx DAC0 Register Value)4096 VOUT1 = (VREF Gx DAC1 Register Value)4096

Where

RSENSE

Ib

Load

IL

VCC+

VCC-

VOUT

IL

VOUT

Rsense---------------

1+-------------=

Ib

IL

----=

Common Emitter Current GainWhere

VDD

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

(or VREF)


MCP47CXBXX

89 Software I2C Interface Reset Sequence

At times it may become necessary to perform aSoftware Reset sequence to ensure the MCP47CXBXXdevice is in a correct and known I2C interface state Thistechnique only resets the I2C state machine

This is useful if the MCP47CXBXX device powers up inan incorrect state (due to excessive bus noise etc) orif the Master device is reset during communicationFigure 8-9 shows the communication sequence tosoftware reset the device

FIGURE 8-9 Software Reset Sequence Format

The first Start bit will cause the device to reset from astate in which it is expecting to receive data from theMaster device In this mode the device is monitoringthe data bus in Receive mode and can detect if theStart bit forces an internal Reset

The nine bits of lsquo1rsquo are used to force a reset of thosedevices that could not be reset by the previous Start bitThis occurs only if the MCP47CXBXX is driving an A biton the I2C bus or is in Output mode (from a readcommand) and is driving a data bit of lsquo0rsquo onto the I2Cbus In both of these cases the previous Start bit couldnot be generated due to the MCP47CXBXX holding thebus low By sending out nine lsquo1rsquo bits it is ensured that thedevice will see an A bit (the Master device does not drivethe I2C bus low to Acknowledge the data sent by theMCP47CXBXX) which also forces the MCP47CXBXX toreset

The second Start bit is sent to address the rarepossibility of an erroneous write This could occur if theMaster device was reset while sending a write com-mand to the MCP47CXBXX and then as the Masterdevice returns to normal operation and issues a Startcondition while the MCP47CXBXX is issuing anAcknowledge In this case if the second Start bit is notsent (and the Stop bit was sent) the MCP47CXBXXcould initiate a write cycle

The Stop bit terminates the current I2C bus activity TheMCP47CXBXX waits to detect the next Start condition

This sequence does not affect any other I2C deviceswhich may be on the bus as they should disregard thisas an invalid command

810 Design Considerations

In the design of a system with the MCP47CXBXXdevices the following considerations should be takeninto account



8101 POWER SUPPLY CONSIDERATIONS

The typical application requires a bypass capacitor inorder to filter high-frequency noise which can beinduced onto the power supplyrsquos traces The bypasscapacitor helps to minimize the effect of these noisesources on signal integrity Figure 8-10 illustrates anappropriate bypass strategy

In this example the recommended bypass capacitorvalue is 01 microF This capacitor should be placed as close(within 4 mm) to the device power pin (VDD) as possible

The power source supplying these devices should beas clean as possible If the application circuit hasseparate digital and analog power supplies VDD andVSS should reside on the analog plane

FIGURE 8-10 Typical Microcontroller Connections

Note This technique is documented in AN1028ldquoRecommended Usage of Microchip I2CSerial EEPROM Devicesrdquo (DS01028)

Note The potential for this erroneous writeONLY occurs if the Master device is resetwhile sending a write command to theMCP47CVBXX

S lsquo1rsquo lsquo1rsquo lsquo1rsquo lsquo1rsquo lsquo1rsquo lsquo1rsquo lsquo1rsquo lsquo1rsquo S P

Start

Nine Bits of lsquo1rsquo

Start BitStop BitBit

VDD

VDD

VSS VSS

MC

P4

7CX

BX

X

01 microFP

ICreg

Mic

roc

on

tro

lle

r

01 microF

SCL

VOUT

VREF SDA


MCP47CXBXX

8102 LAYOUT CONSIDERATIONS

Several layout considerations may be applicable toyour application These may include

bull Noise

bull PCB Area Requirements

81021 Noise

Inductively coupled AC transients and digital switchingnoise can degrade the input and output signal integritypotentially masking the MCP47CXBXX devicersquos perfor-mance Careful board layout minimizes these effectsand increases the Signal-to-Noise Ratio (SNR) Multi-layer boards utilizing a low-inductance ground planeisolated inputs isolated outputs and proper decouplingare critical to achieving the performance that the silicon iscapable of providing Particularly harsh environmentsmay require shielding of critical signals

Separate digital and analog ground planes arerecommended In this case the VSS pin and the groundpins of the VDD capacitors should be terminated to theanalog ground plane

81022 PCB Area Requirements

In some applications PCB area is a criteria for deviceselection Table 8-1 shows the typical packagedimensions and area for the different package options

Note Breadboards and wire-wrapped boardsare not recommended

TABLE 8-1 PACKAGE FOOTPRINT(1)

Package Package Footprint

Pin

s

Type Code

Dimensions (mm) Area (mm2)

Length Width

10 MSOP UN 300 490 1470

10 DFN MF 300 300 900

16 QFN MG 300 300 900

Note 1 Does not include recommended land pattern dimensions Dimensions are typical values


MCP47CXBXX

90 DEVELOPMENT SUPPORT

Development support can be classified into two groups

bull Development Tools

bull Technical Documentation

91 Development Tools

Several development tools are available to assist in yourdesign and evaluation of the MCP47CXBXX devicesThe currently available tools are shown in Table 9-1

Figure 9-1 shows how the ADM00309 bond-out PCBcan be populated to easily evaluate the MCP47CXBXXdevices Device evaluation can use the PICkittrade SerialAnalyzer to control the DAC Output registers and stateof the Configuration Control and Status registers

The ADM00309 boards may be purchased directlyfrom the Microchip web site at wwwmicrochipcom

92 Technical Documentation

Several additional technical documents are available toassist you in your design and development Thesetechnical documents include Application NotesTechnical Briefs and Design Guides Table 9-2 listssome of these documents

TABLE 9-1 DEVELOPMENT TOOLS(1)

Board Name Part Comment

MSOP-8 and MSOP-10 Evaluation Board ADM00309 The MSOP-8 and MSOP-10 Evaluation Board is a bond-out board that allows the system designer to quickly evaluate the operation of Microchip Technologyrsquos devices in any of the following packagesbull MSOP (810-pin)bull DIP (10 pin)

Note 1 Supports the PICkittrade Serial Analyzer See the Userrsquos Guide for additional information and requirements

TABLE 9-2 TECHNICAL DOCUMENTATION

Application Note Number

Title Literature

AN1326 Using the MCP4728 12-Bit DAC for LDMOS Amplifier Bias Control Applications DS01326

mdash Signal Chain Design Guide DS21825

mdash Analog Solutions for Automotive Applications Design Guide DS01005


MCP47CXBXX

FIGURE 9-1 MCP47CXBXX Evaluation Board Circuit Using ADM00309

0

47k

Two Wire Jumpers to Connect thePICkittrade Serial Interface (I2C) to Device Pins

1 x 6 Male Header with 90deg Right Angle

MCP47CVBXX in MSOP-10 PackageInstalled in U1 Footprint

Connected toDigital Ground Connected to

Digital Power (VL) Plane

VDD SDA

SCL

(DGND) Plane

NCVOUT1 LATHVC

VSS

10 microF 47k

VOUT0

VREF

47Cx

Bxx

0

A1

A0


MCP47CXBXX

100 PACKAGING INFORMATION

101 Package Marking Information

Legend XXX Customer-specific informationY Year code (last digit of calendar year)YY Year code (last 2 digits of calendar year)WW Week code (week of January 1 is week lsquo01rsquo)NNN Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free The Pb-free JEDEC designator ( )

can be found on the outer packaging for this package

Note In the event the full Microchip part number cannot be marked on one line it willbe carried over to the next line thus limiting the number of availablecharacters for customer-specific information

3e

3e

Part Number Code

MCP47CVB01-EMF BAJU

MCP47CVB11-EMF BAJX

MCP47CVB21-EMF BAJZ

MCP47CVB02-EMF BAJV

MCP47CVB12-EMF BAJY

MCP47CVB22-EMF BAKA

MCP47CMB01-EMF BAJV

MCP47CMB11-EMF BAJQ

MCP47CMB21-EMF BAJS

MCP47CMB02-EMF BAJP

MCP47CMB12-EMF BAJR

MCP47CMB22-EMF BAJT

XXXXXX

10-Lead MSOP

YWWNNN47CV01

Example

935256

XXXX

10-Lead DFN (3x3 mm)

PIN 1

YYWWNNN

BAJU

Example

PIN 1

1935256


MCP47CXBXX

Part Number Code

MCP47CVB02-EMG AAD

MCP47CVB12-EMG AAE

MCP47CVB22-EMG AAF

MCP47CMB02-EMG AAA

MCP47CMB12-EMG AAB

MCP47CMB22-EMG AAC

XXX

16-Lead QFN (3x3 mm)

PIN 1

XYYWWNNN

Note For MCP47CVB02 MCP47CVB12 MCP47CVB22 MCP47CMB02 MCP47CMB12 and MCP47CMB22) devices

AAD

Example

PIN 1

1935256


MCP47CXBXX

Note For the most current package drawings please see the Microchip Packaging Specification located at httpwwwmicrochipcompackaging

UN


MCP47CXBXX


UN


MCP47CXBXX

10-Lead Plastic Micro Small Outline Package (UN) [MSOP]



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX

NOTES


MCP47CXBXX

APPENDIX A REVISION HISTORY

Revision B (June 2019)

bull Corrected the Internal Band Gap voltage throughout the document

bull Updated the Block Diagrams

bull Updated DC Characteristics table

bull Added Section 112 Latch Pin (LAT) Timing

bull Updated Figure 1-3 Figure 1-4 and Figure 4-1

bull Updated Table 1-3 Table 1-5 Table 3-2 and Table 4-1

bull Updated Section 35 ldquoLatchHigh-Voltage Command Pin (LATHVC)rdquo

bull Updated Section 422 ldquoNonvolatile Register Memory (MTP)rdquo

bull Updated Section 523 ldquoUsing an External VREF Source in Buffered Moderdquo

bull Updated Section 532 ldquoOutput Voltagerdquo

bull Various typographical edits

Revision A (September 2018)

bull Original release of this document


MCP47CXBXX

NOTES


MCP47CXBXX

APPENDIX B I2C SERIAL INTERFACE

This I2C is a two-wire interface that allows multipledevices to be connected to the two-wire bus Figure B-1shows a typical I2C interface connection

FIGURE B-1 Typical I2C Interface

B1 Overview

A device that sends data onto the bus is defined as atransmitter and a device receiving data is defined as areceiver The bus has to be controlled by a Masterdevice which generates the Serial Clock (SCL) con-trols the bus access and generates the Start and Stopconditions Devices that do not generate a serial clockwork as Slave devices Both Master and Slave canoperate as transmitter or receiver but the Masterdevice determines which mode is activated Communi-cation is initiated by the Master (microcontroller) whichsends the Start bit followed by the Slave address byteThe first byte transmitted is always the Slave addressbyte which contains the device code the address bitsand the RW bit

The I2C interface specifies different communication bitrates These are referred to as Standard Fast or High-Speed modes and the MCP47CXBXX supports thesethree modes The clock rates (bit rate) of these modesare




The I2C protocol supports two addressing modes

bull 7-Bit Slave Addressing

bull 10-Bit Slave Addressing (allows more devices on the I2C bus)

Only 7-Bit Slave Addressing will be discussed in thissection

The I2C serial protocol allows multiple Master deviceson the I2C bus This is referred to as ldquoMulti-Masterrdquo Forthis all Master devices must support Multi-Masteroperation In this configuration all Master devices mon-itor their communication If they detect that they wish totransmit a bit that is a logic high but is detected as alogic low (some other Master device driving) they ldquogetoffrdquo the bus That is they stop their communication andcontinue to listen to determine if the communication isdirected towards them

The I2C serial protocol only defines the field types fieldlengths timings etc of a frame The frame contentdefines the behavior of the device For details on theframe content (commandsdata) refer to Section 70Device Commands

The I2C serial protocol defines some commands calledldquoGeneral Call Addressingrdquo which allow the Masterdevice to communicate to all Slave devices on the I2Cbus

SCL SCL

Slave

SDA SDA

Master


Other Devices

Note Refer to the ldquoNXP SpecificationUM10204rdquo Rev 06 4 April 2014document for more details on theI2C specifications


MCP47CXBXX

B2 Signal Descriptions

The I2C interface uses two pins (signals) These are

bull SDA (Serial Data)bull SCL (Serial Clock)

B21 SERIAL DATA (SDA)

The Serial Data (SDA) signal is the data signal of thedevice The value on this pin is latched on the risingedge of the SCL signal when the signal is an input

With the exception of the Start (Restart) and Stop con-ditions the high or low state of the SDA pin can onlychange when the clock signal on the SCL pin is lowDuring the high period of the clock the SDA pinrsquos value(high or low) must be stable Changes in the SDA pinrsquosvalue while the SCL pin is high will be interpreted as aStart or a Stop condition

B22 SERIAL CLOCK (SCL)

The Serial Clock (SCL) signal is the clock signal of thedevice The rising edge of the SCL signal latches thevalue on the SDA pin

Depending on the Clock Rate mode the interface willdisplay different characteristics

B3 I2C Operation

B31 I2C BIT STATES AND SEQUENCE

Figure B-8 shows the I2C transfer sequence whileFigure B-7 shows the bit definitions The serial clock isgenerated by the Master The following definitions areused for the bit states

bull Start Bit (S)bull Data Bitbull Acknowledge (A) Bit (driven low)

No Acknowledge (A) bit (not driven low)bull Repeated Start Bit (Sr)bull Stop Bit (P)

B311 Start Bit

The Start bit (see Figure B-2) indicates the beginning ofa data transfer sequence The Start bit is defined as theSDA signal falling when the SCL signal is ldquohighrdquo

FIGURE B-2 Start Bit

B312 Data Bit

The SDA signal may change state while the SCL signalis low While the SCL signal is high the SDA signalMUST be stable (see Figure B-3)

FIGURE B-3 Data Bit

B313 Acknowledge (A) Bit

The A bit (see Figure B-4) is typically a response fromthe receiving device to the transmitting deviceDepending on the context of the transfer sequence theA bit may indicate different things Typically the Slavedevice will supply an A response after the Start bit andeight ldquodatardquo bits have been received An A bit has theSDA signal low while the A bit has the SDA signal high

FIGURE B-4 Acknowledge Waveform

Table B-1 shows some of the conditions where theSlave device issues the A or Not A (A)

If an error condition occurs (such as an A instead of A)then a Start bit must be issued to reset the commandstate machine

SDA

SCL

S

1st Bit 2nd Bit

TABLE B-1 MCP47CXBXX AA RESPONSES

EventAcknowledge Bit Response

Comment

General Call A

Slave Address Valid

A

Slave Address Not Valid

A

Bus Collision NA I2C module resets or is a ldquoDonrsquot Carerdquo if the collision occurs on the Masterrsquos ldquoStart bitrdquo

SDA

SCL

Data Bit

1st Bit 2nd Bit

A

8

D0

9

SDA

SCL


MCP47CXBXX

B314 Repeated Start Bit

The Repeated Start bit (see Figure B-5) indicates thecurrent Master device wishes to continue communicat-ing with the current Slave device without releasing theI2C bus The Repeated Start condition is the same asthe Start condition except that the Repeated Start bitfollows a Start bit (with the Data bits + A bit) and not aStop bit

The Start bit is the beginning of a data transfersequence and is defined as the SDA signal falling whenthe SCL signal is ldquohighrdquo

FIGURE B-5 Repeated Start Condition Waveform

B315 Stop Bit

The Stop bit (see Figure B-6) Indicates the end of theI2C data transfer sequence The Stop bit is defined asthe SDA signal rising when the SCL signal is ldquohighrdquo

A Stop bit should reset the I2C interface of the Slavedevice

FIGURE B-6 Stop Condition Receive or Transmit Mode

B32 CLOCK STRETCHING

ldquoClock Stretchingrdquo is something the receiving devicecan do to allow additional time to ldquorespondrdquo to theldquodatardquo that has been received

B33 ABORTING A TRANSMISSION

If any part of the I2C transmission does not meet thecommand format it is aborted This can be intentionallyaccomplished with a Start or Stop condition This is doneso that noisy transmissions (usually an extra Start or Stopcondition) are aborted before they corrupt the device

FIGURE B-7 Typical 8-Bit I2C Waveform Format

FIGURE B-8 I2C Data States and Bit Sequence

Note 1 A bus collision during the Repeated Startcondition occurs if

bull SDA is sampled low when SCL goes from low-to-high

bull SCL goes low before SDA is asserted low This may indicate that another Master is attempting to transmit a data lsquo1rsquo

SDA

SCL

Sr = Repeated Start

1st Bit

SCL

SDA AA

P

1st Bit

SDA

SCL

S 2nd Bit 3rd Bit 4th Bit 5th Bit 6th Bit 7th Bit 8th Bit PAA

SCL

SDA

StartCondition

StopCondition

Data Allowedto Change

Data orA Valid


MCP47CXBXX

B34 SLOPE CONTROL

As the device transitions from High-Speed (HS) mode toFats (FS) mode the slope control parameter will changefrom the HS specification to the FS specification

For FS and HS modes the device has a spikesuppression and a Schmitt Trigger at SDA and SCLinputs

B35 DEVICE ADDRESSING

The I2C Slave address control byte is the first bytereceived following the Start condition from the Masterdevice This byte has seven bits to specify the Slaveaddress and the readwrite control bit

Figure B-9 shows the I2C Slave address byte formatwhich contains the seven address bits and aReadWrite (RW) bit

FIGURE B-9 I2C Slave Address Control Byte

B36 HS MODE

The I2C specification requires that a High-Speed modedevice must be lsquoactivatedrsquo to operate in High-Speed(34 Mbits) mode This is done by the Master sending

a special address byte following the Start bit This byteis referred to as the High-Speed Master Mode Code(HSMMC)




2 High-Speed Master Mode Code (lsquo0000 1xxxrsquo)the lsquoxxxrsquo bits are unique to the HS mode Master


After switching to HS mode the next transferred byte isthe I2C control byte which specifies the device to com-municate with and any number of data bytes plusAcknowledgments The Master device can then eitherissue a Repeated Start bit to address a different device(at high speed) or a Stop bit to return to faststandardbus speed After the Stop bit any other Master device(in a Multi-Master system) can arbitrate for the I2C bus

See Figure B-10 for an illustration of an HS modecommand sequence


B361 Slope Control


B362 Pulse Gobbler


FIGURE B-10 HS Mode Sequence


Address Byte

RW ACK

Acknowledge Bit

7-Bit Slave Address

A6 A5 A4 A3 A2 A1 A0

S A0000 1xxxrsquob Sr ASlave Address AAData

P

S = Start bit

Sr = Repeated Start bit

A = Acknowledge bit

A = Not Acknowledge bit

RW = ReadWrite bit

RW


FS Mode HS Mode

HS Mode Continues

FS Mode

Sr ASlave Address RWHS Select Byte Control Byte CommandData Byte(s)

Control Byte


MCP47CXBXX

B37 GENERAL CALL

The general call is a method the Master device can useto communicate with all other Slave devices In a Multi-Master application the other Master devices areoperating in Slave mode The general call address hastwo documented formats These are shown inFigure B-11

The I2C specification documents three 7-bit commandbytes

The I2C specification does not allow lsquo00000000rsquo (00h)in the second byte Also the lsquo00000100rsquo andlsquo00000110rsquo functionalities are defined by the specifica-tion Lastly a data byte with a lsquo1rsquo in the LSb indicates aldquoHardware General Callrdquo

For details on the operation of the MCP47CXBXXdevicersquos general call commands see Section 73ldquoGeneral Call Commandsrdquo

FIGURE B-11 General Call Formats

Note Only one general call command per issueof the general call control byte Anyadditional general call commands areignored and Not Acknowledged

00 0 0S 0 0 0 0 xx x x xA x x 0 A P

General Call Address

Second Byte

7-Bit Command

Reserved 7-Bit Commands (by I2C Specification ndash ldquoNXP Specification UM10204rdquo Rev 06 4 April 2014)lsquo0000 011rsquobrsquo ndash Reset and Write Programmable Part of Slave Address by Hardwarelsquo0000 010rsquobrsquo ndash Write Programmable Part of Slave Address by Hardware

The Following is a ldquoHardware General Callrdquo Format

00 0 0S 0 0 0 0 xx x x xA x x 1 A


Second Byte

Master Address

xx x x x x x x A P

n Occurrences of (Data + A)

This Indicates a ldquoHardware General Callrdquo


MCP47CXBXX

NOTES


MCP47CXBXX

APPENDIX C TERMINOLOGY

C1 Resolution

The resolution is the number of DAC output states thatdivide the Full-Scale Range (FSR) For the 12-bit DACthe resolution is 212 meaning the DAC code rangesfrom 0 to 4095

C2 Least Significant Bit (LSb)

This is the voltage difference between two successivecodes For a given output voltage range it is divided bythe resolution of the device (Equation C-1) The rangemay be VDD (or VREF) to VSS (ideal) the DAC registercodes across the linear range of the output driver(Measured 1) or full scale to zero scale (Measured 2)

EQUATION C-1 LSb VOLTAGE CALCULATION

C3 Monotonic Operation

The monotonic operation means that the devicersquosOutput Voltage (VOUT) increases with every one codestep (LSb) increment (from VSS to the DACrsquos referencevoltage (VDD or VREF))

FIGURE C-1 VW (VOUT)

Note When there are 2N resistors in the resistorladder and 2N tap points the full-scaleDAC register code is the resistor element(1 LSb) from the source reference voltage(VDD or VREF)

2N = 4096 (MCP47CVB2X)= 1024 (MCP47CVB1X)= 256 (MCP47CVB0X)

Ideal

Measured 1

Measured 2

VLSb IDEAL VDD

2N

----------- or VREF

2N

-------------=

VLSb Measured VOUT(4032) VOUT(64)ndash

4032 64ndash ---------------------------------------------------------------=

VLSb

VOUT(FS) VOUT(ZS)ndash

2N

1ndash-----------------------------------------------------------=

40h

3Fh

3Eh

03h

02h

01h

00h

Wip

er

Cod

eVoltage (VW ~= VOUT)

VW ( Tap)

VS0

VS1

VS3

VS63

VS64

VW = VSn + VZS( Tap 0) n = 0

n =


MCP47CXBXX

C4 Full-Scale Error (EFS)

The Full-Scale Error EFS (see Figure C-3) is the erroron the VOUT pin relative to the expected VOUT voltage(theoretical) for the maximum device DAC registercode (code FFFh for 12-bit code 3FFh for 10-bit andcode FFh for 8-bit) see Equation C-2 The error isdependent on the resistive load on the VOUT pin (andwhere that load is tied to such as VSS or VDD) Forloads (to VSS) greater than specified the full-scaleerror will be greater

The error in bits is determined by the theoretical voltagestep-size to give an error in LSb

EQUATION C-2 FULL-SCALE ERROR

C5 Zero-Scale Error (EZS)

The Zero-Scale Error EZS (see Figure C-2) is the differ-ence between the ideal and measured VOUT voltage withthe DAC register code equal to 000h (Equation C-3) Theerror is dependent on the resistive load on the VOUT pin(and where that load is tied to such as VSS or VDD) Forloads (to VDD) greater than specified the zero-scaleerror is greater


EQUATION C-3 ZERO-SCALE ERROR

C6 Total Unadjusted Error (ET)

The Total Unadjusted Error (ET) is the differencebetween the ideal and measured VOUT voltage Typi-cally calibration of the output voltage is implementedto improve the systemrsquos performance

The error in bits is determined by the theortical voltagestep-size to give an error in LSb

Equation C-4 shows the total unadjusted errorcalculation

EQUATION C-4 TOTAL UNADJUSTED ERROR CALCULATION

WhereEFS is expressed in LSb

VOUT(FS) is the VOUT voltage when the DAC register code is at full scale

VIDEAL(FS) is the ideal output voltage when theDAC register code is at full scale

VLSb(IDEAL) is the theoretical voltage step-size

EFS

VOUT(FS) VIDEAL(FS)ndash

VLSb IDEAL ----------------------------------------------------------------=


VOUT(ZS) is the VOUT voltage when the DAC register code is at zero scale


EZS

VOUT(ZS)

VLSb(IDEAL)----------------------------=

Where

ET is expressed in LSb

VOUT_Actual(code) = The measured DAC output voltage at the specified code

VOUT_Ideal(code) = The calculated DAC output voltage at the specified code (code VLSb(Ideal))

VLSb(Ideal) = VREF Steps 12-bit = VREF4096 10-bit = VREF1024 8-bit = VREF256

ET

VOUT_Actual(code) VOUT_Ideal(code)ndash VLSb Ideal

--------------------------------------------------------------------------------------------------=


MCP47CXBXX

C7 Offset Error (EOS)

The Offset Error (EOS) is the delta voltage of the VOUTvoltage from the ideal output voltage at the specifiedcode This code is specified where the output amplifieris in the linear operating range for the MCP47CXBXXwe specify code 100 (decimal) Offset error does notinclude gain error which is illustrated in Figure C-2

This error is expressed in mV Offset error can benegative or positive The error can be calibrated bysoftware in application circuits

FIGURE C-2 Offset Error (Zero Gain Error)

C8 Offset Error Drift (EOSD)

The Offset Error Drift (EOSD) is the variation in offseterror due to a change in ambient temperature The off-set error drift is typically expressed in ppmdegC or microVdegC

C9 Gain Error (EG)

Gain Error (EG) is a calculation based on the idealslope using the voltage boundaries for the linear rangeof the output driver (eg code 100 and code 4000) seeFigure C-3) The gain error calculation nullifies thedevicersquos offset error

The gain error indicates how well the slope of the actualtransfer function matches the slope of the ideal transferfunction The gain error is usually expressed as a percentof Full-Scale Range ( of FSR) or in LSb FSR is theideal full-scale voltage of the DAC (see Equation C-5)

FIGURE C-3 Gain Error and Full-Scale Error Example

EQUATION C-5 GAIN ERROR EXAMPLE

C10 Gain Error Drift (EGD)

The Gain Error Drift (EGD) is the variation in gain errordue to a change in ambient temperature The gain errordrift is typically expressed in ppmdegC (of Full-ScaleRange)

Ideal Transfer

Actual

DAC Input Code0

Zero-ScaleError (EZS)

Offset

Function

64 4032

VO

UT

Error (EOS)

TransferFunction

VO

UT

Ideal Transfer

Actual

DAC Input Code0

Full-ScaleError (EFS)

Gain Error (EG)

Function

64 4032 4095

VREF

TransferFunction

( code = 4032)

Ideal TransferFunction Shifted byOffset Error(crosses at start ofdefined linear range)

Where

EG is expressed in of Full-Scale Range (FSR)

VOUT(4032) = The measured DAC output voltage at the specified code

VOUT_Ideal(4032) = The calculated DAC output voltage at the specified code(4032 VLSb(Ideal))

VOS = Measured offset voltage

VFull-Scale Range = Expected full-scale output value (such as the VREF voltage)

EG

VOUT(4032) VOSndash VOUT_Ideal(4032)ndash VFull-Scale Range

---------------------------------------------------------------------------------------------------- 100=


MCP47CXBXX

C11 Integral Nonlinearity (INL)

The Integral Nonlinearity (INL) error is the maximumdeviation of an actual transfer function from an idealtransfer function (straight line) passing through thedefined end-points of the DAC transfer function (afterOffset and Gain Errors have been removed)

For the MCP47CXBXX INL is calculated using thedefined end points DAC code 64 and code 4032 INLcan be expressed as a percentage of Full-Scale Range(FSR) or in LSb INL is also called relative accuracyEquation C-6 shows how to calculate the INL error inLSb and Figure C-4 shows an example of INL accuracy

Positive INL means a VOUT voltage higher than theideal one Negative INL means a VOUT voltage lowerthan the ideal one

EQUATION C-6 INL ERROR

FIGURE C-4 INL Accuracy

C12 Differential Nonlinearity (DNL)

The Differential Nonlinearity (DNL) error (seeFigure C-5) is the measure of step-size between codesin an actual transfer function The ideal step-sizebetween codes is 1 LSb A DNL error of zero wouldimply that every code is exactly 1 LSb wide If the DNLerror is less than 1 LSb the DAC ensures monotonicoutput and no missing codes Equation C-7 shows howto calculate the DNL error between any two adjacentcodes in LSb

EQUATION C-7 DNL ERROR

FIGURE C-5 DNL Accuracy

Where

INL is expressed in LSb

VCalc_Ideal = Code VLSb(Measured) + VOS

VOUT(Code = n) = The measured DAC output voltage with a given DAC register code

VLSb(Measured) = For Measured (VOUT(4032) ndash VOUT(64))3968


EINL

VOUT VCalc_Idealndash VLSb Measured

--------------------------------------------------=

010001000

AnalogOutput(LSb)

DAC Input Code011 111100 101

1

2

3

4

5

6

0

7

110

Ideal Transfer Function

Actual Transfer Function

INL = lt -1 LSb

INL = 05 LSb

INL = -1 LSb

Where

DNL is expressed in LSb



EDNL

VOUT(code = n+1) VOUT(code = n)ndash VLSb Measured

------------------------------------------------------------------------------------ 1ndash=

010001000

AnalogOutput(LSb)

DAC Input Code

011 111100 101

1

2

3

4

5

6

0

7

DNL = 2 LSb

DNL = 05 LSb

110




MCP47CXBXX

C13 Settling Time

The settling time is the time delay required for the VOUTvoltage to settle into its new output value This time ismeasured from the start of code transition to when theVOUT voltage is within the specified accuracy

For the MCP47CXBXX the settling time is a measureof the time delay until the VOUT voltage reaches within05 LSb of its final value when the Volatile DAC registerchanges from 14 to 34 of the Full-Scale Range (12-bitdevice 400h to C00h)

C14 Major Code Transition Glitch

Major code transition glitch is the impulse energyinjected into the DAC analog output when the code inthe DAC register changes the state It is normally spec-ified as the area of the glitch in nV-Sec and is measuredwhen the digital code is changed by 1 LSb at the majorcarry transition (Example 011111 to 100000 or 100000 to 011111)

C15 Digital Feedthrough

The digital feedthrough is the glitch that appears at theanalog output caused by coupling from the digital inputpins of the device The area of the glitch is expressedin nV-Sec and is measured with a full-scale change(Example all lsquo0rsquos to all lsquo1rsquos and vice versa) on the digitalinput pins The digital feedthrough is measured whenthe DAC is not being written to the output register

C16 -3 dB Bandwidth

This is the frequency of the signal at the VREF pin thatcauses the voltage at the VOUT pin to fall to -3 dB froma static value on the VREF pin The output decreasesdue to the RC characteristics of the resistor ladder andthe characteristics of the output buffer

C17 Power Supply Sensitivity (PSS)

PSS indicates how the output of the DAC is affected bychanges in the supply voltage PSS is the ratio of thechange in VOUT to a change in VDD for mid-scale outputof the DAC The VOUT is measured while the VDD isvaried from 55V to 27V as a step (VREF voltage heldconstant) and expressed in which is the change of the DAC output voltage with respect to the change of the VDD voltage

EQUATION C-8 PSS CALCULATION

C18 Power Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the DAC is affectedby changes in the supply voltage PSRR is the ratio ofthe change in VOUT to a change in VDD for full-scaleoutput of the DAC The VOUT is measured while theVDD is varied plusmn10 (VREF voltage held constant) andexpressed in dB or microVV

C19 VOUT Temperature Coefficient

The VOUT temperature coefficient quantifies the error inthe resistor ladderrsquos resistance ratio (DAC registercode value) and output buffer due to temperature drift

C20 Absolute Temperature Coefficient

The absolute temperature coefficient quantifies theerror in the end-to-end output voltage (nominal outputvoltage VOUT) due to temperature drift For a DAC thiserror is typically not an issue due to the ratiometricaspect of the output

C21 Noise Spectral Density

The noise spectral density is a measurement of thedevicersquos internally generated random noise and ischaracterized as a spectral density (voltage per radicHz)It is measured by loading the DAC to the mid-scalevalue and measuring the noise at the VOUT pin It ismeasured in nVradicHz

Where

PSS is expressed in

VOUT(55V) = The measured DAC output voltage with VDD = 55V


PSSVOUT(55V) VOUT(27V)ndash VOUT(55V)

55V 27Vndash 55V ----------------------------------------------------------------------------------------------------------=


MCP47CXBXX

NOTES


MCP47CXBXX

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information eg on pricing or delivery refer to the factory or the listed sales office

Device MCP47CXBXX 1 LSb INL Voltage Output Digital-to-Analog Converters with I2C Interface81012-Bit Resolution SingleDual Outputsand VolatileMTP Memory

Tape and Reel T = Tape and Reel

Temperature Range

E = -40degC to +125degC (Extended)

Package MF = Plastic Dual Flat No Lead Package (DFN) 3x3x09 mm 10-Lead

MG = Plastic Quad Flat No Lead Package (QFN) 3x3x09 mm 16-Lead

UN = Plastic Micro Small Outline Package (MSOP) 10-Lead

Examples

a) MCP47CVB01-EMF 1 LSb INL Voltage OutputDigital-to-Analog Converter 8-Bit Resolution Extended Temperature 10LD DFN with Volatile Memory

b) MCP47CVB01T-EMF 1 LSb INL Voltage Output Digital-to-Analog Converter 8-Bit Resolution Tape and Reel Extended Temperature 10LD DFN with Volatile Memory

a) MCP47CVB12-EMG 1 LSb INL Voltage Output Digital-to-Analog Converter 10-Bit Resolution Extended Temperature 16LD QFN with Volatile Memory

b) MCP47CVB12T-EMG 1 LSb INL Voltage Output Digital-to-Analog Converter 10-Bit Resolution Tape and Reel Extended Temperature 16LD QFN with Volatile Memory

a) MCP47CMB21-EUN 1 LSb INL Voltage Output Digital-to-Analog Converter 12-Bit Resolution Extended Temperature 10LD MSOP with Nonvolatile Memory

b) MCP47CMB21T-EUN 1 LSb INL Voltage Output Digital-to-Analog Converter 12-Bit Resolution Tape and Reel Extended Temperature 10LD MSOP with Nonvolatile Memory

PART NO X

TemperatureRange

Device

XX

Package

X(1)

Tape andReel

Note 1 Tape and Reel identifier only appears in the catalog part number description This identifier is used for ordering purposes and is not printed on the device package Check with your Microchip Sales Office for package availability with the Tape and Reel option

-


MCP47CXBXX

NOTES


Note the following details of the code protection feature on Microchip devices

bull Microchip products meet the specification contained in their particular Microchip Data Sheet

bull Microchip believes that its family of products is one of the most secure families of its kind on the market today when used in the intended manner and under normal conditions

bull There are dishonest and possibly illegal methods used to breach the code protection feature All of these methods to our knowledge require using the Microchip products in a manner outside the operating specifications contained in Microchiprsquos Data Sheets Most likely the person doing so is engaged in theft of intellectual property

bull Microchip is willing to work with the customer who is concerned about the integrity of their code

bull Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code Code protection does not mean that we are guaranteeing the product as ldquounbreakablerdquo

Code protection is constantly evolving We at Microchip are committed to continuously improving the code protection features of ourproducts Attempts to break Microchiprsquos code protection feature may be a violation of the Digital Millennium Copyright Act If such actsallow unauthorized access to your software or other copyrighted work you may have a right to sue for relief under that Act

Information contained in this publication regarding deviceapplications and the like is provided only for your convenienceand may be superseded by updates It is your responsibility toensure that your application meets with your specificationsMICROCHIP MAKES NO REPRESENTATIONS ORWARRANTIES OF ANY KIND WHETHER EXPRESS ORIMPLIED WRITTEN OR ORAL STATUTORY OROTHERWISE RELATED TO THE INFORMATIONINCLUDING BUT NOT LIMITED TO ITS CONDITIONQUALITY PERFORMANCE MERCHANTABILITY ORFITNESS FOR PURPOSE Microchip disclaims all liabilityarising from this information and its use Use of Microchipdevices in life support andor safety applications is entirely atthe buyerrsquos risk and the buyer agrees to defend indemnify andhold harmless Microchip from any and all damages claimssuits or expenses resulting from such use No licenses areconveyed implicitly or otherwise under any Microchipintellectual property rights unless otherwise stated

2018-2019 Microchip Technology Inc

For information regarding Microchiprsquos Quality Management Systems please visit wwwmicrochipcomquality

TrademarksThe Microchip name and logo the Microchip logo Adaptec AnyRate AVR AVR logo AVR Freaks BesTime BitCloud chipKIT chipKIT logo CryptoMemory CryptoRF dsPIC FlashFlex flexPWR HELDO IGLOO JukeBlox KeeLoq Kleer LANCheck LinkMD maXStylus maXTouch MediaLB megaAVR Microsemi Microsemi logo MOST MOST logo MPLAB OptoLyzer PackeTime PIC picoPower PICSTART PIC32 logo PolarFire Prochip Designer QTouch SAM-BA SenGenuity SpyNIC SST SST Logo SuperFlash Symmetricom SyncServer Tachyon TempTrackr TimeSource tinyAVR UNIO Vectron and XMEGA are registered trademarks of Microchip Technology Incorporated in the USA and other countries

APT ClockWorks The Embedded Control Solutions Company EtherSynch FlashTec Hyper Speed Control HyperLight Load IntelliMOS Libero motorBench mTouch Powermite 3 Precision Edge ProASIC ProASIC Plus ProASIC Plus logo Quiet-Wire SmartFusion SyncWorld Temux TimeCesium TimeHub TimePictra TimeProvider Vite WinPath and ZL are registered trademarks of Microchip Technology Incorporated in the USA

Adjacent Key Suppression AKS Analog-for-the-Digital Age Any Capacitor AnyIn AnyOut BlueSky BodyCom CodeGuard CryptoAuthentication CryptoAutomotive CryptoCompanion CryptoController dsPICDEM dsPICDEMnet Dynamic Average Matching DAM ECAN EtherGREEN In-Circuit Serial Programming ICSP INICnet Inter-Chip Connectivity JitterBlocker KleerNet KleerNet logo memBrain Mindi MiWi MPASM MPF MPLAB Certified logo MPLIB MPLINK MultiTRAK NetDetach Omniscient Code Generation PICDEM PICDEMnet PICkit PICtail PowerSmart PureSilicon QMatrix REAL ICE Ripple Blocker SAM-ICE Serial Quad IO SMART-IS SQI SuperSwitcher SuperSwitcher II Total Endurance TSHARC USBCheck VariSense ViewSpan WiperLock Wireless DNA and ZENA are trademarks of Microchip Technology Incorporated in the USA and other countries

SQTP is a service mark of Microchip Technology Incorporated in the USAThe Adaptec logo Frequency on Demand Silicon Storage Technology and Symmcom are registered trademarks of Microchip Technology Inc in other countriesGestIC is a registered trademark of Microchip Technology Germany II GmbH amp Co KG a subsidiary of Microchip Technology Inc in other countries All other trademarks mentioned herein are property of their respective companies

copy 2018-2019 Microchip Technology Incorporated All Rights Reserved

ISBN 978-1-5224-4636-1

DS20006089B-page 123


AMERICASCorporate Office2355 West Chandler BlvdChandler AZ 85224-6199Tel 480-792-7200 Fax 480-792-7277Technical Support httpwwwmicrochipcomsupportWeb Address wwwmicrochipcom

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UK - WokinghamTel 44-118-921-5800Fax 44-118-921-5820

Worldwide Sales and Service

051419

Features

General Description

Applications




10 Electrical Characteristics


DC Characteristics

DC Characteristics (Continued)








DC Notes


111 Wiper Settling Time


TABLE 1-1 Wiper Settling Timing

112 Latch Pin (LAT) Timing


TABLE 1-2 LAT Pin Timing




TABLE 1-3 Reset Timing


TABLE 1-4 I2C Bus StartStop Bits and LAT Requirements


TABLE 1-5 I2C Bus Requirements (Slave Mode)

TABLE 1-5 I2C Bus Requirements (Slave Mode) (Continued)

Timing Notes

Temperature Specifications

20 Typical Performance Curves

21 Electrical Data










22 Linearity Data

221 Total Unadjusted Error (TUE) ndash MCP47CXB2X (12-Bit) VREF = VDD (VRXBVRXA = 10) Gain = 1X Code 64-4032







222 Integral Nonlinearity (INL) ndash MCP47CXB2X (12-Bit) VREF = VDD (VRXBVRXA = 10) Gain = 1X Code 64-4032







223 Differential Nonlinearity (DNL) ndash MCP47CXB2X (12-Bit) VREF = VDD (VRXBVRXA = 10) Gain = 1X Code 64-4032







224 Total Unadjusted Error (TUE) ndash MCP47CXB2X (12-Bit) External VREF = 05 VDD (VRXBVRXA = 10) Unbuffered Code 64-4032





225 Integral Nonlinearity (INL) ndash MCP47CXB2X (12-Bit) External VREF = 05 VDD (VRXBVRXA = 10) Unbuffered Code 64-4032





226 Differential Nonlinearity Error (DNL) ndash MCP47CXB2X (12-Bit) External VREF = 05 VDD (VRXBVRXA = 10) Unbuffered Code 64-4032





227 Total Unadjusted Error (TUE) ndash MCP47CXB2X (12-Bit) VREF = Internal Band Gap (VRXBVRXA = 01) Code 64-4032














228 Integral Nonlinearity Error (INL) ndash MCP47CXB2X (12-Bit) VREF = Internal Band Gap (VRXBVRXA = 01) CODE 64-4032














229 Differential Nonlinearity Error (DNL) ndash MCP47CXB2X (12-Bit) VREF = Internal Band Gap (VRXBVRXA = 01) Code 64-4032














30 Pin Descriptions

TABLE 3-1 MCP47CXBX1 (Single DAC) Pin Function Table

TABLE 3-2 MCP47CXBX2 (Dual DAC) Pin Function Table


32 Ground (VSS)







39 No Connect (NC)

40 General Description


411 Power-on Reset


412 Brown-out Reset

42 Device Memory

421 Volatile Register Memory (RAM)

TABLE 4-1 MCP47CXBXX Memory Map (16-Bit)

422 Nonvolatile Register Memory (MTP)

423 PORBOR Operation with WiperLock Technology Enabled

424 Unimplemented Locations

TABLE 4-2 Factory Default PORBOR Values (MTP Memory Unprogrammed)

425 Device Registers

Register 4-1 DAC0 (00h10h) and DAC1 (01h11h) Output Value Registers (VolatileNonvolatile)

Register 4-2 Voltage Reference (VREF) Control Registers (08h18h) (VolatileNonvolatile)

Register 4-3 Power-Down Control Registers (09h19h) (VolatileNonvolatile)

Register 4-4 Gain Control and System Status Register (0Ah) (Volatile)

Register 4-5 Gain Control and Slave Address Register (1AH) (Nonvolatile)

Register 4-6 WiperLocktrade Technology Control Register (1Bh) (Nonvolatile)

50 DAC Circuitry


51 Resistor Ladder


EQUATION 5-1 RS Calculation




521 Using VDD as VREF

522 Using an External VREF Source in Unbuffered Mode

523 Using an External VREF Source in Buffered Mode

524 Using the Internal Band Gap as Voltage Reference

TABLE 5-1 VOUT Using Band Gap



531 Programmable Gain

TABLE 5-2 Output Driver Gain

532 Output Voltage

EQUATION 5-2 Calculating Output Voltage (VOUT)

533 Step Voltage (VS)

EQUATION 5-3 VS Calculation

TABLE 5-3 Theoretical Step Voltage (VS)(1)

534 Output Slew Rate


535 Driving Resistive and Capacitive Loads


54 Latch Pin (LAT)




TABLE 5-4 Power-Down Bits and Output Resistive Load

TABLE 5-5 DAC Current Sources

551 Exiting Power-Down

TABLE 5-6 DAC Input Code vs Calculated Analog Output (VOUT) (VDD = 50V)

60 I2C Serial Interface Module


61 Overview

611 Interface Pins (SCL and SDA)


63 PORBOR






TABLE 6-1 I2C AddressOrder Code

671 Custom I2C Slave Address Options

68 Slope Control

69 Pulse Gobbler



70 Device Commands

71 Write Commands

72 Read Commands

TABLE 7-1 Device Commands ndash Number of Clocks



75 Write Command

751 Single Write to Volatile Memory

752 Single Write to Nonvolatile Memory (HVC Pin = VIL or VIH)

753 Single Write to Nonvolatile Memory (HVC Pin = VIHH)


754 Continuous Writes to Volatile Memory

TABLE 7-2 Volatile Memory Addresses

755 Continuous Writes to Nonvolatile Memory



76 Read Command

761 Single Read

762 Continuous Reads

763 Ignoring an I2C Transmission and ldquoFalling Offrdquo the Bus







771 General Call Reset

772 General Call Wake-up



80 Typical Applications


811 Device Connection Test





831 DC Set Point or Calibration


EQUATION 8-1 VOUT and VTRIP Calculations





EQUATION 8-3 VOUT VOA+ and VO Calculations


851 Bipolar DAC Example

EQUATION 8-4

EQUATION 8-5



EQUATION 8-7 Bipolar ldquoWindowrdquo DAC Using R4 and R5



EQUATION 8-8 VOUT Calculation









8102 Layout Considerations

TABLE 8-1 Package Footprint(1)

90 Development Support



TABLE 9-1 Development Tools(1)

TABLE 9-2 Technical Documentation


100 Packaging Information


Appendix A Revision History



Appendix B I2C Serial Interface


B1 Overview


B21 Serial Data (SDA)

B22 Serial Clock (SCL)

B3 I2C Operation

B31 I2C Bit States and Sequence


FIGURE B-3 Data Bit


TABLE B-1 MCP47CXBXX AA Responses



B32 Clock Stretching

B33 Aborting a Transmission



B34 Slope Control

B35 Device Addressing


B36 HS Mode


B37 General Call


Appendix C Terminology

C1 Resolution


EQUATION C-1 LSb Voltage Calculation




EQUATION C-2 Full-Scale Error


EQUATION C-3 Zero-Scale Error


EQUATION C-4 Total Unadjusted Error Calculation




C9 Gain Error (EG)


EQUATION C-5 Gain Error Example



EQUATION C-6 INL Error



EQUATION C-7 DNL Error


C13 Settling Time



C16 -3 dB Bandwidth


EQUATION C-8 PSS Calculation





Product Identification System


MCP47CXBXX

General Description

The MCP47CXBXX devices are single and dualchannel 8-bit 10-bit and 12-bit buffered voltage outputDigital-to-Analog Converters (DAC) with volatile orMTP memory and an I2C serial interface

The MTP memory can be written by the user up to32 times for each specific register It requires a high-voltage level on the HVC pin typically 75V in order tosuccessfully program the desired memory locationThe nonvolatile memory includes power-up outputvalues device Configuration registers and generalpurpose memory

The VREF pin the device VDD or the internal band gapvoltage can be selected as the DACrsquos referencevoltage When VDD is selected VDD is internallyconnected to the DAC reference circuit

When the VREF pin is used with an external voltagereference the user can select between a gain of 1 or 2and can have the reference buffer enabled or disabledWhen the gain is 2 the VREF pin voltage should belimited to a maximum of VDD2

These devices have a two-wire I2C compatible serialinterface for Standard (100 kHz) Fast (400 kHz) orHigh-Speed (17 MHz and 34 MHz) modes

Applications



bull Low-Power Portable Instrumentation

bull PC Peripherals

bull Data Acquisition Systems


VDD

VSS

Memory

SDA

SCL

VREF1VREF0

A0

A1

VOUT0

10

0k

1k

VDD PD1PD0

VREF1VREF0

OP AMP

ADDR6ADDR0


DAC0VREFPOWER-DOWNGAINSTATUS

DAC0VREFPOWER-DOWNGAINI2C ADDRESSWiperLocktrade

VOLATILE (4x16)

NONVOLATILE (13x16)

Band Gap1214V

VDD

VIHH

LAT0

VBG

LATHVC

VREF0




Res

isto

rL

add

er

GAIN


MCP47CXBXX


VDD

VSS

Memory

VREF0(2)

SDA

SCL

VREF1VREF0



A0

A1

Res

isto

rL

add

er

VOUT0

10

0k

1k

VDD

LAT0HVC

PD1PD0

VREF1VREF0

OP AMP

ADDR6ADDR0




VOLATILE (5x16)

NONVOLATILE (14x16)

Band Gap1214V

VDD

GAIN

VREF1(2)

VREF1VREF0

Re

sist

or

Lad

der

VOUT1

100

k

1k

VDD

LAT1(1)

PD1PD0

VREF1VREF0

OP AMP


VDD

GAIN

VIHH

LAT0

LAT0(1)

VBG

VBG





MCP47CXBXX


Device Package Type

o

f C

ha

nn

els

Re

so

luti

on

(b

its)


o

f V

RE

F I

np

uts

o

f L

AT

In

pu

ts(3

)

o

f A

dd

ress

Pin

s

Me

mo

ry(2

)

GP

MT

P L

oca

tio

ns























MCP47CXBXX



























MCP47CXBXX

DC CHARACTERISTICS










VDDRR Note 3 Vms







MCP47CXBXX
















Power-Down Current






MCP47CXBXX











mdash 0016 0300 18V VDD 55V(2)










MCP47CXBXX





































MCP47CXBXX































MCP47CXBXX













Internal Band Gap












MCP47CXBXX










spec (at 55V)



Dynamic Performance








MCP47CXBXX






















RAM Value


mdash 3FFh 10-bit

mdash FFFh 12-bit



10-bit

12-bit



Power Requirements



mdash 10-bit

mdash 12-bit


MCP47CXBXX























MCP47CXBXX

DC Notes














MCP47CXBXX






VOUT

plusmn 05 LSb

Old Value

New Value









LATx

SCL

tLAT

Wx








MCP47CXBXX




VDD

tBORD

VOUT

VBOR

VOUT at High-Z


VPOR

tPOR2SIA = tPOR2OD

SDA

SCL

ACK Stop Start ACK

VOUT

tPDD tPDE














MCP47CXBXX


SCL

SDA

StartCondition

StopCondition

VIH

111

VIL

VIH VIHH

VIHHVC94


9091 93

92


MCP47CXBXX



Param No






























MCP47CXBXX




Param No











400 kHz mode 20 + 01Cb(4) 300 ns






400 kHz mode 20 + 01Cb 300 ns




400 kHz mode 20 + 01Cb 300 ns






9091 92

100101

103

106107

109 109 110

102

SCL

SDA In

SDA Out


MCP47CXBXX



Param No



400 kHz mode 20 + 01Cb 300 ns




































MCP47CXBXX

Timing Notes












MCP47CXBXX




Temperature Ranges









MCP47CXBXX

NOTES


MCP47CXBXX











MCP47CXBXX






MCP47CXBXX

22 Linearity Data










MCP47CXBXX










MCP47CXBXX










MCP47CXBXX








MCP47CXBXX








MCP47CXBXX








MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX

NOTES


MCP47CXBXX

30 PIN DESCRIPTIONS




Pin


DescriptionMSOP10L

DFN10L

QFN16L





5 5 456781415












MCP47CXBXX


Pin


DescriptionMSOP10L

DFN10L

QFN16L








mdash mdash 671415
















MCP47CXBXX




32 Ground (VSS)






















MCP47CXBXX







39 No Connect (NC)



MCP47CXBXX













bull Device Memory










411 POWER-ON RESET





MCP47CXBXX











VPOR

TPORD2OD

VDD(MIN)


VRAM


VBOR


VDD(MIN)

TPOR2OD

VBOR VPOR

VRAM

Case 1 VDD Ramp

Case 2 VDD Step

















POR Event


MCP47CXBXX

412 BROWN-OUT RESET












42 Device Memory


















MCP47CXBXX


dd

res

s

Function

Sin

gle

Du

al

Ad

dre

ss

Function

Sin

gle

(1)

Du

al(1

)

















Legend






MCP47CXBXX























MCP47CXBXX


dd

ress

Function

PORBOR Value

Ad

dre

ss

Function

PORBOR Value

8-B

it

10-B

it

12-B

it

8-B

it

10-B

it

12-B

it


7Fh 1FFh 7FFh


7Fh 1FFh 7FFh










0000h 0000h 0000h



0060h 0060h 0060h


0000h 0000h 0000h





Legend



Not Implemented




MCP47CXBXX

12-b

10-b

8-b








bit 15 bit 0

Legend



12-bit 10-bit 8-bit









MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual




powered down(2)





MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual







MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual




0 = 1x gain



0 = 1x gain














MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual









MCP47CXBXX

Singl

Dua







bit 15 bit 0

Legend



Single Dual







MCP47CXBXX

50 DAC CIRCUITRY










RS(2)

VREF

DACOutput

RS(1)

RS(2n ndash 1)

RS(2n ndash 2)

RS(2n ndash 3)

RS(2n)

VDD

VRL

VOUT

PD1PD0

VDD

PD1PD0

VDD

VW



Selection


ResistorLadder


Power-DownOperation

Power-DownOperation

Power-DownOperation

A (RL)

B

VREF1VREF0

Where


1024 (MCP47CXB1X)

4096 (MCP47CXB2X)



VDD

(~71 k)RRL

1kΩ

100

kΩ

Gain(1x or 2x)



MCP47CXBXX

51 Resistor Ladder












VW

Analog MUX


RS(2)

DACRegister

RS(1)

RS(2n ndash 1)

RS(2n ndash 2)

RS(2n ndash 3)

RS(2n)

VRL

RRL

RW(1)

RW(1)

RW(1)

RW(1)

RW(1)

RW(1)

2n ndash 1

2n ndash 2

1

0

2

2n ndash 3

RS

RRL256

--------------=

RS

RRL1024

------------------=

8-Bit Device

10-Bit Device

RS

RRL4096

------------------= 12-Bit Device


MCP47CXBXX




1 VDD pin voltage














VRL

VDD

Buffer

Re

fere

nce

VREF1VREF0

Se

lect

ion

VREF

Band Gap


VDD

VRL

Band Gap(1)

(1214V typical)

VDD

VDD

VREF





MCP47CXBXX
























VD

D

DA

C G

ain Max DAC Code(1)










VWVOUT

PD1PD0

VDD

PD1PD0

1kΩ

100

kΩ

Gain(1x or 2x)


MCP47CXBXX



bull POR Event

bull BOR Event



532 OUTPUT VOLTAGE
















0 1


Where


1024 (MCP47CXB1X)

256 (MCP47CXB0X)

VOUT


Where


1024 (10-bit)

256 (8-bit)

VS

VRL


StepVoltage

VREF

50 27 18 15 10

VS

122 mV 659 uV 439 uV 366 uV 244 uV 12-bit

488 mV 264 mV 176 mV 146 mV 977 uV 10-bit

195 mV 105 mV 703 mV 586 mV 391 mV 8-bit



MCP47CXBXX




















Time

DACx = A

VO

UT

VOUT(A)

VOUT(B)

DACx = B


T--------------------------------------------------=


Gain

VOUT RISO

RL CL

VCL

VW


MCP47CXBXX

54 Latch Pin (LAT)













DAC Wiper x

16 Clocks

LATSYNC

Transfer

Serial Shift Reg


LAT SYNCTransfer

DataComment

1 1 0 No Transfer

1 0 0 No Transfer


0 0 0 No Transfer

Vol DAC Register x





MCP47CXBXX






Configuration bits
























PD1 PD0 Function




1 1 Open circuit















MCP47CXBXX


DeviceVolatile DAC

Register ValueVRL

(1)LSb Gain

Selection (2)

VOUT(3)


CP

47C

VB

2X (

12

-bit)

1111 1111 1111 50V 50V4096 12207 1x VRL (40954096) 1 4998779

25V 25V4096 6104 1x VRL (40954096) 1 2499390

2x(2) VRL (40954096) 2) 4998779

0111 1111 1111 50V 50V4096 12207 1x VRL (20474096) 1) 2498779

25V 25V4096 6104 1x VRL (20474096) 1) 1249390

2x(2) VRL (20474096) 2) 2498779

0011 1111 1111 50V 50V4096 12207 1x VRL (10234096) 1) 1248779

25V 25V4096 6104 1x VRL (10234096) 1) 0624390

2x(2) VRL (10234096) 2) 1248779

0000 0000 0000 50V 50V4096 12207 1x VRL (04096) 1) 0

25V 25V4096 6104 1x VRL (04096) 1) 0

2x(2) VRL (04096) 2) 0

MC

P47

CV

B1X

(1

0-b

it)

11 1111 1111 50V 50V1024 48828 1x VRL (10231024) 1 4995117

25V 25V1024 24414 1x VRL (10231024) 1 2497559

2x(2) VRL (10231024) 2 4995117

01 1111 1111 50V 50V1024 48828 1x VRL (5111024) 1 2495117

25V 25V1024 24414 1x VRL (5111024) 1 1247559

2x(2) VRL (5111024) 2 2495117

00 1111 1111 50V 50V1024 48828 1x VRL (2551024) 1 1245117

25V 25V1024 24414 1x VRL (2551024) 1 0622559

2x(2) VRL (2551024) 2 1245117

00 0000 0000 50V 50V1024 48828 1x VRL (01024) 1 0

25V 25V1024 24414 1x VRL (01024) 1 0

2x(2) VRL (01024) 1 0

MC

P4

7CV

B0X

(8

-bit)

1111 1111 50V 50V256 195313 1x VRL (255256) 1 4980469

25V 25V256 97656 1x VRL (255256) 1 2490234

2x(2) VRL (255256) 2 4980469

0111 1111 50V 50V256 195313 1x VRL (127256) 1 2480469

25V 25V256 97656 1x VRL (127256) 1 1240234

2x(2) VRL (127256) 2 2480469

0011 1111 50V 50V256 195313 1x VRL (63256) 1 1230469

25V 25V256 97656 1x VRL (63256) 1 0615234

2x(2) VRL (63256) 2 1230469

0000 0000 50V 50V256 195313 1x VRL (0256) 1 0

25V 25V256 97656 1x VRL (0256) 1 0

2x(2) VRL (0256) 2 0





MCP47CXBXX

NOTES


MCP47CXBXX






61 Overview





bull PORBOR




bull Slope Control










63 PORBOR













SCLSCL

MCP47CVBXX

SDASDA

HostController


Other Devices

(Master)(Slave)


MCP47CXBXX








68 Slope Control


69 Pulse Gobbler




Address Byte

RW ACK

Acknowledge Bit

Slave Address

A6 A5 A4 A3


A2 A1 A0













MCP47CXBXX














P


RW = ReadWrite bit

RW


FS Mode HS Mode

HS Mode Continues

FS Mode


Control Byte

Sr


MCP47CXBXX

NOTES


MCP47CXBXX

70 DEVICE COMMANDS





71 Write Commands



72 Read Commands




Command

of Bit Clocks(1)



CodeMode

C1 C0 100 kHz 400 kHz 34 MHz (3)





1 1 Last Address 29 3448 13793 117241








MCP47CXBXX











75 Write Command














MCP47CXBXX











Memory Address

I2C ACK bit(1)




SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

0 0 x A

ADn

D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA

A

P

S xSAn

0 0

I2C Start Bit

I2C Slave Address



I2C Stop Bit(3)




Legend


MCP47CXBXX








00h Yes Yes

01h No Yes

08h Yes Yes

09h Yes Yes

0Ah Yes Yes



S Slave Address

RW

AC

K

Command

AC

K

Data Byte

AC

K

Data Byte

AC

K

P

Master S

SA

6S

A5

SA

4S

A3

SA

2S

A1

SA

0

0 AA

AD

4A

D3

AD

2A

D1

AD

0C

1C

0 x AA

D15

D14

D13

D12

D11

D10

D09

D08 AA

D07

D06

D05

D04

D03

D02

D01

D00 AA P



MCP47CXBXX 0 0 0 0




MCP47CXBXX 0 1 1 1




MCP47CXBXX






D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


AD4

AD3

AD2

AD1

AD0

0 0 x A

Write Command

P

AD4

AD3

AD2

AD1

AD0

0 0 x A

Write Command

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0 AAD4

AD3

AD2

AD1

AD0

0 0 x A


Memory Address

I2C ACK Bit (1)

0

ADn

A

P

S x

SAn

0 0

I2C Start Bit

I2C Slave Address



I2C Stop Bit(3)


Legend


MCP47CXBXX

76 Read Command




bull Single Read





761 SINGLE READ
















MCP47CXBXX








Memory Address(5)

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

1 1 x A

ADn

A

A

PS

x

SAn

1 1

I2C Start Bit

I2C Slave Address

I2C Write Bit

Read Command


I2C Stop Bit(3)

Dnn



Legend

Sr

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

Control Byte

A I2C ACK Bit(2)

I2C NACK Bit(4)A

1 I2C Read Bit



MCP47CXBXX









I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

1 A

A

P

S

SAn

I2C Start Bit


Control Byte

Legend

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


A I2C ACK Bit(2)



MCP47CXBXX


Read 1 Word Command

S Slave Address

RW

AC

K Command

AC

K

Master SS

A6

SA

5S

A4

SA

3S

A2

SA

1S

A0 0 1

AD

4A

D3

AD

2A

D1

AD

0C

1C

0x

1

Sr

Slave Address RW

AC

K

Data Byte AC

K

Data Byte AC

K

P


SA

6S

A5

SA

4S

A3

SA

2S

A1

SA

0

1 1

D1

5D

14

D1

3D

12

D11

D1

0D

09

D0

8 1

D0

7D

06

D0

5D

04

D0

3D

02

D0

1D

00 1 P


Master S 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 x 1

MCP47CXBXX 0 0

I2C Bus S 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 x 0





Master S 1 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 x 1

MCP47CXBXX 0 1

I2C Bus S 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 x 1







MCP47CXBXX








Memory Address(5)

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

1 1 x A

ADn

A

A

PS

x

SAn

1 1

I2C Start Bit

I2C Slave Address

I2C Write Bit

Read Command


I2C Stop Bit(3)



Legend

Sr

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

Control Byte

A I2C ACK Bit(2)

I2C NACK Bit(4)A

1 I2C Read Bit


0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A



MCP47CXBXX












S 0 A 0 x x 0 A


0 00 0 0 0 0 x P000


Legend

x




MCP47CXBXX















S 0 A 0 1 1 0 A


0 00 0 0 0 0 0 P000


Legend

0




S 0 A 0 0 1 0 A


0 00 0 0 0 0 1 P000


Legend

1


MCP47CXBXX







bull Motor Control








3 Send Stop bit


1 2 3 4 5 6 7 8 9SCL


Address Byte

Address Bits

RW

StopBit

Device

AC

K

Response

A3A4A5A6


MCP47CXBXX





5

Analog

VDD

1

2

3

8

6

VDD SDA

SCL

VSS

VOUT0

7

R1 R2

To MCU


R1 and R2









C2C1

MCP47CVBX2

Optional




Output

VREF

4 5

LATHVC

VOUT1

C4C3

Analog

VDD

1

2

3

8

6

VDD SDA

SCL

VSS

VOUT0

7To MCU

C2C1

MCP47CVBX2

Optional

Output

VREF

4

LATHVC

VOUT1

C5

Optional

VREF

C6

R1 R2

C4C3


MCP47CXBXX






















R1

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

VOR2 C1

RSENSE

Comp

VDD

VTRIP

Vtrip VOUT

R2R1 R2+--------------------

=


2N


MCP47CXBXX











R1

VCC+

VCC-

VO

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

VOUTR2 C1

R3

VCC+

VCC-

RSENSE

CompVTRIP

R23

R2R3

R2 R3+-------------------=

V23

VCC+R2 VCC-R3 +

R2 R3+------------------------------------------------------=

VTRIP

VOUTR23 V23R1+

R1 R23+---------------------------------------------------=

TheveninEquivalent

R1

R23

V23

VOUT VTRIP


2N

R3

VCC+

VCC-

VO

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

R2

VOUT

VIN

R1

R4 C1

VOA+

VOA+ = VOUT bull R4

R3 + R4


2N


R1

R2

R1


MCP47CXBXX








EQUATION 8-4

EQUATION 8-5






41V1 mV = 4100




R2ndash

R1---------

205ndash4096V-----------------=


R2

R1------

12---=

R4

R3 R4+ ------------------------

205V 05 4096V +15 4096V

-------------------------------------------------------23---= =

If R4 = 20 k then R3 = 10 k

R3

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

R2

VO

VIN

R1

R4C1

R5

Optional

VOA+

VCC+

VCC-

C1 = 01 microF



2N


R3 + R4


R1

R2

R1


VCC+R4 VCC-R5+

R4 R5+---------------------------------------------=

VIN+

VOUTR45 V45R3+

R3 R45+---------------------------------------------=

R45

R4R5

R4 R5+-------------------=

VO VIN+ 1R2

R1------+

VA

R2

R1------ ndash=



MCP47CXBXX

















R1

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBX2

VDD

I2C2-Wire

VREF

Optional

MCP47CVBX2

VDD

R2

01 microF

VOUT0

VOUT1

(DAC0)

(DAC1)

VOUT =


VOUT0 R2 + VOUT1 R1

R1 + R2


Where

RSENSE

Ib

Load

IL

VCC+

VCC-

VOUT

IL

VOUT

Rsense---------------

1+-------------=

Ib

IL

----=


VDD

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

(or VREF)


MCP47CXBXX






















Start



VDD

VDD

VSS VSS

MC

P4

7CX

BX

X

01 microFP

ICreg

Mic

roc

on

tro

lle

r

01 microF

SCL

VOUT

VREF SDA


MCP47CXBXX



bull Noise


81021 Noise








Pin

s

Type Code


Length Width

10 MSOP UN 300 490 1470

10 DFN MF 300 300 900

16 QFN MG 300 300 900



MCP47CXBXX

















Title Literature





MCP47CXBXX


0

47k






VDD SDA

SCL

(DGND) Plane

NCVOUT1 LATHVC

VSS

10 microF 47k

VOUT0

VREF

47Cx

Bxx

0

A1

A0


MCP47CXBXX






3e

3e

Part Number Code

MCP47CVB01-EMF BAJU

MCP47CVB11-EMF BAJX

MCP47CVB21-EMF BAJZ

MCP47CVB02-EMF BAJV

MCP47CVB12-EMF BAJY

MCP47CVB22-EMF BAKA

MCP47CMB01-EMF BAJV

MCP47CMB11-EMF BAJQ

MCP47CMB21-EMF BAJS

MCP47CMB02-EMF BAJP

MCP47CMB12-EMF BAJR

MCP47CMB22-EMF BAJT

XXXXXX

10-Lead MSOP

YWWNNN47CV01

Example

935256

XXXX


PIN 1

YYWWNNN

BAJU

Example

PIN 1

1935256


MCP47CXBXX

Part Number Code

MCP47CVB02-EMG AAD

MCP47CVB12-EMG AAE

MCP47CVB22-EMG AAF

MCP47CMB02-EMG AAA

MCP47CMB12-EMG AAB

MCP47CMB22-EMG AAC

XXX


PIN 1

XYYWWNNN


AAD

Example

PIN 1

1935256


MCP47CXBXX


UN


MCP47CXBXX


UN


MCP47CXBXX




MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX

NOTES


MCP47CXBXX

















MCP47CXBXX

NOTES


MCP47CXBXX




B1 Overview













SCL SCL

Slave

SDA SDA

Master


Other Devices



MCP47CXBXX










B3 I2C Operation





B311 Start Bit



B312 Data Bit


FIGURE B-3 Data Bit






SDA

SCL

S

1st Bit 2nd Bit



Comment

General Call A

Slave Address Valid

A


A


SDA

SCL

Data Bit

1st Bit 2nd Bit

A

8

D0

9

SDA

SCL


MCP47CXBXX





B315 Stop Bit













SDA

SCL

Sr = Repeated Start

1st Bit

SCL

SDA AA

P

1st Bit

SDA

SCL


SCL

SDA

StartCondition

StopCondition


Data orA Valid


MCP47CXBXX

B34 SLOPE CONTROL







B36 HS MODE











B361 Slope Control


B362 Pulse Gobbler




Address Byte

RW ACK

Acknowledge Bit

7-Bit Slave Address

A6 A5 A4 A3 A2 A1 A0


P

S = Start bit


A = Acknowledge bit


RW = ReadWrite bit

RW


FS Mode HS Mode

HS Mode Continues

FS Mode


Control Byte


MCP47CXBXX

B37 GENERAL CALL







00 0 0S 0 0 0 0 xx x x xA x x 0 A P


Second Byte

7-Bit Command



00 0 0S 0 0 0 0 xx x x xA x x 1 A


Second Byte

Master Address

xx x x x x x x A P




MCP47CXBXX

NOTES


MCP47CXBXX


C1 Resolution










Ideal

Measured 1

Measured 2

VLSb IDEAL VDD

2N

----------- or VREF

2N

-------------=


4032 64ndash ---------------------------------------------------------------=

VLSb


2N

1ndash-----------------------------------------------------------=

40h

3Fh

3Eh

03h

02h

01h

00h

Wip

er

Cod


VW ( Tap)

VS0

VS1

VS3

VS63

VS64


n =


MCP47CXBXX


















EFS


VLSb IDEAL ----------------------------------------------------------------=




EZS

VOUT(ZS)

VLSb(IDEAL)----------------------------=

Where





ET


--------------------------------------------------------------------------------------------------=


MCP47CXBXX







C9 Gain Error (EG)







Ideal Transfer

Actual

DAC Input Code0


Offset

Function

64 4032

VO

UT

Error (EOS)

TransferFunction

VO

UT

Ideal Transfer

Actual

DAC Input Code0


Gain Error (EG)

Function

64 4032 4095

VREF

TransferFunction

( code = 4032)


Where






EG


---------------------------------------------------------------------------------------------------- 100=


MCP47CXBXX











Where






EINL


--------------------------------------------------=

010001000

AnalogOutput(LSb)


1

2

3

4

5

6

0

7

110



INL = lt -1 LSb

INL = 05 LSb

INL = -1 LSb

Where




EDNL


------------------------------------------------------------------------------------ 1ndash=

010001000

AnalogOutput(LSb)

DAC Input Code

011 111100 101

1

2

3

4

5

6

0

7

DNL = 2 LSb

DNL = 05 LSb

110




MCP47CXBXX

C13 Settling Time







C16 -3 dB Bandwidth













Where

PSS is expressed in




55V 27Vndash 55V ----------------------------------------------------------------------------------------------------------=


MCP47CXBXX

NOTES


MCP47CXBXX





Temperature Range





Examples







PART NO X

TemperatureRange

Device

XX

Package

X(1)

Tape andReel


-


MCP47CXBXX

NOTES

















ISBN 978-1-5224-4636-1

DS20006089B-page 123































China - XianTel 86-29-8833-7252





India - PuneTel 91-20-4121-0141




































051419

Features

General Description

Applications






DC Characteristics









DC Notes

















Timing Notes



21 Electrical Data










22 Linearity Data















































































30 Pin Descriptions




32 Ground (VSS)







39 No Connect (NC)



411 Power-on Reset


412 Brown-out Reset

42 Device Memory














50 DAC Circuitry


51 Resistor Ladder















532 Output Voltage









54 Latch Pin (LAT)










61 Overview



63 PORBOR








68 Slope Control

69 Pulse Gobbler



70 Device Commands

71 Write Commands

72 Read Commands




75 Write Command










76 Read Command

761 Single Read






























EQUATION 8-4

EQUATION 8-5






























B1 Overview




B3 I2C Operation



FIGURE B-3 Data Bit









B34 Slope Control



B36 HS Mode


B37 General Call



C1 Resolution














C9 Gain Error (EG)










C13 Settling Time



C16 -3 dB Bandwidth









MCP47CXBXX


VDD

VSS

Memory

VREF0(2)

SDA

SCL

VREF1VREF0



A0

A1

Res

isto

rL

add

er

VOUT0

10

0k

1k

VDD

LAT0HVC

PD1PD0

VREF1VREF0

OP AMP

ADDR6ADDR0




VOLATILE (5x16)

NONVOLATILE (14x16)

Band Gap1214V

VDD

GAIN

VREF1(2)

VREF1VREF0

Re

sist

or

Lad

der

VOUT1

100

k

1k

VDD

LAT1(1)

PD1PD0

VREF1VREF0

OP AMP


VDD

GAIN

VIHH

LAT0

LAT0(1)

VBG

VBG





MCP47CXBXX


Device Package Type

o

f C

ha

nn

els

Re

so

luti

on

(b

its)


o

f V

RE

F I

np

uts

o

f L

AT

In

pu

ts(3

)

o

f A

dd

ress

Pin

s

Me

mo

ry(2

)

GP

MT

P L

oca

tio

ns























MCP47CXBXX



























MCP47CXBXX

DC CHARACTERISTICS










VDDRR Note 3 Vms







MCP47CXBXX
















Power-Down Current






MCP47CXBXX











mdash 0016 0300 18V VDD 55V(2)










MCP47CXBXX





































MCP47CXBXX































MCP47CXBXX













Internal Band Gap












MCP47CXBXX










spec (at 55V)



Dynamic Performance








MCP47CXBXX






















RAM Value


mdash 3FFh 10-bit

mdash FFFh 12-bit



10-bit

12-bit



Power Requirements



mdash 10-bit

mdash 12-bit


MCP47CXBXX























MCP47CXBXX

DC Notes














MCP47CXBXX






VOUT

plusmn 05 LSb

Old Value

New Value









LATx

SCL

tLAT

Wx








MCP47CXBXX




VDD

tBORD

VOUT

VBOR

VOUT at High-Z


VPOR

tPOR2SIA = tPOR2OD

SDA

SCL

ACK Stop Start ACK

VOUT

tPDD tPDE














MCP47CXBXX


SCL

SDA

StartCondition

StopCondition

VIH

111

VIL

VIH VIHH

VIHHVC94


9091 93

92


MCP47CXBXX



Param No






























MCP47CXBXX




Param No











400 kHz mode 20 + 01Cb(4) 300 ns






400 kHz mode 20 + 01Cb 300 ns




400 kHz mode 20 + 01Cb 300 ns






9091 92

100101

103

106107

109 109 110

102

SCL

SDA In

SDA Out


MCP47CXBXX



Param No



400 kHz mode 20 + 01Cb 300 ns




































MCP47CXBXX

Timing Notes












MCP47CXBXX




Temperature Ranges









MCP47CXBXX

NOTES


MCP47CXBXX











MCP47CXBXX






MCP47CXBXX

22 Linearity Data










MCP47CXBXX










MCP47CXBXX










MCP47CXBXX








MCP47CXBXX








MCP47CXBXX








MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX

NOTES


MCP47CXBXX

30 PIN DESCRIPTIONS




Pin


DescriptionMSOP10L

DFN10L

QFN16L





5 5 456781415












MCP47CXBXX


Pin


DescriptionMSOP10L

DFN10L

QFN16L








mdash mdash 671415
















MCP47CXBXX




32 Ground (VSS)






















MCP47CXBXX







39 No Connect (NC)



MCP47CXBXX













bull Device Memory










411 POWER-ON RESET





MCP47CXBXX











VPOR

TPORD2OD

VDD(MIN)


VRAM


VBOR


VDD(MIN)

TPOR2OD

VBOR VPOR

VRAM

Case 1 VDD Ramp

Case 2 VDD Step

















POR Event


MCP47CXBXX

412 BROWN-OUT RESET












42 Device Memory


















MCP47CXBXX


dd

res

s

Function

Sin

gle

Du

al

Ad

dre

ss

Function

Sin

gle

(1)

Du

al(1

)

















Legend






MCP47CXBXX























MCP47CXBXX


dd

ress

Function

PORBOR Value

Ad

dre

ss

Function

PORBOR Value

8-B

it

10-B

it

12-B

it

8-B

it

10-B

it

12-B

it


7Fh 1FFh 7FFh


7Fh 1FFh 7FFh










0000h 0000h 0000h



0060h 0060h 0060h


0000h 0000h 0000h





Legend



Not Implemented




MCP47CXBXX

12-b

10-b

8-b








bit 15 bit 0

Legend



12-bit 10-bit 8-bit









MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual




powered down(2)





MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual







MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual




0 = 1x gain



0 = 1x gain














MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual









MCP47CXBXX

Singl

Dua







bit 15 bit 0

Legend



Single Dual







MCP47CXBXX

50 DAC CIRCUITRY










RS(2)

VREF

DACOutput

RS(1)

RS(2n ndash 1)

RS(2n ndash 2)

RS(2n ndash 3)

RS(2n)

VDD

VRL

VOUT

PD1PD0

VDD

PD1PD0

VDD

VW



Selection


ResistorLadder


Power-DownOperation

Power-DownOperation

Power-DownOperation

A (RL)

B

VREF1VREF0

Where


1024 (MCP47CXB1X)

4096 (MCP47CXB2X)



VDD

(~71 k)RRL

1kΩ

100

kΩ

Gain(1x or 2x)



MCP47CXBXX

51 Resistor Ladder












VW

Analog MUX


RS(2)

DACRegister

RS(1)

RS(2n ndash 1)

RS(2n ndash 2)

RS(2n ndash 3)

RS(2n)

VRL

RRL

RW(1)

RW(1)

RW(1)

RW(1)

RW(1)

RW(1)

2n ndash 1

2n ndash 2

1

0

2

2n ndash 3

RS

RRL256

--------------=

RS

RRL1024

------------------=

8-Bit Device

10-Bit Device

RS

RRL4096

------------------= 12-Bit Device


MCP47CXBXX




1 VDD pin voltage














VRL

VDD

Buffer

Re

fere

nce

VREF1VREF0

Se

lect

ion

VREF

Band Gap


VDD

VRL

Band Gap(1)

(1214V typical)

VDD

VDD

VREF





MCP47CXBXX
























VD

D

DA

C G

ain Max DAC Code(1)










VWVOUT

PD1PD0

VDD

PD1PD0

1kΩ

100

kΩ

Gain(1x or 2x)


MCP47CXBXX



bull POR Event

bull BOR Event



532 OUTPUT VOLTAGE
















0 1


Where


1024 (MCP47CXB1X)

256 (MCP47CXB0X)

VOUT


Where


1024 (10-bit)

256 (8-bit)

VS

VRL


StepVoltage

VREF

50 27 18 15 10

VS

122 mV 659 uV 439 uV 366 uV 244 uV 12-bit

488 mV 264 mV 176 mV 146 mV 977 uV 10-bit

195 mV 105 mV 703 mV 586 mV 391 mV 8-bit



MCP47CXBXX




















Time

DACx = A

VO

UT

VOUT(A)

VOUT(B)

DACx = B


T--------------------------------------------------=


Gain

VOUT RISO

RL CL

VCL

VW


MCP47CXBXX

54 Latch Pin (LAT)













DAC Wiper x

16 Clocks

LATSYNC

Transfer

Serial Shift Reg


LAT SYNCTransfer

DataComment

1 1 0 No Transfer

1 0 0 No Transfer


0 0 0 No Transfer

Vol DAC Register x





MCP47CXBXX






Configuration bits
























PD1 PD0 Function




1 1 Open circuit















MCP47CXBXX


DeviceVolatile DAC

Register ValueVRL

(1)LSb Gain

Selection (2)

VOUT(3)


CP

47C

VB

2X (

12

-bit)

1111 1111 1111 50V 50V4096 12207 1x VRL (40954096) 1 4998779

25V 25V4096 6104 1x VRL (40954096) 1 2499390

2x(2) VRL (40954096) 2) 4998779

0111 1111 1111 50V 50V4096 12207 1x VRL (20474096) 1) 2498779

25V 25V4096 6104 1x VRL (20474096) 1) 1249390

2x(2) VRL (20474096) 2) 2498779

0011 1111 1111 50V 50V4096 12207 1x VRL (10234096) 1) 1248779

25V 25V4096 6104 1x VRL (10234096) 1) 0624390

2x(2) VRL (10234096) 2) 1248779

0000 0000 0000 50V 50V4096 12207 1x VRL (04096) 1) 0

25V 25V4096 6104 1x VRL (04096) 1) 0

2x(2) VRL (04096) 2) 0

MC

P47

CV

B1X

(1

0-b

it)

11 1111 1111 50V 50V1024 48828 1x VRL (10231024) 1 4995117

25V 25V1024 24414 1x VRL (10231024) 1 2497559

2x(2) VRL (10231024) 2 4995117

01 1111 1111 50V 50V1024 48828 1x VRL (5111024) 1 2495117

25V 25V1024 24414 1x VRL (5111024) 1 1247559

2x(2) VRL (5111024) 2 2495117

00 1111 1111 50V 50V1024 48828 1x VRL (2551024) 1 1245117

25V 25V1024 24414 1x VRL (2551024) 1 0622559

2x(2) VRL (2551024) 2 1245117

00 0000 0000 50V 50V1024 48828 1x VRL (01024) 1 0

25V 25V1024 24414 1x VRL (01024) 1 0

2x(2) VRL (01024) 1 0

MC

P4

7CV

B0X

(8

-bit)

1111 1111 50V 50V256 195313 1x VRL (255256) 1 4980469

25V 25V256 97656 1x VRL (255256) 1 2490234

2x(2) VRL (255256) 2 4980469

0111 1111 50V 50V256 195313 1x VRL (127256) 1 2480469

25V 25V256 97656 1x VRL (127256) 1 1240234

2x(2) VRL (127256) 2 2480469

0011 1111 50V 50V256 195313 1x VRL (63256) 1 1230469

25V 25V256 97656 1x VRL (63256) 1 0615234

2x(2) VRL (63256) 2 1230469

0000 0000 50V 50V256 195313 1x VRL (0256) 1 0

25V 25V256 97656 1x VRL (0256) 1 0

2x(2) VRL (0256) 2 0





MCP47CXBXX

NOTES


MCP47CXBXX






61 Overview





bull PORBOR




bull Slope Control










63 PORBOR













SCLSCL

MCP47CVBXX

SDASDA

HostController


Other Devices

(Master)(Slave)


MCP47CXBXX








68 Slope Control


69 Pulse Gobbler




Address Byte

RW ACK

Acknowledge Bit

Slave Address

A6 A5 A4 A3


A2 A1 A0













MCP47CXBXX














P


RW = ReadWrite bit

RW


FS Mode HS Mode

HS Mode Continues

FS Mode


Control Byte

Sr


MCP47CXBXX

NOTES


MCP47CXBXX

70 DEVICE COMMANDS





71 Write Commands



72 Read Commands




Command

of Bit Clocks(1)



CodeMode

C1 C0 100 kHz 400 kHz 34 MHz (3)





1 1 Last Address 29 3448 13793 117241








MCP47CXBXX











75 Write Command














MCP47CXBXX











Memory Address

I2C ACK bit(1)




SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

0 0 x A

ADn

D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA

A

P

S xSAn

0 0

I2C Start Bit

I2C Slave Address



I2C Stop Bit(3)




Legend


MCP47CXBXX








00h Yes Yes

01h No Yes

08h Yes Yes

09h Yes Yes

0Ah Yes Yes



S Slave Address

RW

AC

K

Command

AC

K

Data Byte

AC

K

Data Byte

AC

K

P

Master S

SA

6S

A5

SA

4S

A3

SA

2S

A1

SA

0

0 AA

AD

4A

D3

AD

2A

D1

AD

0C

1C

0 x AA

D15

D14

D13

D12

D11

D10

D09

D08 AA

D07

D06

D05

D04

D03

D02

D01

D00 AA P



MCP47CXBXX 0 0 0 0




MCP47CXBXX 0 1 1 1




MCP47CXBXX






D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


AD4

AD3

AD2

AD1

AD0

0 0 x A

Write Command

P

AD4

AD3

AD2

AD1

AD0

0 0 x A

Write Command

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0 AAD4

AD3

AD2

AD1

AD0

0 0 x A


Memory Address

I2C ACK Bit (1)

0

ADn

A

P

S x

SAn

0 0

I2C Start Bit

I2C Slave Address



I2C Stop Bit(3)


Legend


MCP47CXBXX

76 Read Command




bull Single Read





761 SINGLE READ
















MCP47CXBXX








Memory Address(5)

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

1 1 x A

ADn

A

A

PS

x

SAn

1 1

I2C Start Bit

I2C Slave Address

I2C Write Bit

Read Command


I2C Stop Bit(3)

Dnn



Legend

Sr

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

Control Byte

A I2C ACK Bit(2)

I2C NACK Bit(4)A

1 I2C Read Bit



MCP47CXBXX









I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

1 A

A

P

S

SAn

I2C Start Bit


Control Byte

Legend

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


A I2C ACK Bit(2)



MCP47CXBXX


Read 1 Word Command

S Slave Address

RW

AC

K Command

AC

K

Master SS

A6

SA

5S

A4

SA

3S

A2

SA

1S

A0 0 1

AD

4A

D3

AD

2A

D1

AD

0C

1C

0x

1

Sr

Slave Address RW

AC

K

Data Byte AC

K

Data Byte AC

K

P


SA

6S

A5

SA

4S

A3

SA

2S

A1

SA

0

1 1

D1

5D

14

D1

3D

12

D11

D1

0D

09

D0

8 1

D0

7D

06

D0

5D

04

D0

3D

02

D0

1D

00 1 P


Master S 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 x 1

MCP47CXBXX 0 0

I2C Bus S 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 x 0





Master S 1 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 x 1

MCP47CXBXX 0 1

I2C Bus S 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 x 1







MCP47CXBXX








Memory Address(5)

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

1 1 x A

ADn

A

A

PS

x

SAn

1 1

I2C Start Bit

I2C Slave Address

I2C Write Bit

Read Command


I2C Stop Bit(3)



Legend

Sr

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

Control Byte

A I2C ACK Bit(2)

I2C NACK Bit(4)A

1 I2C Read Bit


0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A



MCP47CXBXX












S 0 A 0 x x 0 A


0 00 0 0 0 0 x P000


Legend

x




MCP47CXBXX















S 0 A 0 1 1 0 A


0 00 0 0 0 0 0 P000


Legend

0




S 0 A 0 0 1 0 A


0 00 0 0 0 0 1 P000


Legend

1


MCP47CXBXX







bull Motor Control








3 Send Stop bit


1 2 3 4 5 6 7 8 9SCL


Address Byte

Address Bits

RW

StopBit

Device

AC

K

Response

A3A4A5A6


MCP47CXBXX





5

Analog

VDD

1

2

3

8

6

VDD SDA

SCL

VSS

VOUT0

7

R1 R2

To MCU


R1 and R2









C2C1

MCP47CVBX2

Optional




Output

VREF

4 5

LATHVC

VOUT1

C4C3

Analog

VDD

1

2

3

8

6

VDD SDA

SCL

VSS

VOUT0

7To MCU

C2C1

MCP47CVBX2

Optional

Output

VREF

4

LATHVC

VOUT1

C5

Optional

VREF

C6

R1 R2

C4C3


MCP47CXBXX






















R1

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

VOR2 C1

RSENSE

Comp

VDD

VTRIP

Vtrip VOUT

R2R1 R2+--------------------

=


2N


MCP47CXBXX











R1

VCC+

VCC-

VO

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

VOUTR2 C1

R3

VCC+

VCC-

RSENSE

CompVTRIP

R23

R2R3

R2 R3+-------------------=

V23

VCC+R2 VCC-R3 +

R2 R3+------------------------------------------------------=

VTRIP

VOUTR23 V23R1+

R1 R23+---------------------------------------------------=

TheveninEquivalent

R1

R23

V23

VOUT VTRIP


2N

R3

VCC+

VCC-

VO

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

R2

VOUT

VIN

R1

R4 C1

VOA+

VOA+ = VOUT bull R4

R3 + R4


2N


R1

R2

R1


MCP47CXBXX








EQUATION 8-4

EQUATION 8-5






41V1 mV = 4100




R2ndash

R1---------

205ndash4096V-----------------=


R2

R1------

12---=

R4

R3 R4+ ------------------------

205V 05 4096V +15 4096V

-------------------------------------------------------23---= =

If R4 = 20 k then R3 = 10 k

R3

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

R2

VO

VIN

R1

R4C1

R5

Optional

VOA+

VCC+

VCC-

C1 = 01 microF



2N


R3 + R4


R1

R2

R1


VCC+R4 VCC-R5+

R4 R5+---------------------------------------------=

VIN+

VOUTR45 V45R3+

R3 R45+---------------------------------------------=

R45

R4R5

R4 R5+-------------------=

VO VIN+ 1R2

R1------+

VA

R2

R1------ ndash=



MCP47CXBXX

















R1

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBX2

VDD

I2C2-Wire

VREF

Optional

MCP47CVBX2

VDD

R2

01 microF

VOUT0

VOUT1

(DAC0)

(DAC1)

VOUT =


VOUT0 R2 + VOUT1 R1

R1 + R2


Where

RSENSE

Ib

Load

IL

VCC+

VCC-

VOUT

IL

VOUT

Rsense---------------

1+-------------=

Ib

IL

----=


VDD

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

(or VREF)


MCP47CXBXX






















Start



VDD

VDD

VSS VSS

MC

P4

7CX

BX

X

01 microFP

ICreg

Mic

roc

on

tro

lle

r

01 microF

SCL

VOUT

VREF SDA


MCP47CXBXX



bull Noise


81021 Noise








Pin

s

Type Code


Length Width

10 MSOP UN 300 490 1470

10 DFN MF 300 300 900

16 QFN MG 300 300 900



MCP47CXBXX

















Title Literature





MCP47CXBXX


0

47k






VDD SDA

SCL

(DGND) Plane

NCVOUT1 LATHVC

VSS

10 microF 47k

VOUT0

VREF

47Cx

Bxx

0

A1

A0


MCP47CXBXX






3e

3e

Part Number Code

MCP47CVB01-EMF BAJU

MCP47CVB11-EMF BAJX

MCP47CVB21-EMF BAJZ

MCP47CVB02-EMF BAJV

MCP47CVB12-EMF BAJY

MCP47CVB22-EMF BAKA

MCP47CMB01-EMF BAJV

MCP47CMB11-EMF BAJQ

MCP47CMB21-EMF BAJS

MCP47CMB02-EMF BAJP

MCP47CMB12-EMF BAJR

MCP47CMB22-EMF BAJT

XXXXXX

10-Lead MSOP

YWWNNN47CV01

Example

935256

XXXX


PIN 1

YYWWNNN

BAJU

Example

PIN 1

1935256


MCP47CXBXX

Part Number Code

MCP47CVB02-EMG AAD

MCP47CVB12-EMG AAE

MCP47CVB22-EMG AAF

MCP47CMB02-EMG AAA

MCP47CMB12-EMG AAB

MCP47CMB22-EMG AAC

XXX


PIN 1

XYYWWNNN


AAD

Example

PIN 1

1935256


MCP47CXBXX


UN


MCP47CXBXX


UN


MCP47CXBXX




MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX

NOTES


MCP47CXBXX

















MCP47CXBXX

NOTES


MCP47CXBXX




B1 Overview













SCL SCL

Slave

SDA SDA

Master


Other Devices



MCP47CXBXX










B3 I2C Operation





B311 Start Bit



B312 Data Bit


FIGURE B-3 Data Bit






SDA

SCL

S

1st Bit 2nd Bit



Comment

General Call A

Slave Address Valid

A


A


SDA

SCL

Data Bit

1st Bit 2nd Bit

A

8

D0

9

SDA

SCL


MCP47CXBXX





B315 Stop Bit













SDA

SCL

Sr = Repeated Start

1st Bit

SCL

SDA AA

P

1st Bit

SDA

SCL


SCL

SDA

StartCondition

StopCondition


Data orA Valid


MCP47CXBXX

B34 SLOPE CONTROL







B36 HS MODE











B361 Slope Control


B362 Pulse Gobbler




Address Byte

RW ACK

Acknowledge Bit

7-Bit Slave Address

A6 A5 A4 A3 A2 A1 A0


P

S = Start bit


A = Acknowledge bit


RW = ReadWrite bit

RW


FS Mode HS Mode

HS Mode Continues

FS Mode


Control Byte


MCP47CXBXX

B37 GENERAL CALL







00 0 0S 0 0 0 0 xx x x xA x x 0 A P


Second Byte

7-Bit Command



00 0 0S 0 0 0 0 xx x x xA x x 1 A


Second Byte

Master Address

xx x x x x x x A P




MCP47CXBXX

NOTES


MCP47CXBXX


C1 Resolution










Ideal

Measured 1

Measured 2

VLSb IDEAL VDD

2N

----------- or VREF

2N

-------------=


4032 64ndash ---------------------------------------------------------------=

VLSb


2N

1ndash-----------------------------------------------------------=

40h

3Fh

3Eh

03h

02h

01h

00h

Wip

er

Cod


VW ( Tap)

VS0

VS1

VS3

VS63

VS64


n =


MCP47CXBXX


















EFS


VLSb IDEAL ----------------------------------------------------------------=




EZS

VOUT(ZS)

VLSb(IDEAL)----------------------------=

Where





ET


--------------------------------------------------------------------------------------------------=


MCP47CXBXX







C9 Gain Error (EG)







Ideal Transfer

Actual

DAC Input Code0


Offset

Function

64 4032

VO

UT

Error (EOS)

TransferFunction

VO

UT

Ideal Transfer

Actual

DAC Input Code0


Gain Error (EG)

Function

64 4032 4095

VREF

TransferFunction

( code = 4032)


Where






EG


---------------------------------------------------------------------------------------------------- 100=


MCP47CXBXX











Where






EINL


--------------------------------------------------=

010001000

AnalogOutput(LSb)


1

2

3

4

5

6

0

7

110



INL = lt -1 LSb

INL = 05 LSb

INL = -1 LSb

Where




EDNL


------------------------------------------------------------------------------------ 1ndash=

010001000

AnalogOutput(LSb)

DAC Input Code

011 111100 101

1

2

3

4

5

6

0

7

DNL = 2 LSb

DNL = 05 LSb

110




MCP47CXBXX

C13 Settling Time







C16 -3 dB Bandwidth













Where

PSS is expressed in




55V 27Vndash 55V ----------------------------------------------------------------------------------------------------------=


MCP47CXBXX

NOTES


MCP47CXBXX





Temperature Range





Examples







PART NO X

TemperatureRange

Device

XX

Package

X(1)

Tape andReel


-


MCP47CXBXX

NOTES

















ISBN 978-1-5224-4636-1

DS20006089B-page 123































China - XianTel 86-29-8833-7252





India - PuneTel 91-20-4121-0141




































051419

Features

General Description

Applications






DC Characteristics









DC Notes

















Timing Notes



21 Electrical Data










22 Linearity Data















































































30 Pin Descriptions




32 Ground (VSS)







39 No Connect (NC)



411 Power-on Reset


412 Brown-out Reset

42 Device Memory














50 DAC Circuitry


51 Resistor Ladder















532 Output Voltage









54 Latch Pin (LAT)










61 Overview



63 PORBOR








68 Slope Control

69 Pulse Gobbler



70 Device Commands

71 Write Commands

72 Read Commands




75 Write Command










76 Read Command

761 Single Read






























EQUATION 8-4

EQUATION 8-5






























B1 Overview




B3 I2C Operation



FIGURE B-3 Data Bit









B34 Slope Control



B36 HS Mode


B37 General Call



C1 Resolution














C9 Gain Error (EG)










C13 Settling Time



C16 -3 dB Bandwidth









MCP47CXBXX


Device Package Type

o

f C

ha

nn

els

Re

so

luti

on

(b

its)


o

f V

RE

F I

np

uts

o

f L

AT

In

pu

ts(3

)

o

f A

dd

ress

Pin

s

Me

mo

ry(2

)

GP

MT

P L

oca

tio

ns























MCP47CXBXX



























MCP47CXBXX

DC CHARACTERISTICS










VDDRR Note 3 Vms







MCP47CXBXX
















Power-Down Current






MCP47CXBXX











mdash 0016 0300 18V VDD 55V(2)










MCP47CXBXX





































MCP47CXBXX































MCP47CXBXX













Internal Band Gap












MCP47CXBXX










spec (at 55V)



Dynamic Performance








MCP47CXBXX






















RAM Value


mdash 3FFh 10-bit

mdash FFFh 12-bit



10-bit

12-bit



Power Requirements



mdash 10-bit

mdash 12-bit


MCP47CXBXX























MCP47CXBXX

DC Notes














MCP47CXBXX






VOUT

plusmn 05 LSb

Old Value

New Value









LATx

SCL

tLAT

Wx








MCP47CXBXX




VDD

tBORD

VOUT

VBOR

VOUT at High-Z


VPOR

tPOR2SIA = tPOR2OD

SDA

SCL

ACK Stop Start ACK

VOUT

tPDD tPDE














MCP47CXBXX


SCL

SDA

StartCondition

StopCondition

VIH

111

VIL

VIH VIHH

VIHHVC94


9091 93

92


MCP47CXBXX



Param No






























MCP47CXBXX




Param No











400 kHz mode 20 + 01Cb(4) 300 ns






400 kHz mode 20 + 01Cb 300 ns




400 kHz mode 20 + 01Cb 300 ns






9091 92

100101

103

106107

109 109 110

102

SCL

SDA In

SDA Out


MCP47CXBXX



Param No



400 kHz mode 20 + 01Cb 300 ns




































MCP47CXBXX

Timing Notes












MCP47CXBXX




Temperature Ranges









MCP47CXBXX

NOTES


MCP47CXBXX











MCP47CXBXX






MCP47CXBXX

22 Linearity Data










MCP47CXBXX










MCP47CXBXX










MCP47CXBXX








MCP47CXBXX








MCP47CXBXX








MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX

NOTES


MCP47CXBXX

30 PIN DESCRIPTIONS




Pin


DescriptionMSOP10L

DFN10L

QFN16L





5 5 456781415












MCP47CXBXX


Pin


DescriptionMSOP10L

DFN10L

QFN16L








mdash mdash 671415
















MCP47CXBXX




32 Ground (VSS)






















MCP47CXBXX







39 No Connect (NC)



MCP47CXBXX













bull Device Memory










411 POWER-ON RESET





MCP47CXBXX











VPOR

TPORD2OD

VDD(MIN)


VRAM


VBOR


VDD(MIN)

TPOR2OD

VBOR VPOR

VRAM

Case 1 VDD Ramp

Case 2 VDD Step

















POR Event


MCP47CXBXX

412 BROWN-OUT RESET












42 Device Memory


















MCP47CXBXX


dd

res

s

Function

Sin

gle

Du

al

Ad

dre

ss

Function

Sin

gle

(1)

Du

al(1

)

















Legend






MCP47CXBXX























MCP47CXBXX


dd

ress

Function

PORBOR Value

Ad

dre

ss

Function

PORBOR Value

8-B

it

10-B

it

12-B

it

8-B

it

10-B

it

12-B

it


7Fh 1FFh 7FFh


7Fh 1FFh 7FFh










0000h 0000h 0000h



0060h 0060h 0060h


0000h 0000h 0000h





Legend



Not Implemented




MCP47CXBXX

12-b

10-b

8-b








bit 15 bit 0

Legend



12-bit 10-bit 8-bit









MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual




powered down(2)





MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual







MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual




0 = 1x gain



0 = 1x gain














MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual









MCP47CXBXX

Singl

Dua







bit 15 bit 0

Legend



Single Dual







MCP47CXBXX

50 DAC CIRCUITRY










RS(2)

VREF

DACOutput

RS(1)

RS(2n ndash 1)

RS(2n ndash 2)

RS(2n ndash 3)

RS(2n)

VDD

VRL

VOUT

PD1PD0

VDD

PD1PD0

VDD

VW



Selection


ResistorLadder


Power-DownOperation

Power-DownOperation

Power-DownOperation

A (RL)

B

VREF1VREF0

Where


1024 (MCP47CXB1X)

4096 (MCP47CXB2X)



VDD

(~71 k)RRL

1kΩ

100

kΩ

Gain(1x or 2x)



MCP47CXBXX

51 Resistor Ladder












VW

Analog MUX


RS(2)

DACRegister

RS(1)

RS(2n ndash 1)

RS(2n ndash 2)

RS(2n ndash 3)

RS(2n)

VRL

RRL

RW(1)

RW(1)

RW(1)

RW(1)

RW(1)

RW(1)

2n ndash 1

2n ndash 2

1

0

2

2n ndash 3

RS

RRL256

--------------=

RS

RRL1024

------------------=

8-Bit Device

10-Bit Device

RS

RRL4096

------------------= 12-Bit Device


MCP47CXBXX




1 VDD pin voltage














VRL

VDD

Buffer

Re

fere

nce

VREF1VREF0

Se

lect

ion

VREF

Band Gap


VDD

VRL

Band Gap(1)

(1214V typical)

VDD

VDD

VREF





MCP47CXBXX
























VD

D

DA

C G

ain Max DAC Code(1)










VWVOUT

PD1PD0

VDD

PD1PD0

1kΩ

100

kΩ

Gain(1x or 2x)


MCP47CXBXX



bull POR Event

bull BOR Event



532 OUTPUT VOLTAGE
















0 1


Where


1024 (MCP47CXB1X)

256 (MCP47CXB0X)

VOUT


Where


1024 (10-bit)

256 (8-bit)

VS

VRL


StepVoltage

VREF

50 27 18 15 10

VS

122 mV 659 uV 439 uV 366 uV 244 uV 12-bit

488 mV 264 mV 176 mV 146 mV 977 uV 10-bit

195 mV 105 mV 703 mV 586 mV 391 mV 8-bit



MCP47CXBXX




















Time

DACx = A

VO

UT

VOUT(A)

VOUT(B)

DACx = B


T--------------------------------------------------=


Gain

VOUT RISO

RL CL

VCL

VW


MCP47CXBXX

54 Latch Pin (LAT)













DAC Wiper x

16 Clocks

LATSYNC

Transfer

Serial Shift Reg


LAT SYNCTransfer

DataComment

1 1 0 No Transfer

1 0 0 No Transfer


0 0 0 No Transfer

Vol DAC Register x





MCP47CXBXX






Configuration bits
























PD1 PD0 Function




1 1 Open circuit















MCP47CXBXX


DeviceVolatile DAC

Register ValueVRL

(1)LSb Gain

Selection (2)

VOUT(3)


CP

47C

VB

2X (

12

-bit)

1111 1111 1111 50V 50V4096 12207 1x VRL (40954096) 1 4998779

25V 25V4096 6104 1x VRL (40954096) 1 2499390

2x(2) VRL (40954096) 2) 4998779

0111 1111 1111 50V 50V4096 12207 1x VRL (20474096) 1) 2498779

25V 25V4096 6104 1x VRL (20474096) 1) 1249390

2x(2) VRL (20474096) 2) 2498779

0011 1111 1111 50V 50V4096 12207 1x VRL (10234096) 1) 1248779

25V 25V4096 6104 1x VRL (10234096) 1) 0624390

2x(2) VRL (10234096) 2) 1248779

0000 0000 0000 50V 50V4096 12207 1x VRL (04096) 1) 0

25V 25V4096 6104 1x VRL (04096) 1) 0

2x(2) VRL (04096) 2) 0

MC

P47

CV

B1X

(1

0-b

it)

11 1111 1111 50V 50V1024 48828 1x VRL (10231024) 1 4995117

25V 25V1024 24414 1x VRL (10231024) 1 2497559

2x(2) VRL (10231024) 2 4995117

01 1111 1111 50V 50V1024 48828 1x VRL (5111024) 1 2495117

25V 25V1024 24414 1x VRL (5111024) 1 1247559

2x(2) VRL (5111024) 2 2495117

00 1111 1111 50V 50V1024 48828 1x VRL (2551024) 1 1245117

25V 25V1024 24414 1x VRL (2551024) 1 0622559

2x(2) VRL (2551024) 2 1245117

00 0000 0000 50V 50V1024 48828 1x VRL (01024) 1 0

25V 25V1024 24414 1x VRL (01024) 1 0

2x(2) VRL (01024) 1 0

MC

P4

7CV

B0X

(8

-bit)

1111 1111 50V 50V256 195313 1x VRL (255256) 1 4980469

25V 25V256 97656 1x VRL (255256) 1 2490234

2x(2) VRL (255256) 2 4980469

0111 1111 50V 50V256 195313 1x VRL (127256) 1 2480469

25V 25V256 97656 1x VRL (127256) 1 1240234

2x(2) VRL (127256) 2 2480469

0011 1111 50V 50V256 195313 1x VRL (63256) 1 1230469

25V 25V256 97656 1x VRL (63256) 1 0615234

2x(2) VRL (63256) 2 1230469

0000 0000 50V 50V256 195313 1x VRL (0256) 1 0

25V 25V256 97656 1x VRL (0256) 1 0

2x(2) VRL (0256) 2 0





MCP47CXBXX

NOTES


MCP47CXBXX






61 Overview





bull PORBOR




bull Slope Control










63 PORBOR













SCLSCL

MCP47CVBXX

SDASDA

HostController


Other Devices

(Master)(Slave)


MCP47CXBXX








68 Slope Control


69 Pulse Gobbler




Address Byte

RW ACK

Acknowledge Bit

Slave Address

A6 A5 A4 A3


A2 A1 A0













MCP47CXBXX














P


RW = ReadWrite bit

RW


FS Mode HS Mode

HS Mode Continues

FS Mode


Control Byte

Sr


MCP47CXBXX

NOTES


MCP47CXBXX

70 DEVICE COMMANDS





71 Write Commands



72 Read Commands




Command

of Bit Clocks(1)



CodeMode

C1 C0 100 kHz 400 kHz 34 MHz (3)





1 1 Last Address 29 3448 13793 117241








MCP47CXBXX











75 Write Command














MCP47CXBXX











Memory Address

I2C ACK bit(1)




SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

0 0 x A

ADn

D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA

A

P

S xSAn

0 0

I2C Start Bit

I2C Slave Address



I2C Stop Bit(3)




Legend


MCP47CXBXX








00h Yes Yes

01h No Yes

08h Yes Yes

09h Yes Yes

0Ah Yes Yes



S Slave Address

RW

AC

K

Command

AC

K

Data Byte

AC

K

Data Byte

AC

K

P

Master S

SA

6S

A5

SA

4S

A3

SA

2S

A1

SA

0

0 AA

AD

4A

D3

AD

2A

D1

AD

0C

1C

0 x AA

D15

D14

D13

D12

D11

D10

D09

D08 AA

D07

D06

D05

D04

D03

D02

D01

D00 AA P



MCP47CXBXX 0 0 0 0




MCP47CXBXX 0 1 1 1




MCP47CXBXX






D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


AD4

AD3

AD2

AD1

AD0

0 0 x A

Write Command

P

AD4

AD3

AD2

AD1

AD0

0 0 x A

Write Command

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0 AAD4

AD3

AD2

AD1

AD0

0 0 x A


Memory Address

I2C ACK Bit (1)

0

ADn

A

P

S x

SAn

0 0

I2C Start Bit

I2C Slave Address



I2C Stop Bit(3)


Legend


MCP47CXBXX

76 Read Command




bull Single Read





761 SINGLE READ
















MCP47CXBXX








Memory Address(5)

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

1 1 x A

ADn

A

A

PS

x

SAn

1 1

I2C Start Bit

I2C Slave Address

I2C Write Bit

Read Command


I2C Stop Bit(3)

Dnn



Legend

Sr

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

Control Byte

A I2C ACK Bit(2)

I2C NACK Bit(4)A

1 I2C Read Bit



MCP47CXBXX









I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

1 A

A

P

S

SAn

I2C Start Bit


Control Byte

Legend

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


A I2C ACK Bit(2)



MCP47CXBXX


Read 1 Word Command

S Slave Address

RW

AC

K Command

AC

K

Master SS

A6

SA

5S

A4

SA

3S

A2

SA

1S

A0 0 1

AD

4A

D3

AD

2A

D1

AD

0C

1C

0x

1

Sr

Slave Address RW

AC

K

Data Byte AC

K

Data Byte AC

K

P


SA

6S

A5

SA

4S

A3

SA

2S

A1

SA

0

1 1

D1

5D

14

D1

3D

12

D11

D1

0D

09

D0

8 1

D0

7D

06

D0

5D

04

D0

3D

02

D0

1D

00 1 P


Master S 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 x 1

MCP47CXBXX 0 0

I2C Bus S 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 x 0





Master S 1 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 x 1

MCP47CXBXX 0 1

I2C Bus S 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 x 1







MCP47CXBXX








Memory Address(5)

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

1 1 x A

ADn

A

A

PS

x

SAn

1 1

I2C Start Bit

I2C Slave Address

I2C Write Bit

Read Command


I2C Stop Bit(3)



Legend

Sr

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

Control Byte

A I2C ACK Bit(2)

I2C NACK Bit(4)A

1 I2C Read Bit


0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A



MCP47CXBXX












S 0 A 0 x x 0 A


0 00 0 0 0 0 x P000


Legend

x




MCP47CXBXX















S 0 A 0 1 1 0 A


0 00 0 0 0 0 0 P000


Legend

0




S 0 A 0 0 1 0 A


0 00 0 0 0 0 1 P000


Legend

1


MCP47CXBXX







bull Motor Control








3 Send Stop bit


1 2 3 4 5 6 7 8 9SCL


Address Byte

Address Bits

RW

StopBit

Device

AC

K

Response

A3A4A5A6


MCP47CXBXX





5

Analog

VDD

1

2

3

8

6

VDD SDA

SCL

VSS

VOUT0

7

R1 R2

To MCU


R1 and R2









C2C1

MCP47CVBX2

Optional




Output

VREF

4 5

LATHVC

VOUT1

C4C3

Analog

VDD

1

2

3

8

6

VDD SDA

SCL

VSS

VOUT0

7To MCU

C2C1

MCP47CVBX2

Optional

Output

VREF

4

LATHVC

VOUT1

C5

Optional

VREF

C6

R1 R2

C4C3


MCP47CXBXX






















R1

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

VOR2 C1

RSENSE

Comp

VDD

VTRIP

Vtrip VOUT

R2R1 R2+--------------------

=


2N


MCP47CXBXX











R1

VCC+

VCC-

VO

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

VOUTR2 C1

R3

VCC+

VCC-

RSENSE

CompVTRIP

R23

R2R3

R2 R3+-------------------=

V23

VCC+R2 VCC-R3 +

R2 R3+------------------------------------------------------=

VTRIP

VOUTR23 V23R1+

R1 R23+---------------------------------------------------=

TheveninEquivalent

R1

R23

V23

VOUT VTRIP


2N

R3

VCC+

VCC-

VO

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

R2

VOUT

VIN

R1

R4 C1

VOA+

VOA+ = VOUT bull R4

R3 + R4


2N


R1

R2

R1


MCP47CXBXX








EQUATION 8-4

EQUATION 8-5






41V1 mV = 4100




R2ndash

R1---------

205ndash4096V-----------------=


R2

R1------

12---=

R4

R3 R4+ ------------------------

205V 05 4096V +15 4096V

-------------------------------------------------------23---= =

If R4 = 20 k then R3 = 10 k

R3

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

R2

VO

VIN

R1

R4C1

R5

Optional

VOA+

VCC+

VCC-

C1 = 01 microF



2N


R3 + R4


R1

R2

R1


VCC+R4 VCC-R5+

R4 R5+---------------------------------------------=

VIN+

VOUTR45 V45R3+

R3 R45+---------------------------------------------=

R45

R4R5

R4 R5+-------------------=

VO VIN+ 1R2

R1------+

VA

R2

R1------ ndash=



MCP47CXBXX

















R1

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBX2

VDD

I2C2-Wire

VREF

Optional

MCP47CVBX2

VDD

R2

01 microF

VOUT0

VOUT1

(DAC0)

(DAC1)

VOUT =


VOUT0 R2 + VOUT1 R1

R1 + R2


Where

RSENSE

Ib

Load

IL

VCC+

VCC-

VOUT

IL

VOUT

Rsense---------------

1+-------------=

Ib

IL

----=


VDD

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

(or VREF)


MCP47CXBXX






















Start



VDD

VDD

VSS VSS

MC

P4

7CX

BX

X

01 microFP

ICreg

Mic

roc

on

tro

lle

r

01 microF

SCL

VOUT

VREF SDA


MCP47CXBXX



bull Noise


81021 Noise








Pin

s

Type Code


Length Width

10 MSOP UN 300 490 1470

10 DFN MF 300 300 900

16 QFN MG 300 300 900



MCP47CXBXX

















Title Literature





MCP47CXBXX


0

47k






VDD SDA

SCL

(DGND) Plane

NCVOUT1 LATHVC

VSS

10 microF 47k

VOUT0

VREF

47Cx

Bxx

0

A1

A0


MCP47CXBXX






3e

3e

Part Number Code

MCP47CVB01-EMF BAJU

MCP47CVB11-EMF BAJX

MCP47CVB21-EMF BAJZ

MCP47CVB02-EMF BAJV

MCP47CVB12-EMF BAJY

MCP47CVB22-EMF BAKA

MCP47CMB01-EMF BAJV

MCP47CMB11-EMF BAJQ

MCP47CMB21-EMF BAJS

MCP47CMB02-EMF BAJP

MCP47CMB12-EMF BAJR

MCP47CMB22-EMF BAJT

XXXXXX

10-Lead MSOP

YWWNNN47CV01

Example

935256

XXXX


PIN 1

YYWWNNN

BAJU

Example

PIN 1

1935256


MCP47CXBXX

Part Number Code

MCP47CVB02-EMG AAD

MCP47CVB12-EMG AAE

MCP47CVB22-EMG AAF

MCP47CMB02-EMG AAA

MCP47CMB12-EMG AAB

MCP47CMB22-EMG AAC

XXX


PIN 1

XYYWWNNN


AAD

Example

PIN 1

1935256


MCP47CXBXX


UN


MCP47CXBXX


UN


MCP47CXBXX




MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX

NOTES


MCP47CXBXX

















MCP47CXBXX

NOTES


MCP47CXBXX




B1 Overview













SCL SCL

Slave

SDA SDA

Master


Other Devices



MCP47CXBXX










B3 I2C Operation





B311 Start Bit



B312 Data Bit


FIGURE B-3 Data Bit






SDA

SCL

S

1st Bit 2nd Bit



Comment

General Call A

Slave Address Valid

A


A


SDA

SCL

Data Bit

1st Bit 2nd Bit

A

8

D0

9

SDA

SCL


MCP47CXBXX





B315 Stop Bit













SDA

SCL

Sr = Repeated Start

1st Bit

SCL

SDA AA

P

1st Bit

SDA

SCL


SCL

SDA

StartCondition

StopCondition


Data orA Valid


MCP47CXBXX

B34 SLOPE CONTROL







B36 HS MODE











B361 Slope Control


B362 Pulse Gobbler




Address Byte

RW ACK

Acknowledge Bit

7-Bit Slave Address

A6 A5 A4 A3 A2 A1 A0


P

S = Start bit


A = Acknowledge bit


RW = ReadWrite bit

RW


FS Mode HS Mode

HS Mode Continues

FS Mode


Control Byte


MCP47CXBXX

B37 GENERAL CALL







00 0 0S 0 0 0 0 xx x x xA x x 0 A P


Second Byte

7-Bit Command



00 0 0S 0 0 0 0 xx x x xA x x 1 A


Second Byte

Master Address

xx x x x x x x A P




MCP47CXBXX

NOTES


MCP47CXBXX


C1 Resolution










Ideal

Measured 1

Measured 2

VLSb IDEAL VDD

2N

----------- or VREF

2N

-------------=


4032 64ndash ---------------------------------------------------------------=

VLSb


2N

1ndash-----------------------------------------------------------=

40h

3Fh

3Eh

03h

02h

01h

00h

Wip

er

Cod


VW ( Tap)

VS0

VS1

VS3

VS63

VS64


n =


MCP47CXBXX


















EFS


VLSb IDEAL ----------------------------------------------------------------=




EZS

VOUT(ZS)

VLSb(IDEAL)----------------------------=

Where





ET


--------------------------------------------------------------------------------------------------=


MCP47CXBXX







C9 Gain Error (EG)







Ideal Transfer

Actual

DAC Input Code0


Offset

Function

64 4032

VO

UT

Error (EOS)

TransferFunction

VO

UT

Ideal Transfer

Actual

DAC Input Code0


Gain Error (EG)

Function

64 4032 4095

VREF

TransferFunction

( code = 4032)


Where






EG


---------------------------------------------------------------------------------------------------- 100=


MCP47CXBXX











Where






EINL


--------------------------------------------------=

010001000

AnalogOutput(LSb)


1

2

3

4

5

6

0

7

110



INL = lt -1 LSb

INL = 05 LSb

INL = -1 LSb

Where




EDNL


------------------------------------------------------------------------------------ 1ndash=

010001000

AnalogOutput(LSb)

DAC Input Code

011 111100 101

1

2

3

4

5

6

0

7

DNL = 2 LSb

DNL = 05 LSb

110




MCP47CXBXX

C13 Settling Time







C16 -3 dB Bandwidth













Where

PSS is expressed in




55V 27Vndash 55V ----------------------------------------------------------------------------------------------------------=


MCP47CXBXX

NOTES


MCP47CXBXX





Temperature Range





Examples







PART NO X

TemperatureRange

Device

XX

Package

X(1)

Tape andReel


-


MCP47CXBXX

NOTES

















ISBN 978-1-5224-4636-1

DS20006089B-page 123































China - XianTel 86-29-8833-7252





India - PuneTel 91-20-4121-0141




































051419

Features

General Description

Applications






DC Characteristics









DC Notes

















Timing Notes



21 Electrical Data










22 Linearity Data















































































30 Pin Descriptions




32 Ground (VSS)







39 No Connect (NC)



411 Power-on Reset


412 Brown-out Reset

42 Device Memory














50 DAC Circuitry


51 Resistor Ladder















532 Output Voltage









54 Latch Pin (LAT)










61 Overview



63 PORBOR








68 Slope Control

69 Pulse Gobbler



70 Device Commands

71 Write Commands

72 Read Commands




75 Write Command










76 Read Command

761 Single Read






























EQUATION 8-4

EQUATION 8-5






























B1 Overview




B3 I2C Operation



FIGURE B-3 Data Bit









B34 Slope Control



B36 HS Mode


B37 General Call



C1 Resolution














C9 Gain Error (EG)










C13 Settling Time



C16 -3 dB Bandwidth









MCP47CXBXX



























MCP47CXBXX

DC CHARACTERISTICS










VDDRR Note 3 Vms







MCP47CXBXX
















Power-Down Current






MCP47CXBXX











mdash 0016 0300 18V VDD 55V(2)










MCP47CXBXX





































MCP47CXBXX































MCP47CXBXX













Internal Band Gap












MCP47CXBXX










spec (at 55V)



Dynamic Performance








MCP47CXBXX






















RAM Value


mdash 3FFh 10-bit

mdash FFFh 12-bit



10-bit

12-bit



Power Requirements



mdash 10-bit

mdash 12-bit


MCP47CXBXX























MCP47CXBXX

DC Notes














MCP47CXBXX






VOUT

plusmn 05 LSb

Old Value

New Value









LATx

SCL

tLAT

Wx








MCP47CXBXX




VDD

tBORD

VOUT

VBOR

VOUT at High-Z


VPOR

tPOR2SIA = tPOR2OD

SDA

SCL

ACK Stop Start ACK

VOUT

tPDD tPDE














MCP47CXBXX


SCL

SDA

StartCondition

StopCondition

VIH

111

VIL

VIH VIHH

VIHHVC94


9091 93

92


MCP47CXBXX



Param No






























MCP47CXBXX




Param No











400 kHz mode 20 + 01Cb(4) 300 ns






400 kHz mode 20 + 01Cb 300 ns




400 kHz mode 20 + 01Cb 300 ns






9091 92

100101

103

106107

109 109 110

102

SCL

SDA In

SDA Out


MCP47CXBXX



Param No



400 kHz mode 20 + 01Cb 300 ns




































MCP47CXBXX

Timing Notes












MCP47CXBXX




Temperature Ranges









MCP47CXBXX

NOTES


MCP47CXBXX











MCP47CXBXX






MCP47CXBXX

22 Linearity Data










MCP47CXBXX










MCP47CXBXX










MCP47CXBXX








MCP47CXBXX








MCP47CXBXX








MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX

NOTES


MCP47CXBXX

30 PIN DESCRIPTIONS




Pin


DescriptionMSOP10L

DFN10L

QFN16L





5 5 456781415












MCP47CXBXX


Pin


DescriptionMSOP10L

DFN10L

QFN16L








mdash mdash 671415
















MCP47CXBXX




32 Ground (VSS)






















MCP47CXBXX







39 No Connect (NC)



MCP47CXBXX













bull Device Memory










411 POWER-ON RESET





MCP47CXBXX











VPOR

TPORD2OD

VDD(MIN)


VRAM


VBOR


VDD(MIN)

TPOR2OD

VBOR VPOR

VRAM

Case 1 VDD Ramp

Case 2 VDD Step

















POR Event


MCP47CXBXX

412 BROWN-OUT RESET












42 Device Memory


















MCP47CXBXX


dd

res

s

Function

Sin

gle

Du

al

Ad

dre

ss

Function

Sin

gle

(1)

Du

al(1

)

















Legend






MCP47CXBXX























MCP47CXBXX


dd

ress

Function

PORBOR Value

Ad

dre

ss

Function

PORBOR Value

8-B

it

10-B

it

12-B

it

8-B

it

10-B

it

12-B

it


7Fh 1FFh 7FFh


7Fh 1FFh 7FFh










0000h 0000h 0000h



0060h 0060h 0060h


0000h 0000h 0000h





Legend



Not Implemented




MCP47CXBXX

12-b

10-b

8-b








bit 15 bit 0

Legend



12-bit 10-bit 8-bit









MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual




powered down(2)





MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual







MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual




0 = 1x gain



0 = 1x gain














MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual









MCP47CXBXX

Singl

Dua







bit 15 bit 0

Legend



Single Dual







MCP47CXBXX

50 DAC CIRCUITRY










RS(2)

VREF

DACOutput

RS(1)

RS(2n ndash 1)

RS(2n ndash 2)

RS(2n ndash 3)

RS(2n)

VDD

VRL

VOUT

PD1PD0

VDD

PD1PD0

VDD

VW



Selection


ResistorLadder


Power-DownOperation

Power-DownOperation

Power-DownOperation

A (RL)

B

VREF1VREF0

Where


1024 (MCP47CXB1X)

4096 (MCP47CXB2X)



VDD

(~71 k)RRL

1kΩ

100

kΩ

Gain(1x or 2x)



MCP47CXBXX

51 Resistor Ladder












VW

Analog MUX


RS(2)

DACRegister

RS(1)

RS(2n ndash 1)

RS(2n ndash 2)

RS(2n ndash 3)

RS(2n)

VRL

RRL

RW(1)

RW(1)

RW(1)

RW(1)

RW(1)

RW(1)

2n ndash 1

2n ndash 2

1

0

2

2n ndash 3

RS

RRL256

--------------=

RS

RRL1024

------------------=

8-Bit Device

10-Bit Device

RS

RRL4096

------------------= 12-Bit Device


MCP47CXBXX




1 VDD pin voltage














VRL

VDD

Buffer

Re

fere

nce

VREF1VREF0

Se

lect

ion

VREF

Band Gap


VDD

VRL

Band Gap(1)

(1214V typical)

VDD

VDD

VREF





MCP47CXBXX
























VD

D

DA

C G

ain Max DAC Code(1)










VWVOUT

PD1PD0

VDD

PD1PD0

1kΩ

100

kΩ

Gain(1x or 2x)


MCP47CXBXX



bull POR Event

bull BOR Event



532 OUTPUT VOLTAGE
















0 1


Where


1024 (MCP47CXB1X)

256 (MCP47CXB0X)

VOUT


Where


1024 (10-bit)

256 (8-bit)

VS

VRL


StepVoltage

VREF

50 27 18 15 10

VS

122 mV 659 uV 439 uV 366 uV 244 uV 12-bit

488 mV 264 mV 176 mV 146 mV 977 uV 10-bit

195 mV 105 mV 703 mV 586 mV 391 mV 8-bit



MCP47CXBXX




















Time

DACx = A

VO

UT

VOUT(A)

VOUT(B)

DACx = B


T--------------------------------------------------=


Gain

VOUT RISO

RL CL

VCL

VW


MCP47CXBXX

54 Latch Pin (LAT)













DAC Wiper x

16 Clocks

LATSYNC

Transfer

Serial Shift Reg


LAT SYNCTransfer

DataComment

1 1 0 No Transfer

1 0 0 No Transfer


0 0 0 No Transfer

Vol DAC Register x





MCP47CXBXX






Configuration bits
























PD1 PD0 Function




1 1 Open circuit















MCP47CXBXX


DeviceVolatile DAC

Register ValueVRL

(1)LSb Gain

Selection (2)

VOUT(3)


CP

47C

VB

2X (

12

-bit)

1111 1111 1111 50V 50V4096 12207 1x VRL (40954096) 1 4998779

25V 25V4096 6104 1x VRL (40954096) 1 2499390

2x(2) VRL (40954096) 2) 4998779

0111 1111 1111 50V 50V4096 12207 1x VRL (20474096) 1) 2498779

25V 25V4096 6104 1x VRL (20474096) 1) 1249390

2x(2) VRL (20474096) 2) 2498779

0011 1111 1111 50V 50V4096 12207 1x VRL (10234096) 1) 1248779

25V 25V4096 6104 1x VRL (10234096) 1) 0624390

2x(2) VRL (10234096) 2) 1248779

0000 0000 0000 50V 50V4096 12207 1x VRL (04096) 1) 0

25V 25V4096 6104 1x VRL (04096) 1) 0

2x(2) VRL (04096) 2) 0

MC

P47

CV

B1X

(1

0-b

it)

11 1111 1111 50V 50V1024 48828 1x VRL (10231024) 1 4995117

25V 25V1024 24414 1x VRL (10231024) 1 2497559

2x(2) VRL (10231024) 2 4995117

01 1111 1111 50V 50V1024 48828 1x VRL (5111024) 1 2495117

25V 25V1024 24414 1x VRL (5111024) 1 1247559

2x(2) VRL (5111024) 2 2495117

00 1111 1111 50V 50V1024 48828 1x VRL (2551024) 1 1245117

25V 25V1024 24414 1x VRL (2551024) 1 0622559

2x(2) VRL (2551024) 2 1245117

00 0000 0000 50V 50V1024 48828 1x VRL (01024) 1 0

25V 25V1024 24414 1x VRL (01024) 1 0

2x(2) VRL (01024) 1 0

MC

P4

7CV

B0X

(8

-bit)

1111 1111 50V 50V256 195313 1x VRL (255256) 1 4980469

25V 25V256 97656 1x VRL (255256) 1 2490234

2x(2) VRL (255256) 2 4980469

0111 1111 50V 50V256 195313 1x VRL (127256) 1 2480469

25V 25V256 97656 1x VRL (127256) 1 1240234

2x(2) VRL (127256) 2 2480469

0011 1111 50V 50V256 195313 1x VRL (63256) 1 1230469

25V 25V256 97656 1x VRL (63256) 1 0615234

2x(2) VRL (63256) 2 1230469

0000 0000 50V 50V256 195313 1x VRL (0256) 1 0

25V 25V256 97656 1x VRL (0256) 1 0

2x(2) VRL (0256) 2 0





MCP47CXBXX

NOTES


MCP47CXBXX






61 Overview





bull PORBOR




bull Slope Control










63 PORBOR













SCLSCL

MCP47CVBXX

SDASDA

HostController


Other Devices

(Master)(Slave)


MCP47CXBXX








68 Slope Control


69 Pulse Gobbler




Address Byte

RW ACK

Acknowledge Bit

Slave Address

A6 A5 A4 A3


A2 A1 A0













MCP47CXBXX














P


RW = ReadWrite bit

RW


FS Mode HS Mode

HS Mode Continues

FS Mode


Control Byte

Sr


MCP47CXBXX

NOTES


MCP47CXBXX

70 DEVICE COMMANDS





71 Write Commands



72 Read Commands




Command

of Bit Clocks(1)



CodeMode

C1 C0 100 kHz 400 kHz 34 MHz (3)





1 1 Last Address 29 3448 13793 117241








MCP47CXBXX











75 Write Command














MCP47CXBXX











Memory Address

I2C ACK bit(1)




SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

0 0 x A

ADn

D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA

A

P

S xSAn

0 0

I2C Start Bit

I2C Slave Address



I2C Stop Bit(3)




Legend


MCP47CXBXX








00h Yes Yes

01h No Yes

08h Yes Yes

09h Yes Yes

0Ah Yes Yes



S Slave Address

RW

AC

K

Command

AC

K

Data Byte

AC

K

Data Byte

AC

K

P

Master S

SA

6S

A5

SA

4S

A3

SA

2S

A1

SA

0

0 AA

AD

4A

D3

AD

2A

D1

AD

0C

1C

0 x AA

D15

D14

D13

D12

D11

D10

D09

D08 AA

D07

D06

D05

D04

D03

D02

D01

D00 AA P



MCP47CXBXX 0 0 0 0




MCP47CXBXX 0 1 1 1




MCP47CXBXX






D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


AD4

AD3

AD2

AD1

AD0

0 0 x A

Write Command

P

AD4

AD3

AD2

AD1

AD0

0 0 x A

Write Command

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0 AAD4

AD3

AD2

AD1

AD0

0 0 x A


Memory Address

I2C ACK Bit (1)

0

ADn

A

P

S x

SAn

0 0

I2C Start Bit

I2C Slave Address



I2C Stop Bit(3)


Legend


MCP47CXBXX

76 Read Command




bull Single Read





761 SINGLE READ
















MCP47CXBXX








Memory Address(5)

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

1 1 x A

ADn

A

A

PS

x

SAn

1 1

I2C Start Bit

I2C Slave Address

I2C Write Bit

Read Command


I2C Stop Bit(3)

Dnn



Legend

Sr

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

Control Byte

A I2C ACK Bit(2)

I2C NACK Bit(4)A

1 I2C Read Bit



MCP47CXBXX









I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

1 A

A

P

S

SAn

I2C Start Bit


Control Byte

Legend

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


A I2C ACK Bit(2)



MCP47CXBXX


Read 1 Word Command

S Slave Address

RW

AC

K Command

AC

K

Master SS

A6

SA

5S

A4

SA

3S

A2

SA

1S

A0 0 1

AD

4A

D3

AD

2A

D1

AD

0C

1C

0x

1

Sr

Slave Address RW

AC

K

Data Byte AC

K

Data Byte AC

K

P


SA

6S

A5

SA

4S

A3

SA

2S

A1

SA

0

1 1

D1

5D

14

D1

3D

12

D11

D1

0D

09

D0

8 1

D0

7D

06

D0

5D

04

D0

3D

02

D0

1D

00 1 P


Master S 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 x 1

MCP47CXBXX 0 0

I2C Bus S 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 x 0





Master S 1 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 x 1

MCP47CXBXX 0 1

I2C Bus S 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 x 1







MCP47CXBXX








Memory Address(5)

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

1 1 x A

ADn

A

A

PS

x

SAn

1 1

I2C Start Bit

I2C Slave Address

I2C Write Bit

Read Command


I2C Stop Bit(3)



Legend

Sr

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

Control Byte

A I2C ACK Bit(2)

I2C NACK Bit(4)A

1 I2C Read Bit


0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A



MCP47CXBXX












S 0 A 0 x x 0 A


0 00 0 0 0 0 x P000


Legend

x




MCP47CXBXX















S 0 A 0 1 1 0 A


0 00 0 0 0 0 0 P000


Legend

0




S 0 A 0 0 1 0 A


0 00 0 0 0 0 1 P000


Legend

1


MCP47CXBXX







bull Motor Control








3 Send Stop bit


1 2 3 4 5 6 7 8 9SCL


Address Byte

Address Bits

RW

StopBit

Device

AC

K

Response

A3A4A5A6


MCP47CXBXX





5

Analog

VDD

1

2

3

8

6

VDD SDA

SCL

VSS

VOUT0

7

R1 R2

To MCU


R1 and R2









C2C1

MCP47CVBX2

Optional




Output

VREF

4 5

LATHVC

VOUT1

C4C3

Analog

VDD

1

2

3

8

6

VDD SDA

SCL

VSS

VOUT0

7To MCU

C2C1

MCP47CVBX2

Optional

Output

VREF

4

LATHVC

VOUT1

C5

Optional

VREF

C6

R1 R2

C4C3


MCP47CXBXX






















R1

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

VOR2 C1

RSENSE

Comp

VDD

VTRIP

Vtrip VOUT

R2R1 R2+--------------------

=


2N


MCP47CXBXX











R1

VCC+

VCC-

VO

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

VOUTR2 C1

R3

VCC+

VCC-

RSENSE

CompVTRIP

R23

R2R3

R2 R3+-------------------=

V23

VCC+R2 VCC-R3 +

R2 R3+------------------------------------------------------=

VTRIP

VOUTR23 V23R1+

R1 R23+---------------------------------------------------=

TheveninEquivalent

R1

R23

V23

VOUT VTRIP


2N

R3

VCC+

VCC-

VO

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

R2

VOUT

VIN

R1

R4 C1

VOA+

VOA+ = VOUT bull R4

R3 + R4


2N


R1

R2

R1


MCP47CXBXX








EQUATION 8-4

EQUATION 8-5






41V1 mV = 4100




R2ndash

R1---------

205ndash4096V-----------------=


R2

R1------

12---=

R4

R3 R4+ ------------------------

205V 05 4096V +15 4096V

-------------------------------------------------------23---= =

If R4 = 20 k then R3 = 10 k

R3

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

R2

VO

VIN

R1

R4C1

R5

Optional

VOA+

VCC+

VCC-

C1 = 01 microF



2N


R3 + R4


R1

R2

R1


VCC+R4 VCC-R5+

R4 R5+---------------------------------------------=

VIN+

VOUTR45 V45R3+

R3 R45+---------------------------------------------=

R45

R4R5

R4 R5+-------------------=

VO VIN+ 1R2

R1------+

VA

R2

R1------ ndash=



MCP47CXBXX

















R1

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBX2

VDD

I2C2-Wire

VREF

Optional

MCP47CVBX2

VDD

R2

01 microF

VOUT0

VOUT1

(DAC0)

(DAC1)

VOUT =


VOUT0 R2 + VOUT1 R1

R1 + R2


Where

RSENSE

Ib

Load

IL

VCC+

VCC-

VOUT

IL

VOUT

Rsense---------------

1+-------------=

Ib

IL

----=


VDD

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

(or VREF)


MCP47CXBXX






















Start



VDD

VDD

VSS VSS

MC

P4

7CX

BX

X

01 microFP

ICreg

Mic

roc

on

tro

lle

r

01 microF

SCL

VOUT

VREF SDA


MCP47CXBXX



bull Noise


81021 Noise








Pin

s

Type Code


Length Width

10 MSOP UN 300 490 1470

10 DFN MF 300 300 900

16 QFN MG 300 300 900



MCP47CXBXX

















Title Literature





MCP47CXBXX


0

47k






VDD SDA

SCL

(DGND) Plane

NCVOUT1 LATHVC

VSS

10 microF 47k

VOUT0

VREF

47Cx

Bxx

0

A1

A0


MCP47CXBXX






3e

3e

Part Number Code

MCP47CVB01-EMF BAJU

MCP47CVB11-EMF BAJX

MCP47CVB21-EMF BAJZ

MCP47CVB02-EMF BAJV

MCP47CVB12-EMF BAJY

MCP47CVB22-EMF BAKA

MCP47CMB01-EMF BAJV

MCP47CMB11-EMF BAJQ

MCP47CMB21-EMF BAJS

MCP47CMB02-EMF BAJP

MCP47CMB12-EMF BAJR

MCP47CMB22-EMF BAJT

XXXXXX

10-Lead MSOP

YWWNNN47CV01

Example

935256

XXXX


PIN 1

YYWWNNN

BAJU

Example

PIN 1

1935256


MCP47CXBXX

Part Number Code

MCP47CVB02-EMG AAD

MCP47CVB12-EMG AAE

MCP47CVB22-EMG AAF

MCP47CMB02-EMG AAA

MCP47CMB12-EMG AAB

MCP47CMB22-EMG AAC

XXX


PIN 1

XYYWWNNN


AAD

Example

PIN 1

1935256


MCP47CXBXX


UN


MCP47CXBXX


UN


MCP47CXBXX




MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX

NOTES


MCP47CXBXX

















MCP47CXBXX

NOTES


MCP47CXBXX




B1 Overview













SCL SCL

Slave

SDA SDA

Master


Other Devices



MCP47CXBXX










B3 I2C Operation





B311 Start Bit



B312 Data Bit


FIGURE B-3 Data Bit






SDA

SCL

S

1st Bit 2nd Bit



Comment

General Call A

Slave Address Valid

A


A


SDA

SCL

Data Bit

1st Bit 2nd Bit

A

8

D0

9

SDA

SCL


MCP47CXBXX





B315 Stop Bit













SDA

SCL

Sr = Repeated Start

1st Bit

SCL

SDA AA

P

1st Bit

SDA

SCL


SCL

SDA

StartCondition

StopCondition


Data orA Valid


MCP47CXBXX

B34 SLOPE CONTROL







B36 HS MODE











B361 Slope Control


B362 Pulse Gobbler




Address Byte

RW ACK

Acknowledge Bit

7-Bit Slave Address

A6 A5 A4 A3 A2 A1 A0


P

S = Start bit


A = Acknowledge bit


RW = ReadWrite bit

RW


FS Mode HS Mode

HS Mode Continues

FS Mode


Control Byte


MCP47CXBXX

B37 GENERAL CALL







00 0 0S 0 0 0 0 xx x x xA x x 0 A P


Second Byte

7-Bit Command



00 0 0S 0 0 0 0 xx x x xA x x 1 A


Second Byte

Master Address

xx x x x x x x A P




MCP47CXBXX

NOTES


MCP47CXBXX


C1 Resolution










Ideal

Measured 1

Measured 2

VLSb IDEAL VDD

2N

----------- or VREF

2N

-------------=


4032 64ndash ---------------------------------------------------------------=

VLSb


2N

1ndash-----------------------------------------------------------=

40h

3Fh

3Eh

03h

02h

01h

00h

Wip

er

Cod


VW ( Tap)

VS0

VS1

VS3

VS63

VS64


n =


MCP47CXBXX


















EFS


VLSb IDEAL ----------------------------------------------------------------=




EZS

VOUT(ZS)

VLSb(IDEAL)----------------------------=

Where





ET


--------------------------------------------------------------------------------------------------=


MCP47CXBXX







C9 Gain Error (EG)







Ideal Transfer

Actual

DAC Input Code0


Offset

Function

64 4032

VO

UT

Error (EOS)

TransferFunction

VO

UT

Ideal Transfer

Actual

DAC Input Code0


Gain Error (EG)

Function

64 4032 4095

VREF

TransferFunction

( code = 4032)


Where






EG


---------------------------------------------------------------------------------------------------- 100=


MCP47CXBXX











Where






EINL


--------------------------------------------------=

010001000

AnalogOutput(LSb)


1

2

3

4

5

6

0

7

110



INL = lt -1 LSb

INL = 05 LSb

INL = -1 LSb

Where




EDNL


------------------------------------------------------------------------------------ 1ndash=

010001000

AnalogOutput(LSb)

DAC Input Code

011 111100 101

1

2

3

4

5

6

0

7

DNL = 2 LSb

DNL = 05 LSb

110




MCP47CXBXX

C13 Settling Time







C16 -3 dB Bandwidth













Where

PSS is expressed in




55V 27Vndash 55V ----------------------------------------------------------------------------------------------------------=


MCP47CXBXX

NOTES


MCP47CXBXX





Temperature Range





Examples







PART NO X

TemperatureRange

Device

XX

Package

X(1)

Tape andReel


-


MCP47CXBXX

NOTES

















ISBN 978-1-5224-4636-1

DS20006089B-page 123































China - XianTel 86-29-8833-7252





India - PuneTel 91-20-4121-0141




































051419

Features

General Description

Applications






DC Characteristics









DC Notes

















Timing Notes



21 Electrical Data










22 Linearity Data















































































30 Pin Descriptions




32 Ground (VSS)







39 No Connect (NC)



411 Power-on Reset


412 Brown-out Reset

42 Device Memory














50 DAC Circuitry


51 Resistor Ladder















532 Output Voltage









54 Latch Pin (LAT)










61 Overview



63 PORBOR








68 Slope Control

69 Pulse Gobbler



70 Device Commands

71 Write Commands

72 Read Commands




75 Write Command










76 Read Command

761 Single Read






























EQUATION 8-4

EQUATION 8-5






























B1 Overview




B3 I2C Operation



FIGURE B-3 Data Bit









B34 Slope Control



B36 HS Mode


B37 General Call



C1 Resolution














C9 Gain Error (EG)










C13 Settling Time



C16 -3 dB Bandwidth









MCP47CXBXX

DC CHARACTERISTICS










VDDRR Note 3 Vms







MCP47CXBXX
















Power-Down Current






MCP47CXBXX











mdash 0016 0300 18V VDD 55V(2)










MCP47CXBXX





































MCP47CXBXX































MCP47CXBXX













Internal Band Gap












MCP47CXBXX










spec (at 55V)



Dynamic Performance








MCP47CXBXX






















RAM Value


mdash 3FFh 10-bit

mdash FFFh 12-bit



10-bit

12-bit



Power Requirements



mdash 10-bit

mdash 12-bit


MCP47CXBXX























MCP47CXBXX

DC Notes














MCP47CXBXX






VOUT

plusmn 05 LSb

Old Value

New Value









LATx

SCL

tLAT

Wx








MCP47CXBXX




VDD

tBORD

VOUT

VBOR

VOUT at High-Z


VPOR

tPOR2SIA = tPOR2OD

SDA

SCL

ACK Stop Start ACK

VOUT

tPDD tPDE














MCP47CXBXX


SCL

SDA

StartCondition

StopCondition

VIH

111

VIL

VIH VIHH

VIHHVC94


9091 93

92


MCP47CXBXX



Param No






























MCP47CXBXX




Param No











400 kHz mode 20 + 01Cb(4) 300 ns






400 kHz mode 20 + 01Cb 300 ns




400 kHz mode 20 + 01Cb 300 ns






9091 92

100101

103

106107

109 109 110

102

SCL

SDA In

SDA Out


MCP47CXBXX



Param No



400 kHz mode 20 + 01Cb 300 ns




































MCP47CXBXX

Timing Notes












MCP47CXBXX




Temperature Ranges









MCP47CXBXX

NOTES


MCP47CXBXX











MCP47CXBXX






MCP47CXBXX

22 Linearity Data










MCP47CXBXX










MCP47CXBXX










MCP47CXBXX








MCP47CXBXX








MCP47CXBXX








MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX

NOTES


MCP47CXBXX

30 PIN DESCRIPTIONS




Pin


DescriptionMSOP10L

DFN10L

QFN16L





5 5 456781415












MCP47CXBXX


Pin


DescriptionMSOP10L

DFN10L

QFN16L








mdash mdash 671415
















MCP47CXBXX




32 Ground (VSS)






















MCP47CXBXX







39 No Connect (NC)



MCP47CXBXX













bull Device Memory










411 POWER-ON RESET





MCP47CXBXX











VPOR

TPORD2OD

VDD(MIN)


VRAM


VBOR


VDD(MIN)

TPOR2OD

VBOR VPOR

VRAM

Case 1 VDD Ramp

Case 2 VDD Step

















POR Event


MCP47CXBXX

412 BROWN-OUT RESET












42 Device Memory


















MCP47CXBXX


dd

res

s

Function

Sin

gle

Du

al

Ad

dre

ss

Function

Sin

gle

(1)

Du

al(1

)

















Legend






MCP47CXBXX























MCP47CXBXX


dd

ress

Function

PORBOR Value

Ad

dre

ss

Function

PORBOR Value

8-B

it

10-B

it

12-B

it

8-B

it

10-B

it

12-B

it


7Fh 1FFh 7FFh


7Fh 1FFh 7FFh










0000h 0000h 0000h



0060h 0060h 0060h


0000h 0000h 0000h





Legend



Not Implemented




MCP47CXBXX

12-b

10-b

8-b








bit 15 bit 0

Legend



12-bit 10-bit 8-bit









MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual




powered down(2)





MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual







MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual




0 = 1x gain



0 = 1x gain














MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual









MCP47CXBXX

Singl

Dua







bit 15 bit 0

Legend



Single Dual







MCP47CXBXX

50 DAC CIRCUITRY










RS(2)

VREF

DACOutput

RS(1)

RS(2n ndash 1)

RS(2n ndash 2)

RS(2n ndash 3)

RS(2n)

VDD

VRL

VOUT

PD1PD0

VDD

PD1PD0

VDD

VW



Selection


ResistorLadder


Power-DownOperation

Power-DownOperation

Power-DownOperation

A (RL)

B

VREF1VREF0

Where


1024 (MCP47CXB1X)

4096 (MCP47CXB2X)



VDD

(~71 k)RRL

1kΩ

100

kΩ

Gain(1x or 2x)



MCP47CXBXX

51 Resistor Ladder












VW

Analog MUX


RS(2)

DACRegister

RS(1)

RS(2n ndash 1)

RS(2n ndash 2)

RS(2n ndash 3)

RS(2n)

VRL

RRL

RW(1)

RW(1)

RW(1)

RW(1)

RW(1)

RW(1)

2n ndash 1

2n ndash 2

1

0

2

2n ndash 3

RS

RRL256

--------------=

RS

RRL1024

------------------=

8-Bit Device

10-Bit Device

RS

RRL4096

------------------= 12-Bit Device


MCP47CXBXX




1 VDD pin voltage














VRL

VDD

Buffer

Re

fere

nce

VREF1VREF0

Se

lect

ion

VREF

Band Gap


VDD

VRL

Band Gap(1)

(1214V typical)

VDD

VDD

VREF





MCP47CXBXX
























VD

D

DA

C G

ain Max DAC Code(1)










VWVOUT

PD1PD0

VDD

PD1PD0

1kΩ

100

kΩ

Gain(1x or 2x)


MCP47CXBXX



bull POR Event

bull BOR Event



532 OUTPUT VOLTAGE
















0 1


Where


1024 (MCP47CXB1X)

256 (MCP47CXB0X)

VOUT


Where


1024 (10-bit)

256 (8-bit)

VS

VRL


StepVoltage

VREF

50 27 18 15 10

VS

122 mV 659 uV 439 uV 366 uV 244 uV 12-bit

488 mV 264 mV 176 mV 146 mV 977 uV 10-bit

195 mV 105 mV 703 mV 586 mV 391 mV 8-bit



MCP47CXBXX




















Time

DACx = A

VO

UT

VOUT(A)

VOUT(B)

DACx = B


T--------------------------------------------------=


Gain

VOUT RISO

RL CL

VCL

VW


MCP47CXBXX

54 Latch Pin (LAT)













DAC Wiper x

16 Clocks

LATSYNC

Transfer

Serial Shift Reg


LAT SYNCTransfer

DataComment

1 1 0 No Transfer

1 0 0 No Transfer


0 0 0 No Transfer

Vol DAC Register x





MCP47CXBXX






Configuration bits
























PD1 PD0 Function




1 1 Open circuit















MCP47CXBXX


DeviceVolatile DAC

Register ValueVRL

(1)LSb Gain

Selection (2)

VOUT(3)


CP

47C

VB

2X (

12

-bit)

1111 1111 1111 50V 50V4096 12207 1x VRL (40954096) 1 4998779

25V 25V4096 6104 1x VRL (40954096) 1 2499390

2x(2) VRL (40954096) 2) 4998779

0111 1111 1111 50V 50V4096 12207 1x VRL (20474096) 1) 2498779

25V 25V4096 6104 1x VRL (20474096) 1) 1249390

2x(2) VRL (20474096) 2) 2498779

0011 1111 1111 50V 50V4096 12207 1x VRL (10234096) 1) 1248779

25V 25V4096 6104 1x VRL (10234096) 1) 0624390

2x(2) VRL (10234096) 2) 1248779

0000 0000 0000 50V 50V4096 12207 1x VRL (04096) 1) 0

25V 25V4096 6104 1x VRL (04096) 1) 0

2x(2) VRL (04096) 2) 0

MC

P47

CV

B1X

(1

0-b

it)

11 1111 1111 50V 50V1024 48828 1x VRL (10231024) 1 4995117

25V 25V1024 24414 1x VRL (10231024) 1 2497559

2x(2) VRL (10231024) 2 4995117

01 1111 1111 50V 50V1024 48828 1x VRL (5111024) 1 2495117

25V 25V1024 24414 1x VRL (5111024) 1 1247559

2x(2) VRL (5111024) 2 2495117

00 1111 1111 50V 50V1024 48828 1x VRL (2551024) 1 1245117

25V 25V1024 24414 1x VRL (2551024) 1 0622559

2x(2) VRL (2551024) 2 1245117

00 0000 0000 50V 50V1024 48828 1x VRL (01024) 1 0

25V 25V1024 24414 1x VRL (01024) 1 0

2x(2) VRL (01024) 1 0

MC

P4

7CV

B0X

(8

-bit)

1111 1111 50V 50V256 195313 1x VRL (255256) 1 4980469

25V 25V256 97656 1x VRL (255256) 1 2490234

2x(2) VRL (255256) 2 4980469

0111 1111 50V 50V256 195313 1x VRL (127256) 1 2480469

25V 25V256 97656 1x VRL (127256) 1 1240234

2x(2) VRL (127256) 2 2480469

0011 1111 50V 50V256 195313 1x VRL (63256) 1 1230469

25V 25V256 97656 1x VRL (63256) 1 0615234

2x(2) VRL (63256) 2 1230469

0000 0000 50V 50V256 195313 1x VRL (0256) 1 0

25V 25V256 97656 1x VRL (0256) 1 0

2x(2) VRL (0256) 2 0





MCP47CXBXX

NOTES


MCP47CXBXX






61 Overview





bull PORBOR




bull Slope Control










63 PORBOR













SCLSCL

MCP47CVBXX

SDASDA

HostController


Other Devices

(Master)(Slave)


MCP47CXBXX








68 Slope Control


69 Pulse Gobbler




Address Byte

RW ACK

Acknowledge Bit

Slave Address

A6 A5 A4 A3


A2 A1 A0













MCP47CXBXX














P


RW = ReadWrite bit

RW


FS Mode HS Mode

HS Mode Continues

FS Mode


Control Byte

Sr


MCP47CXBXX

NOTES


MCP47CXBXX

70 DEVICE COMMANDS





71 Write Commands



72 Read Commands




Command

of Bit Clocks(1)



CodeMode

C1 C0 100 kHz 400 kHz 34 MHz (3)





1 1 Last Address 29 3448 13793 117241








MCP47CXBXX











75 Write Command














MCP47CXBXX











Memory Address

I2C ACK bit(1)




SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

0 0 x A

ADn

D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA

A

P

S xSAn

0 0

I2C Start Bit

I2C Slave Address



I2C Stop Bit(3)




Legend


MCP47CXBXX








00h Yes Yes

01h No Yes

08h Yes Yes

09h Yes Yes

0Ah Yes Yes



S Slave Address

RW

AC

K

Command

AC

K

Data Byte

AC

K

Data Byte

AC

K

P

Master S

SA

6S

A5

SA

4S

A3

SA

2S

A1

SA

0

0 AA

AD

4A

D3

AD

2A

D1

AD

0C

1C

0 x AA

D15

D14

D13

D12

D11

D10

D09

D08 AA

D07

D06

D05

D04

D03

D02

D01

D00 AA P



MCP47CXBXX 0 0 0 0




MCP47CXBXX 0 1 1 1




MCP47CXBXX






D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


AD4

AD3

AD2

AD1

AD0

0 0 x A

Write Command

P

AD4

AD3

AD2

AD1

AD0

0 0 x A

Write Command

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0 AAD4

AD3

AD2

AD1

AD0

0 0 x A


Memory Address

I2C ACK Bit (1)

0

ADn

A

P

S x

SAn

0 0

I2C Start Bit

I2C Slave Address



I2C Stop Bit(3)


Legend


MCP47CXBXX

76 Read Command




bull Single Read





761 SINGLE READ
















MCP47CXBXX








Memory Address(5)

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

1 1 x A

ADn

A

A

PS

x

SAn

1 1

I2C Start Bit

I2C Slave Address

I2C Write Bit

Read Command


I2C Stop Bit(3)

Dnn



Legend

Sr

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

Control Byte

A I2C ACK Bit(2)

I2C NACK Bit(4)A

1 I2C Read Bit



MCP47CXBXX









I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

1 A

A

P

S

SAn

I2C Start Bit


Control Byte

Legend

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


A I2C ACK Bit(2)



MCP47CXBXX


Read 1 Word Command

S Slave Address

RW

AC

K Command

AC

K

Master SS

A6

SA

5S

A4

SA

3S

A2

SA

1S

A0 0 1

AD

4A

D3

AD

2A

D1

AD

0C

1C

0x

1

Sr

Slave Address RW

AC

K

Data Byte AC

K

Data Byte AC

K

P


SA

6S

A5

SA

4S

A3

SA

2S

A1

SA

0

1 1

D1

5D

14

D1

3D

12

D11

D1

0D

09

D0

8 1

D0

7D

06

D0

5D

04

D0

3D

02

D0

1D

00 1 P


Master S 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 x 1

MCP47CXBXX 0 0

I2C Bus S 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 x 0





Master S 1 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 x 1

MCP47CXBXX 0 1

I2C Bus S 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 x 1







MCP47CXBXX








Memory Address(5)

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

1 1 x A

ADn

A

A

PS

x

SAn

1 1

I2C Start Bit

I2C Slave Address

I2C Write Bit

Read Command


I2C Stop Bit(3)



Legend

Sr

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

Control Byte

A I2C ACK Bit(2)

I2C NACK Bit(4)A

1 I2C Read Bit


0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A



MCP47CXBXX












S 0 A 0 x x 0 A


0 00 0 0 0 0 x P000


Legend

x




MCP47CXBXX















S 0 A 0 1 1 0 A


0 00 0 0 0 0 0 P000


Legend

0




S 0 A 0 0 1 0 A


0 00 0 0 0 0 1 P000


Legend

1


MCP47CXBXX







bull Motor Control








3 Send Stop bit


1 2 3 4 5 6 7 8 9SCL


Address Byte

Address Bits

RW

StopBit

Device

AC

K

Response

A3A4A5A6


MCP47CXBXX





5

Analog

VDD

1

2

3

8

6

VDD SDA

SCL

VSS

VOUT0

7

R1 R2

To MCU


R1 and R2









C2C1

MCP47CVBX2

Optional




Output

VREF

4 5

LATHVC

VOUT1

C4C3

Analog

VDD

1

2

3

8

6

VDD SDA

SCL

VSS

VOUT0

7To MCU

C2C1

MCP47CVBX2

Optional

Output

VREF

4

LATHVC

VOUT1

C5

Optional

VREF

C6

R1 R2

C4C3


MCP47CXBXX






















R1

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

VOR2 C1

RSENSE

Comp

VDD

VTRIP

Vtrip VOUT

R2R1 R2+--------------------

=


2N


MCP47CXBXX











R1

VCC+

VCC-

VO

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

VOUTR2 C1

R3

VCC+

VCC-

RSENSE

CompVTRIP

R23

R2R3

R2 R3+-------------------=

V23

VCC+R2 VCC-R3 +

R2 R3+------------------------------------------------------=

VTRIP

VOUTR23 V23R1+

R1 R23+---------------------------------------------------=

TheveninEquivalent

R1

R23

V23

VOUT VTRIP


2N

R3

VCC+

VCC-

VO

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

R2

VOUT

VIN

R1

R4 C1

VOA+

VOA+ = VOUT bull R4

R3 + R4


2N


R1

R2

R1


MCP47CXBXX








EQUATION 8-4

EQUATION 8-5






41V1 mV = 4100




R2ndash

R1---------

205ndash4096V-----------------=


R2

R1------

12---=

R4

R3 R4+ ------------------------

205V 05 4096V +15 4096V

-------------------------------------------------------23---= =

If R4 = 20 k then R3 = 10 k

R3

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

R2

VO

VIN

R1

R4C1

R5

Optional

VOA+

VCC+

VCC-

C1 = 01 microF



2N


R3 + R4


R1

R2

R1


VCC+R4 VCC-R5+

R4 R5+---------------------------------------------=

VIN+

VOUTR45 V45R3+

R3 R45+---------------------------------------------=

R45

R4R5

R4 R5+-------------------=

VO VIN+ 1R2

R1------+

VA

R2

R1------ ndash=



MCP47CXBXX

















R1

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBX2

VDD

I2C2-Wire

VREF

Optional

MCP47CVBX2

VDD

R2

01 microF

VOUT0

VOUT1

(DAC0)

(DAC1)

VOUT =


VOUT0 R2 + VOUT1 R1

R1 + R2


Where

RSENSE

Ib

Load

IL

VCC+

VCC-

VOUT

IL

VOUT

Rsense---------------

1+-------------=

Ib

IL

----=


VDD

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

(or VREF)


MCP47CXBXX






















Start



VDD

VDD

VSS VSS

MC

P4

7CX

BX

X

01 microFP

ICreg

Mic

roc

on

tro

lle

r

01 microF

SCL

VOUT

VREF SDA


MCP47CXBXX



bull Noise


81021 Noise








Pin

s

Type Code


Length Width

10 MSOP UN 300 490 1470

10 DFN MF 300 300 900

16 QFN MG 300 300 900



MCP47CXBXX

















Title Literature





MCP47CXBXX


0

47k






VDD SDA

SCL

(DGND) Plane

NCVOUT1 LATHVC

VSS

10 microF 47k

VOUT0

VREF

47Cx

Bxx

0

A1

A0


MCP47CXBXX






3e

3e

Part Number Code

MCP47CVB01-EMF BAJU

MCP47CVB11-EMF BAJX

MCP47CVB21-EMF BAJZ

MCP47CVB02-EMF BAJV

MCP47CVB12-EMF BAJY

MCP47CVB22-EMF BAKA

MCP47CMB01-EMF BAJV

MCP47CMB11-EMF BAJQ

MCP47CMB21-EMF BAJS

MCP47CMB02-EMF BAJP

MCP47CMB12-EMF BAJR

MCP47CMB22-EMF BAJT

XXXXXX

10-Lead MSOP

YWWNNN47CV01

Example

935256

XXXX


PIN 1

YYWWNNN

BAJU

Example

PIN 1

1935256


MCP47CXBXX

Part Number Code

MCP47CVB02-EMG AAD

MCP47CVB12-EMG AAE

MCP47CVB22-EMG AAF

MCP47CMB02-EMG AAA

MCP47CMB12-EMG AAB

MCP47CMB22-EMG AAC

XXX


PIN 1

XYYWWNNN


AAD

Example

PIN 1

1935256


MCP47CXBXX


UN


MCP47CXBXX


UN


MCP47CXBXX




MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX

NOTES


MCP47CXBXX

















MCP47CXBXX

NOTES


MCP47CXBXX




B1 Overview













SCL SCL

Slave

SDA SDA

Master


Other Devices



MCP47CXBXX










B3 I2C Operation





B311 Start Bit



B312 Data Bit


FIGURE B-3 Data Bit






SDA

SCL

S

1st Bit 2nd Bit



Comment

General Call A

Slave Address Valid

A


A


SDA

SCL

Data Bit

1st Bit 2nd Bit

A

8

D0

9

SDA

SCL


MCP47CXBXX





B315 Stop Bit













SDA

SCL

Sr = Repeated Start

1st Bit

SCL

SDA AA

P

1st Bit

SDA

SCL


SCL

SDA

StartCondition

StopCondition


Data orA Valid


MCP47CXBXX

B34 SLOPE CONTROL







B36 HS MODE











B361 Slope Control


B362 Pulse Gobbler




Address Byte

RW ACK

Acknowledge Bit

7-Bit Slave Address

A6 A5 A4 A3 A2 A1 A0


P

S = Start bit


A = Acknowledge bit


RW = ReadWrite bit

RW


FS Mode HS Mode

HS Mode Continues

FS Mode


Control Byte


MCP47CXBXX

B37 GENERAL CALL







00 0 0S 0 0 0 0 xx x x xA x x 0 A P


Second Byte

7-Bit Command



00 0 0S 0 0 0 0 xx x x xA x x 1 A


Second Byte

Master Address

xx x x x x x x A P




MCP47CXBXX

NOTES


MCP47CXBXX


C1 Resolution










Ideal

Measured 1

Measured 2

VLSb IDEAL VDD

2N

----------- or VREF

2N

-------------=


4032 64ndash ---------------------------------------------------------------=

VLSb


2N

1ndash-----------------------------------------------------------=

40h

3Fh

3Eh

03h

02h

01h

00h

Wip

er

Cod


VW ( Tap)

VS0

VS1

VS3

VS63

VS64


n =


MCP47CXBXX


















EFS


VLSb IDEAL ----------------------------------------------------------------=




EZS

VOUT(ZS)

VLSb(IDEAL)----------------------------=

Where





ET


--------------------------------------------------------------------------------------------------=


MCP47CXBXX







C9 Gain Error (EG)







Ideal Transfer

Actual

DAC Input Code0


Offset

Function

64 4032

VO

UT

Error (EOS)

TransferFunction

VO

UT

Ideal Transfer

Actual

DAC Input Code0


Gain Error (EG)

Function

64 4032 4095

VREF

TransferFunction

( code = 4032)


Where






EG


---------------------------------------------------------------------------------------------------- 100=


MCP47CXBXX











Where






EINL


--------------------------------------------------=

010001000

AnalogOutput(LSb)


1

2

3

4

5

6

0

7

110



INL = lt -1 LSb

INL = 05 LSb

INL = -1 LSb

Where




EDNL


------------------------------------------------------------------------------------ 1ndash=

010001000

AnalogOutput(LSb)

DAC Input Code

011 111100 101

1

2

3

4

5

6

0

7

DNL = 2 LSb

DNL = 05 LSb

110




MCP47CXBXX

C13 Settling Time







C16 -3 dB Bandwidth













Where

PSS is expressed in




55V 27Vndash 55V ----------------------------------------------------------------------------------------------------------=


MCP47CXBXX

NOTES


MCP47CXBXX





Temperature Range





Examples







PART NO X

TemperatureRange

Device

XX

Package

X(1)

Tape andReel


-


MCP47CXBXX

NOTES

















ISBN 978-1-5224-4636-1

DS20006089B-page 123































China - XianTel 86-29-8833-7252





India - PuneTel 91-20-4121-0141




































051419

Features

General Description

Applications






DC Characteristics









DC Notes

















Timing Notes



21 Electrical Data










22 Linearity Data















































































30 Pin Descriptions




32 Ground (VSS)







39 No Connect (NC)



411 Power-on Reset


412 Brown-out Reset

42 Device Memory














50 DAC Circuitry


51 Resistor Ladder















532 Output Voltage









54 Latch Pin (LAT)










61 Overview



63 PORBOR








68 Slope Control

69 Pulse Gobbler



70 Device Commands

71 Write Commands

72 Read Commands




75 Write Command










76 Read Command

761 Single Read






























EQUATION 8-4

EQUATION 8-5






























B1 Overview




B3 I2C Operation



FIGURE B-3 Data Bit









B34 Slope Control



B36 HS Mode


B37 General Call



C1 Resolution














C9 Gain Error (EG)










C13 Settling Time



C16 -3 dB Bandwidth









MCP47CXBXX
















Power-Down Current






MCP47CXBXX











mdash 0016 0300 18V VDD 55V(2)










MCP47CXBXX





































MCP47CXBXX































MCP47CXBXX













Internal Band Gap












MCP47CXBXX










spec (at 55V)



Dynamic Performance








MCP47CXBXX






















RAM Value


mdash 3FFh 10-bit

mdash FFFh 12-bit



10-bit

12-bit



Power Requirements



mdash 10-bit

mdash 12-bit


MCP47CXBXX























MCP47CXBXX

DC Notes














MCP47CXBXX






VOUT

plusmn 05 LSb

Old Value

New Value









LATx

SCL

tLAT

Wx








MCP47CXBXX




VDD

tBORD

VOUT

VBOR

VOUT at High-Z


VPOR

tPOR2SIA = tPOR2OD

SDA

SCL

ACK Stop Start ACK

VOUT

tPDD tPDE














MCP47CXBXX


SCL

SDA

StartCondition

StopCondition

VIH

111

VIL

VIH VIHH

VIHHVC94


9091 93

92


MCP47CXBXX



Param No






























MCP47CXBXX




Param No











400 kHz mode 20 + 01Cb(4) 300 ns






400 kHz mode 20 + 01Cb 300 ns




400 kHz mode 20 + 01Cb 300 ns






9091 92

100101

103

106107

109 109 110

102

SCL

SDA In

SDA Out


MCP47CXBXX



Param No



400 kHz mode 20 + 01Cb 300 ns




































MCP47CXBXX

Timing Notes












MCP47CXBXX




Temperature Ranges









MCP47CXBXX

NOTES


MCP47CXBXX











MCP47CXBXX






MCP47CXBXX

22 Linearity Data










MCP47CXBXX










MCP47CXBXX










MCP47CXBXX








MCP47CXBXX








MCP47CXBXX








MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX

NOTES


MCP47CXBXX

30 PIN DESCRIPTIONS




Pin


DescriptionMSOP10L

DFN10L

QFN16L





5 5 456781415












MCP47CXBXX


Pin


DescriptionMSOP10L

DFN10L

QFN16L








mdash mdash 671415
















MCP47CXBXX




32 Ground (VSS)






















MCP47CXBXX







39 No Connect (NC)



MCP47CXBXX













bull Device Memory










411 POWER-ON RESET





MCP47CXBXX











VPOR

TPORD2OD

VDD(MIN)


VRAM


VBOR


VDD(MIN)

TPOR2OD

VBOR VPOR

VRAM

Case 1 VDD Ramp

Case 2 VDD Step

















POR Event


MCP47CXBXX

412 BROWN-OUT RESET












42 Device Memory


















MCP47CXBXX


dd

res

s

Function

Sin

gle

Du

al

Ad

dre

ss

Function

Sin

gle

(1)

Du

al(1

)

















Legend






MCP47CXBXX























MCP47CXBXX


dd

ress

Function

PORBOR Value

Ad

dre

ss

Function

PORBOR Value

8-B

it

10-B

it

12-B

it

8-B

it

10-B

it

12-B

it


7Fh 1FFh 7FFh


7Fh 1FFh 7FFh










0000h 0000h 0000h



0060h 0060h 0060h


0000h 0000h 0000h





Legend



Not Implemented




MCP47CXBXX

12-b

10-b

8-b








bit 15 bit 0

Legend



12-bit 10-bit 8-bit









MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual




powered down(2)





MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual







MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual




0 = 1x gain



0 = 1x gain














MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual









MCP47CXBXX

Singl

Dua







bit 15 bit 0

Legend



Single Dual







MCP47CXBXX

50 DAC CIRCUITRY










RS(2)

VREF

DACOutput

RS(1)

RS(2n ndash 1)

RS(2n ndash 2)

RS(2n ndash 3)

RS(2n)

VDD

VRL

VOUT

PD1PD0

VDD

PD1PD0

VDD

VW



Selection


ResistorLadder


Power-DownOperation

Power-DownOperation

Power-DownOperation

A (RL)

B

VREF1VREF0

Where


1024 (MCP47CXB1X)

4096 (MCP47CXB2X)



VDD

(~71 k)RRL

1kΩ

100

kΩ

Gain(1x or 2x)



MCP47CXBXX

51 Resistor Ladder












VW

Analog MUX


RS(2)

DACRegister

RS(1)

RS(2n ndash 1)

RS(2n ndash 2)

RS(2n ndash 3)

RS(2n)

VRL

RRL

RW(1)

RW(1)

RW(1)

RW(1)

RW(1)

RW(1)

2n ndash 1

2n ndash 2

1

0

2

2n ndash 3

RS

RRL256

--------------=

RS

RRL1024

------------------=

8-Bit Device

10-Bit Device

RS

RRL4096

------------------= 12-Bit Device


MCP47CXBXX




1 VDD pin voltage














VRL

VDD

Buffer

Re

fere

nce

VREF1VREF0

Se

lect

ion

VREF

Band Gap


VDD

VRL

Band Gap(1)

(1214V typical)

VDD

VDD

VREF





MCP47CXBXX
























VD

D

DA

C G

ain Max DAC Code(1)










VWVOUT

PD1PD0

VDD

PD1PD0

1kΩ

100

kΩ

Gain(1x or 2x)


MCP47CXBXX



bull POR Event

bull BOR Event



532 OUTPUT VOLTAGE
















0 1


Where


1024 (MCP47CXB1X)

256 (MCP47CXB0X)

VOUT


Where


1024 (10-bit)

256 (8-bit)

VS

VRL


StepVoltage

VREF

50 27 18 15 10

VS

122 mV 659 uV 439 uV 366 uV 244 uV 12-bit

488 mV 264 mV 176 mV 146 mV 977 uV 10-bit

195 mV 105 mV 703 mV 586 mV 391 mV 8-bit



MCP47CXBXX




















Time

DACx = A

VO

UT

VOUT(A)

VOUT(B)

DACx = B


T--------------------------------------------------=


Gain

VOUT RISO

RL CL

VCL

VW


MCP47CXBXX

54 Latch Pin (LAT)













DAC Wiper x

16 Clocks

LATSYNC

Transfer

Serial Shift Reg


LAT SYNCTransfer

DataComment

1 1 0 No Transfer

1 0 0 No Transfer


0 0 0 No Transfer

Vol DAC Register x





MCP47CXBXX






Configuration bits
























PD1 PD0 Function




1 1 Open circuit















MCP47CXBXX


DeviceVolatile DAC

Register ValueVRL

(1)LSb Gain

Selection (2)

VOUT(3)


CP

47C

VB

2X (

12

-bit)

1111 1111 1111 50V 50V4096 12207 1x VRL (40954096) 1 4998779

25V 25V4096 6104 1x VRL (40954096) 1 2499390

2x(2) VRL (40954096) 2) 4998779

0111 1111 1111 50V 50V4096 12207 1x VRL (20474096) 1) 2498779

25V 25V4096 6104 1x VRL (20474096) 1) 1249390

2x(2) VRL (20474096) 2) 2498779

0011 1111 1111 50V 50V4096 12207 1x VRL (10234096) 1) 1248779

25V 25V4096 6104 1x VRL (10234096) 1) 0624390

2x(2) VRL (10234096) 2) 1248779

0000 0000 0000 50V 50V4096 12207 1x VRL (04096) 1) 0

25V 25V4096 6104 1x VRL (04096) 1) 0

2x(2) VRL (04096) 2) 0

MC

P47

CV

B1X

(1

0-b

it)

11 1111 1111 50V 50V1024 48828 1x VRL (10231024) 1 4995117

25V 25V1024 24414 1x VRL (10231024) 1 2497559

2x(2) VRL (10231024) 2 4995117

01 1111 1111 50V 50V1024 48828 1x VRL (5111024) 1 2495117

25V 25V1024 24414 1x VRL (5111024) 1 1247559

2x(2) VRL (5111024) 2 2495117

00 1111 1111 50V 50V1024 48828 1x VRL (2551024) 1 1245117

25V 25V1024 24414 1x VRL (2551024) 1 0622559

2x(2) VRL (2551024) 2 1245117

00 0000 0000 50V 50V1024 48828 1x VRL (01024) 1 0

25V 25V1024 24414 1x VRL (01024) 1 0

2x(2) VRL (01024) 1 0

MC

P4

7CV

B0X

(8

-bit)

1111 1111 50V 50V256 195313 1x VRL (255256) 1 4980469

25V 25V256 97656 1x VRL (255256) 1 2490234

2x(2) VRL (255256) 2 4980469

0111 1111 50V 50V256 195313 1x VRL (127256) 1 2480469

25V 25V256 97656 1x VRL (127256) 1 1240234

2x(2) VRL (127256) 2 2480469

0011 1111 50V 50V256 195313 1x VRL (63256) 1 1230469

25V 25V256 97656 1x VRL (63256) 1 0615234

2x(2) VRL (63256) 2 1230469

0000 0000 50V 50V256 195313 1x VRL (0256) 1 0

25V 25V256 97656 1x VRL (0256) 1 0

2x(2) VRL (0256) 2 0





MCP47CXBXX

NOTES


MCP47CXBXX






61 Overview





bull PORBOR




bull Slope Control










63 PORBOR













SCLSCL

MCP47CVBXX

SDASDA

HostController


Other Devices

(Master)(Slave)


MCP47CXBXX








68 Slope Control


69 Pulse Gobbler




Address Byte

RW ACK

Acknowledge Bit

Slave Address

A6 A5 A4 A3


A2 A1 A0













MCP47CXBXX














P


RW = ReadWrite bit

RW


FS Mode HS Mode

HS Mode Continues

FS Mode


Control Byte

Sr


MCP47CXBXX

NOTES


MCP47CXBXX

70 DEVICE COMMANDS





71 Write Commands



72 Read Commands




Command

of Bit Clocks(1)



CodeMode

C1 C0 100 kHz 400 kHz 34 MHz (3)





1 1 Last Address 29 3448 13793 117241








MCP47CXBXX











75 Write Command














MCP47CXBXX











Memory Address

I2C ACK bit(1)




SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

0 0 x A

ADn

D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA

A

P

S xSAn

0 0

I2C Start Bit

I2C Slave Address



I2C Stop Bit(3)




Legend


MCP47CXBXX








00h Yes Yes

01h No Yes

08h Yes Yes

09h Yes Yes

0Ah Yes Yes



S Slave Address

RW

AC

K

Command

AC

K

Data Byte

AC

K

Data Byte

AC

K

P

Master S

SA

6S

A5

SA

4S

A3

SA

2S

A1

SA

0

0 AA

AD

4A

D3

AD

2A

D1

AD

0C

1C

0 x AA

D15

D14

D13

D12

D11

D10

D09

D08 AA

D07

D06

D05

D04

D03

D02

D01

D00 AA P



MCP47CXBXX 0 0 0 0




MCP47CXBXX 0 1 1 1




MCP47CXBXX






D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


AD4

AD3

AD2

AD1

AD0

0 0 x A

Write Command

P

AD4

AD3

AD2

AD1

AD0

0 0 x A

Write Command

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0 AAD4

AD3

AD2

AD1

AD0

0 0 x A


Memory Address

I2C ACK Bit (1)

0

ADn

A

P

S x

SAn

0 0

I2C Start Bit

I2C Slave Address



I2C Stop Bit(3)


Legend


MCP47CXBXX

76 Read Command




bull Single Read





761 SINGLE READ
















MCP47CXBXX








Memory Address(5)

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

1 1 x A

ADn

A

A

PS

x

SAn

1 1

I2C Start Bit

I2C Slave Address

I2C Write Bit

Read Command


I2C Stop Bit(3)

Dnn



Legend

Sr

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

Control Byte

A I2C ACK Bit(2)

I2C NACK Bit(4)A

1 I2C Read Bit



MCP47CXBXX









I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

1 A

A

P

S

SAn

I2C Start Bit


Control Byte

Legend

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


A I2C ACK Bit(2)



MCP47CXBXX


Read 1 Word Command

S Slave Address

RW

AC

K Command

AC

K

Master SS

A6

SA

5S

A4

SA

3S

A2

SA

1S

A0 0 1

AD

4A

D3

AD

2A

D1

AD

0C

1C

0x

1

Sr

Slave Address RW

AC

K

Data Byte AC

K

Data Byte AC

K

P


SA

6S

A5

SA

4S

A3

SA

2S

A1

SA

0

1 1

D1

5D

14

D1

3D

12

D11

D1

0D

09

D0

8 1

D0

7D

06

D0

5D

04

D0

3D

02

D0

1D

00 1 P


Master S 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 x 1

MCP47CXBXX 0 0

I2C Bus S 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 x 0





Master S 1 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 x 1

MCP47CXBXX 0 1

I2C Bus S 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 x 1







MCP47CXBXX








Memory Address(5)

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

1 1 x A

ADn

A

A

PS

x

SAn

1 1

I2C Start Bit

I2C Slave Address

I2C Write Bit

Read Command


I2C Stop Bit(3)



Legend

Sr

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

Control Byte

A I2C ACK Bit(2)

I2C NACK Bit(4)A

1 I2C Read Bit


0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A



MCP47CXBXX












S 0 A 0 x x 0 A


0 00 0 0 0 0 x P000


Legend

x




MCP47CXBXX















S 0 A 0 1 1 0 A


0 00 0 0 0 0 0 P000


Legend

0




S 0 A 0 0 1 0 A


0 00 0 0 0 0 1 P000


Legend

1


MCP47CXBXX







bull Motor Control








3 Send Stop bit


1 2 3 4 5 6 7 8 9SCL


Address Byte

Address Bits

RW

StopBit

Device

AC

K

Response

A3A4A5A6


MCP47CXBXX





5

Analog

VDD

1

2

3

8

6

VDD SDA

SCL

VSS

VOUT0

7

R1 R2

To MCU


R1 and R2









C2C1

MCP47CVBX2

Optional




Output

VREF

4 5

LATHVC

VOUT1

C4C3

Analog

VDD

1

2

3

8

6

VDD SDA

SCL

VSS

VOUT0

7To MCU

C2C1

MCP47CVBX2

Optional

Output

VREF

4

LATHVC

VOUT1

C5

Optional

VREF

C6

R1 R2

C4C3


MCP47CXBXX






















R1

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

VOR2 C1

RSENSE

Comp

VDD

VTRIP

Vtrip VOUT

R2R1 R2+--------------------

=


2N


MCP47CXBXX











R1

VCC+

VCC-

VO

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

VOUTR2 C1

R3

VCC+

VCC-

RSENSE

CompVTRIP

R23

R2R3

R2 R3+-------------------=

V23

VCC+R2 VCC-R3 +

R2 R3+------------------------------------------------------=

VTRIP

VOUTR23 V23R1+

R1 R23+---------------------------------------------------=

TheveninEquivalent

R1

R23

V23

VOUT VTRIP


2N

R3

VCC+

VCC-

VO

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

R2

VOUT

VIN

R1

R4 C1

VOA+

VOA+ = VOUT bull R4

R3 + R4


2N


R1

R2

R1


MCP47CXBXX








EQUATION 8-4

EQUATION 8-5






41V1 mV = 4100




R2ndash

R1---------

205ndash4096V-----------------=


R2

R1------

12---=

R4

R3 R4+ ------------------------

205V 05 4096V +15 4096V

-------------------------------------------------------23---= =

If R4 = 20 k then R3 = 10 k

R3

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

R2

VO

VIN

R1

R4C1

R5

Optional

VOA+

VCC+

VCC-

C1 = 01 microF



2N


R3 + R4


R1

R2

R1


VCC+R4 VCC-R5+

R4 R5+---------------------------------------------=

VIN+

VOUTR45 V45R3+

R3 R45+---------------------------------------------=

R45

R4R5

R4 R5+-------------------=

VO VIN+ 1R2

R1------+

VA

R2

R1------ ndash=



MCP47CXBXX

















R1

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBX2

VDD

I2C2-Wire

VREF

Optional

MCP47CVBX2

VDD

R2

01 microF

VOUT0

VOUT1

(DAC0)

(DAC1)

VOUT =


VOUT0 R2 + VOUT1 R1

R1 + R2


Where

RSENSE

Ib

Load

IL

VCC+

VCC-

VOUT

IL

VOUT

Rsense---------------

1+-------------=

Ib

IL

----=


VDD

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

(or VREF)


MCP47CXBXX






















Start



VDD

VDD

VSS VSS

MC

P4

7CX

BX

X

01 microFP

ICreg

Mic

roc

on

tro

lle

r

01 microF

SCL

VOUT

VREF SDA


MCP47CXBXX



bull Noise


81021 Noise








Pin

s

Type Code


Length Width

10 MSOP UN 300 490 1470

10 DFN MF 300 300 900

16 QFN MG 300 300 900



MCP47CXBXX

















Title Literature





MCP47CXBXX


0

47k






VDD SDA

SCL

(DGND) Plane

NCVOUT1 LATHVC

VSS

10 microF 47k

VOUT0

VREF

47Cx

Bxx

0

A1

A0


MCP47CXBXX






3e

3e

Part Number Code

MCP47CVB01-EMF BAJU

MCP47CVB11-EMF BAJX

MCP47CVB21-EMF BAJZ

MCP47CVB02-EMF BAJV

MCP47CVB12-EMF BAJY

MCP47CVB22-EMF BAKA

MCP47CMB01-EMF BAJV

MCP47CMB11-EMF BAJQ

MCP47CMB21-EMF BAJS

MCP47CMB02-EMF BAJP

MCP47CMB12-EMF BAJR

MCP47CMB22-EMF BAJT

XXXXXX

10-Lead MSOP

YWWNNN47CV01

Example

935256

XXXX


PIN 1

YYWWNNN

BAJU

Example

PIN 1

1935256


MCP47CXBXX

Part Number Code

MCP47CVB02-EMG AAD

MCP47CVB12-EMG AAE

MCP47CVB22-EMG AAF

MCP47CMB02-EMG AAA

MCP47CMB12-EMG AAB

MCP47CMB22-EMG AAC

XXX


PIN 1

XYYWWNNN


AAD

Example

PIN 1

1935256


MCP47CXBXX


UN


MCP47CXBXX


UN


MCP47CXBXX




MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX

NOTES


MCP47CXBXX

















MCP47CXBXX

NOTES


MCP47CXBXX




B1 Overview













SCL SCL

Slave

SDA SDA

Master


Other Devices



MCP47CXBXX










B3 I2C Operation





B311 Start Bit



B312 Data Bit


FIGURE B-3 Data Bit






SDA

SCL

S

1st Bit 2nd Bit



Comment

General Call A

Slave Address Valid

A


A


SDA

SCL

Data Bit

1st Bit 2nd Bit

A

8

D0

9

SDA

SCL


MCP47CXBXX





B315 Stop Bit













SDA

SCL

Sr = Repeated Start

1st Bit

SCL

SDA AA

P

1st Bit

SDA

SCL


SCL

SDA

StartCondition

StopCondition


Data orA Valid


MCP47CXBXX

B34 SLOPE CONTROL







B36 HS MODE











B361 Slope Control


B362 Pulse Gobbler




Address Byte

RW ACK

Acknowledge Bit

7-Bit Slave Address

A6 A5 A4 A3 A2 A1 A0


P

S = Start bit


A = Acknowledge bit


RW = ReadWrite bit

RW


FS Mode HS Mode

HS Mode Continues

FS Mode


Control Byte


MCP47CXBXX

B37 GENERAL CALL







00 0 0S 0 0 0 0 xx x x xA x x 0 A P


Second Byte

7-Bit Command



00 0 0S 0 0 0 0 xx x x xA x x 1 A


Second Byte

Master Address

xx x x x x x x A P




MCP47CXBXX

NOTES


MCP47CXBXX


C1 Resolution










Ideal

Measured 1

Measured 2

VLSb IDEAL VDD

2N

----------- or VREF

2N

-------------=


4032 64ndash ---------------------------------------------------------------=

VLSb


2N

1ndash-----------------------------------------------------------=

40h

3Fh

3Eh

03h

02h

01h

00h

Wip

er

Cod


VW ( Tap)

VS0

VS1

VS3

VS63

VS64


n =


MCP47CXBXX


















EFS


VLSb IDEAL ----------------------------------------------------------------=




EZS

VOUT(ZS)

VLSb(IDEAL)----------------------------=

Where





ET


--------------------------------------------------------------------------------------------------=


MCP47CXBXX







C9 Gain Error (EG)







Ideal Transfer

Actual

DAC Input Code0


Offset

Function

64 4032

VO

UT

Error (EOS)

TransferFunction

VO

UT

Ideal Transfer

Actual

DAC Input Code0


Gain Error (EG)

Function

64 4032 4095

VREF

TransferFunction

( code = 4032)


Where






EG


---------------------------------------------------------------------------------------------------- 100=


MCP47CXBXX











Where






EINL


--------------------------------------------------=

010001000

AnalogOutput(LSb)


1

2

3

4

5

6

0

7

110



INL = lt -1 LSb

INL = 05 LSb

INL = -1 LSb

Where




EDNL


------------------------------------------------------------------------------------ 1ndash=

010001000

AnalogOutput(LSb)

DAC Input Code

011 111100 101

1

2

3

4

5

6

0

7

DNL = 2 LSb

DNL = 05 LSb

110




MCP47CXBXX

C13 Settling Time







C16 -3 dB Bandwidth













Where

PSS is expressed in




55V 27Vndash 55V ----------------------------------------------------------------------------------------------------------=


MCP47CXBXX

NOTES


MCP47CXBXX





Temperature Range





Examples







PART NO X

TemperatureRange

Device

XX

Package

X(1)

Tape andReel


-


MCP47CXBXX

NOTES

















ISBN 978-1-5224-4636-1

DS20006089B-page 123































China - XianTel 86-29-8833-7252





India - PuneTel 91-20-4121-0141




































051419

Features

General Description

Applications






DC Characteristics









DC Notes

















Timing Notes



21 Electrical Data










22 Linearity Data















































































30 Pin Descriptions




32 Ground (VSS)







39 No Connect (NC)



411 Power-on Reset


412 Brown-out Reset

42 Device Memory














50 DAC Circuitry


51 Resistor Ladder















532 Output Voltage









54 Latch Pin (LAT)










61 Overview



63 PORBOR








68 Slope Control

69 Pulse Gobbler



70 Device Commands

71 Write Commands

72 Read Commands




75 Write Command










76 Read Command

761 Single Read






























EQUATION 8-4

EQUATION 8-5






























B1 Overview




B3 I2C Operation



FIGURE B-3 Data Bit









B34 Slope Control



B36 HS Mode


B37 General Call



C1 Resolution














C9 Gain Error (EG)










C13 Settling Time



C16 -3 dB Bandwidth









MCP47CXBXX











mdash 0016 0300 18V VDD 55V(2)










MCP47CXBXX





































MCP47CXBXX































MCP47CXBXX













Internal Band Gap












MCP47CXBXX










spec (at 55V)



Dynamic Performance








MCP47CXBXX






















RAM Value


mdash 3FFh 10-bit

mdash FFFh 12-bit



10-bit

12-bit



Power Requirements



mdash 10-bit

mdash 12-bit


MCP47CXBXX























MCP47CXBXX

DC Notes














MCP47CXBXX






VOUT

plusmn 05 LSb

Old Value

New Value









LATx

SCL

tLAT

Wx








MCP47CXBXX




VDD

tBORD

VOUT

VBOR

VOUT at High-Z


VPOR

tPOR2SIA = tPOR2OD

SDA

SCL

ACK Stop Start ACK

VOUT

tPDD tPDE














MCP47CXBXX


SCL

SDA

StartCondition

StopCondition

VIH

111

VIL

VIH VIHH

VIHHVC94


9091 93

92


MCP47CXBXX



Param No






























MCP47CXBXX




Param No











400 kHz mode 20 + 01Cb(4) 300 ns






400 kHz mode 20 + 01Cb 300 ns




400 kHz mode 20 + 01Cb 300 ns






9091 92

100101

103

106107

109 109 110

102

SCL

SDA In

SDA Out


MCP47CXBXX



Param No



400 kHz mode 20 + 01Cb 300 ns




































MCP47CXBXX

Timing Notes












MCP47CXBXX




Temperature Ranges









MCP47CXBXX

NOTES


MCP47CXBXX











MCP47CXBXX






MCP47CXBXX

22 Linearity Data










MCP47CXBXX










MCP47CXBXX










MCP47CXBXX








MCP47CXBXX








MCP47CXBXX








MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX

NOTES


MCP47CXBXX

30 PIN DESCRIPTIONS




Pin


DescriptionMSOP10L

DFN10L

QFN16L





5 5 456781415












MCP47CXBXX


Pin


DescriptionMSOP10L

DFN10L

QFN16L








mdash mdash 671415
















MCP47CXBXX




32 Ground (VSS)






















MCP47CXBXX







39 No Connect (NC)



MCP47CXBXX













bull Device Memory










411 POWER-ON RESET





MCP47CXBXX











VPOR

TPORD2OD

VDD(MIN)


VRAM


VBOR


VDD(MIN)

TPOR2OD

VBOR VPOR

VRAM

Case 1 VDD Ramp

Case 2 VDD Step

















POR Event


MCP47CXBXX

412 BROWN-OUT RESET












42 Device Memory


















MCP47CXBXX


dd

res

s

Function

Sin

gle

Du

al

Ad

dre

ss

Function

Sin

gle

(1)

Du

al(1

)

















Legend






MCP47CXBXX























MCP47CXBXX


dd

ress

Function

PORBOR Value

Ad

dre

ss

Function

PORBOR Value

8-B

it

10-B

it

12-B

it

8-B

it

10-B

it

12-B

it


7Fh 1FFh 7FFh


7Fh 1FFh 7FFh










0000h 0000h 0000h



0060h 0060h 0060h


0000h 0000h 0000h





Legend



Not Implemented




MCP47CXBXX

12-b

10-b

8-b








bit 15 bit 0

Legend



12-bit 10-bit 8-bit









MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual




powered down(2)





MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual







MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual




0 = 1x gain



0 = 1x gain














MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual









MCP47CXBXX

Singl

Dua







bit 15 bit 0

Legend



Single Dual







MCP47CXBXX

50 DAC CIRCUITRY










RS(2)

VREF

DACOutput

RS(1)

RS(2n ndash 1)

RS(2n ndash 2)

RS(2n ndash 3)

RS(2n)

VDD

VRL

VOUT

PD1PD0

VDD

PD1PD0

VDD

VW



Selection


ResistorLadder


Power-DownOperation

Power-DownOperation

Power-DownOperation

A (RL)

B

VREF1VREF0

Where


1024 (MCP47CXB1X)

4096 (MCP47CXB2X)



VDD

(~71 k)RRL

1kΩ

100

kΩ

Gain(1x or 2x)



MCP47CXBXX

51 Resistor Ladder












VW

Analog MUX


RS(2)

DACRegister

RS(1)

RS(2n ndash 1)

RS(2n ndash 2)

RS(2n ndash 3)

RS(2n)

VRL

RRL

RW(1)

RW(1)

RW(1)

RW(1)

RW(1)

RW(1)

2n ndash 1

2n ndash 2

1

0

2

2n ndash 3

RS

RRL256

--------------=

RS

RRL1024

------------------=

8-Bit Device

10-Bit Device

RS

RRL4096

------------------= 12-Bit Device


MCP47CXBXX




1 VDD pin voltage














VRL

VDD

Buffer

Re

fere

nce

VREF1VREF0

Se

lect

ion

VREF

Band Gap


VDD

VRL

Band Gap(1)

(1214V typical)

VDD

VDD

VREF





MCP47CXBXX
























VD

D

DA

C G

ain Max DAC Code(1)










VWVOUT

PD1PD0

VDD

PD1PD0

1kΩ

100

kΩ

Gain(1x or 2x)


MCP47CXBXX



bull POR Event

bull BOR Event



532 OUTPUT VOLTAGE
















0 1


Where


1024 (MCP47CXB1X)

256 (MCP47CXB0X)

VOUT


Where


1024 (10-bit)

256 (8-bit)

VS

VRL


StepVoltage

VREF

50 27 18 15 10

VS

122 mV 659 uV 439 uV 366 uV 244 uV 12-bit

488 mV 264 mV 176 mV 146 mV 977 uV 10-bit

195 mV 105 mV 703 mV 586 mV 391 mV 8-bit



MCP47CXBXX




















Time

DACx = A

VO

UT

VOUT(A)

VOUT(B)

DACx = B


T--------------------------------------------------=


Gain

VOUT RISO

RL CL

VCL

VW


MCP47CXBXX

54 Latch Pin (LAT)













DAC Wiper x

16 Clocks

LATSYNC

Transfer

Serial Shift Reg


LAT SYNCTransfer

DataComment

1 1 0 No Transfer

1 0 0 No Transfer


0 0 0 No Transfer

Vol DAC Register x





MCP47CXBXX






Configuration bits
























PD1 PD0 Function




1 1 Open circuit















MCP47CXBXX


DeviceVolatile DAC

Register ValueVRL

(1)LSb Gain

Selection (2)

VOUT(3)


CP

47C

VB

2X (

12

-bit)

1111 1111 1111 50V 50V4096 12207 1x VRL (40954096) 1 4998779

25V 25V4096 6104 1x VRL (40954096) 1 2499390

2x(2) VRL (40954096) 2) 4998779

0111 1111 1111 50V 50V4096 12207 1x VRL (20474096) 1) 2498779

25V 25V4096 6104 1x VRL (20474096) 1) 1249390

2x(2) VRL (20474096) 2) 2498779

0011 1111 1111 50V 50V4096 12207 1x VRL (10234096) 1) 1248779

25V 25V4096 6104 1x VRL (10234096) 1) 0624390

2x(2) VRL (10234096) 2) 1248779

0000 0000 0000 50V 50V4096 12207 1x VRL (04096) 1) 0

25V 25V4096 6104 1x VRL (04096) 1) 0

2x(2) VRL (04096) 2) 0

MC

P47

CV

B1X

(1

0-b

it)

11 1111 1111 50V 50V1024 48828 1x VRL (10231024) 1 4995117

25V 25V1024 24414 1x VRL (10231024) 1 2497559

2x(2) VRL (10231024) 2 4995117

01 1111 1111 50V 50V1024 48828 1x VRL (5111024) 1 2495117

25V 25V1024 24414 1x VRL (5111024) 1 1247559

2x(2) VRL (5111024) 2 2495117

00 1111 1111 50V 50V1024 48828 1x VRL (2551024) 1 1245117

25V 25V1024 24414 1x VRL (2551024) 1 0622559

2x(2) VRL (2551024) 2 1245117

00 0000 0000 50V 50V1024 48828 1x VRL (01024) 1 0

25V 25V1024 24414 1x VRL (01024) 1 0

2x(2) VRL (01024) 1 0

MC

P4

7CV

B0X

(8

-bit)

1111 1111 50V 50V256 195313 1x VRL (255256) 1 4980469

25V 25V256 97656 1x VRL (255256) 1 2490234

2x(2) VRL (255256) 2 4980469

0111 1111 50V 50V256 195313 1x VRL (127256) 1 2480469

25V 25V256 97656 1x VRL (127256) 1 1240234

2x(2) VRL (127256) 2 2480469

0011 1111 50V 50V256 195313 1x VRL (63256) 1 1230469

25V 25V256 97656 1x VRL (63256) 1 0615234

2x(2) VRL (63256) 2 1230469

0000 0000 50V 50V256 195313 1x VRL (0256) 1 0

25V 25V256 97656 1x VRL (0256) 1 0

2x(2) VRL (0256) 2 0





MCP47CXBXX

NOTES


MCP47CXBXX






61 Overview





bull PORBOR




bull Slope Control










63 PORBOR













SCLSCL

MCP47CVBXX

SDASDA

HostController


Other Devices

(Master)(Slave)


MCP47CXBXX








68 Slope Control


69 Pulse Gobbler




Address Byte

RW ACK

Acknowledge Bit

Slave Address

A6 A5 A4 A3


A2 A1 A0













MCP47CXBXX














P


RW = ReadWrite bit

RW


FS Mode HS Mode

HS Mode Continues

FS Mode


Control Byte

Sr


MCP47CXBXX

NOTES


MCP47CXBXX

70 DEVICE COMMANDS





71 Write Commands



72 Read Commands




Command

of Bit Clocks(1)



CodeMode

C1 C0 100 kHz 400 kHz 34 MHz (3)





1 1 Last Address 29 3448 13793 117241








MCP47CXBXX











75 Write Command














MCP47CXBXX











Memory Address

I2C ACK bit(1)




SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

0 0 x A

ADn

D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA

A

P

S xSAn

0 0

I2C Start Bit

I2C Slave Address



I2C Stop Bit(3)




Legend


MCP47CXBXX








00h Yes Yes

01h No Yes

08h Yes Yes

09h Yes Yes

0Ah Yes Yes



S Slave Address

RW

AC

K

Command

AC

K

Data Byte

AC

K

Data Byte

AC

K

P

Master S

SA

6S

A5

SA

4S

A3

SA

2S

A1

SA

0

0 AA

AD

4A

D3

AD

2A

D1

AD

0C

1C

0 x AA

D15

D14

D13

D12

D11

D10

D09

D08 AA

D07

D06

D05

D04

D03

D02

D01

D00 AA P



MCP47CXBXX 0 0 0 0




MCP47CXBXX 0 1 1 1




MCP47CXBXX






D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


AD4

AD3

AD2

AD1

AD0

0 0 x A

Write Command

P

AD4

AD3

AD2

AD1

AD0

0 0 x A

Write Command

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0 AAD4

AD3

AD2

AD1

AD0

0 0 x A


Memory Address

I2C ACK Bit (1)

0

ADn

A

P

S x

SAn

0 0

I2C Start Bit

I2C Slave Address



I2C Stop Bit(3)


Legend


MCP47CXBXX

76 Read Command




bull Single Read





761 SINGLE READ
















MCP47CXBXX








Memory Address(5)

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

1 1 x A

ADn

A

A

PS

x

SAn

1 1

I2C Start Bit

I2C Slave Address

I2C Write Bit

Read Command


I2C Stop Bit(3)

Dnn



Legend

Sr

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

Control Byte

A I2C ACK Bit(2)

I2C NACK Bit(4)A

1 I2C Read Bit



MCP47CXBXX









I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

1 A

A

P

S

SAn

I2C Start Bit


Control Byte

Legend

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


A I2C ACK Bit(2)



MCP47CXBXX


Read 1 Word Command

S Slave Address

RW

AC

K Command

AC

K

Master SS

A6

SA

5S

A4

SA

3S

A2

SA

1S

A0 0 1

AD

4A

D3

AD

2A

D1

AD

0C

1C

0x

1

Sr

Slave Address RW

AC

K

Data Byte AC

K

Data Byte AC

K

P


SA

6S

A5

SA

4S

A3

SA

2S

A1

SA

0

1 1

D1

5D

14

D1

3D

12

D11

D1

0D

09

D0

8 1

D0

7D

06

D0

5D

04

D0

3D

02

D0

1D

00 1 P


Master S 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 x 1

MCP47CXBXX 0 0

I2C Bus S 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 x 0





Master S 1 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 x 1

MCP47CXBXX 0 1

I2C Bus S 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 x 1







MCP47CXBXX








Memory Address(5)

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

1 1 x A

ADn

A

A

PS

x

SAn

1 1

I2C Start Bit

I2C Slave Address

I2C Write Bit

Read Command


I2C Stop Bit(3)



Legend

Sr

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

Control Byte

A I2C ACK Bit(2)

I2C NACK Bit(4)A

1 I2C Read Bit


0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A



MCP47CXBXX












S 0 A 0 x x 0 A


0 00 0 0 0 0 x P000


Legend

x




MCP47CXBXX















S 0 A 0 1 1 0 A


0 00 0 0 0 0 0 P000


Legend

0




S 0 A 0 0 1 0 A


0 00 0 0 0 0 1 P000


Legend

1


MCP47CXBXX







bull Motor Control








3 Send Stop bit


1 2 3 4 5 6 7 8 9SCL


Address Byte

Address Bits

RW

StopBit

Device

AC

K

Response

A3A4A5A6


MCP47CXBXX





5

Analog

VDD

1

2

3

8

6

VDD SDA

SCL

VSS

VOUT0

7

R1 R2

To MCU


R1 and R2









C2C1

MCP47CVBX2

Optional




Output

VREF

4 5

LATHVC

VOUT1

C4C3

Analog

VDD

1

2

3

8

6

VDD SDA

SCL

VSS

VOUT0

7To MCU

C2C1

MCP47CVBX2

Optional

Output

VREF

4

LATHVC

VOUT1

C5

Optional

VREF

C6

R1 R2

C4C3


MCP47CXBXX






















R1

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

VOR2 C1

RSENSE

Comp

VDD

VTRIP

Vtrip VOUT

R2R1 R2+--------------------

=


2N


MCP47CXBXX











R1

VCC+

VCC-

VO

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

VOUTR2 C1

R3

VCC+

VCC-

RSENSE

CompVTRIP

R23

R2R3

R2 R3+-------------------=

V23

VCC+R2 VCC-R3 +

R2 R3+------------------------------------------------------=

VTRIP

VOUTR23 V23R1+

R1 R23+---------------------------------------------------=

TheveninEquivalent

R1

R23

V23

VOUT VTRIP


2N

R3

VCC+

VCC-

VO

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

R2

VOUT

VIN

R1

R4 C1

VOA+

VOA+ = VOUT bull R4

R3 + R4


2N


R1

R2

R1


MCP47CXBXX








EQUATION 8-4

EQUATION 8-5






41V1 mV = 4100




R2ndash

R1---------

205ndash4096V-----------------=


R2

R1------

12---=

R4

R3 R4+ ------------------------

205V 05 4096V +15 4096V

-------------------------------------------------------23---= =

If R4 = 20 k then R3 = 10 k

R3

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

R2

VO

VIN

R1

R4C1

R5

Optional

VOA+

VCC+

VCC-

C1 = 01 microF



2N


R3 + R4


R1

R2

R1


VCC+R4 VCC-R5+

R4 R5+---------------------------------------------=

VIN+

VOUTR45 V45R3+

R3 R45+---------------------------------------------=

R45

R4R5

R4 R5+-------------------=

VO VIN+ 1R2

R1------+

VA

R2

R1------ ndash=



MCP47CXBXX

















R1

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBX2

VDD

I2C2-Wire

VREF

Optional

MCP47CVBX2

VDD

R2

01 microF

VOUT0

VOUT1

(DAC0)

(DAC1)

VOUT =


VOUT0 R2 + VOUT1 R1

R1 + R2


Where

RSENSE

Ib

Load

IL

VCC+

VCC-

VOUT

IL

VOUT

Rsense---------------

1+-------------=

Ib

IL

----=


VDD

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

(or VREF)


MCP47CXBXX






















Start



VDD

VDD

VSS VSS

MC

P4

7CX

BX

X

01 microFP

ICreg

Mic

roc

on

tro

lle

r

01 microF

SCL

VOUT

VREF SDA


MCP47CXBXX



bull Noise


81021 Noise








Pin

s

Type Code


Length Width

10 MSOP UN 300 490 1470

10 DFN MF 300 300 900

16 QFN MG 300 300 900



MCP47CXBXX

















Title Literature





MCP47CXBXX


0

47k






VDD SDA

SCL

(DGND) Plane

NCVOUT1 LATHVC

VSS

10 microF 47k

VOUT0

VREF

47Cx

Bxx

0

A1

A0


MCP47CXBXX






3e

3e

Part Number Code

MCP47CVB01-EMF BAJU

MCP47CVB11-EMF BAJX

MCP47CVB21-EMF BAJZ

MCP47CVB02-EMF BAJV

MCP47CVB12-EMF BAJY

MCP47CVB22-EMF BAKA

MCP47CMB01-EMF BAJV

MCP47CMB11-EMF BAJQ

MCP47CMB21-EMF BAJS

MCP47CMB02-EMF BAJP

MCP47CMB12-EMF BAJR

MCP47CMB22-EMF BAJT

XXXXXX

10-Lead MSOP

YWWNNN47CV01

Example

935256

XXXX


PIN 1

YYWWNNN

BAJU

Example

PIN 1

1935256


MCP47CXBXX

Part Number Code

MCP47CVB02-EMG AAD

MCP47CVB12-EMG AAE

MCP47CVB22-EMG AAF

MCP47CMB02-EMG AAA

MCP47CMB12-EMG AAB

MCP47CMB22-EMG AAC

XXX


PIN 1

XYYWWNNN


AAD

Example

PIN 1

1935256


MCP47CXBXX


UN


MCP47CXBXX


UN


MCP47CXBXX




MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX

NOTES


MCP47CXBXX

















MCP47CXBXX

NOTES


MCP47CXBXX




B1 Overview













SCL SCL

Slave

SDA SDA

Master


Other Devices



MCP47CXBXX










B3 I2C Operation





B311 Start Bit



B312 Data Bit


FIGURE B-3 Data Bit






SDA

SCL

S

1st Bit 2nd Bit



Comment

General Call A

Slave Address Valid

A


A


SDA

SCL

Data Bit

1st Bit 2nd Bit

A

8

D0

9

SDA

SCL


MCP47CXBXX





B315 Stop Bit













SDA

SCL

Sr = Repeated Start

1st Bit

SCL

SDA AA

P

1st Bit

SDA

SCL


SCL

SDA

StartCondition

StopCondition


Data orA Valid


MCP47CXBXX

B34 SLOPE CONTROL







B36 HS MODE











B361 Slope Control


B362 Pulse Gobbler




Address Byte

RW ACK

Acknowledge Bit

7-Bit Slave Address

A6 A5 A4 A3 A2 A1 A0


P

S = Start bit


A = Acknowledge bit


RW = ReadWrite bit

RW


FS Mode HS Mode

HS Mode Continues

FS Mode


Control Byte


MCP47CXBXX

B37 GENERAL CALL







00 0 0S 0 0 0 0 xx x x xA x x 0 A P


Second Byte

7-Bit Command



00 0 0S 0 0 0 0 xx x x xA x x 1 A


Second Byte

Master Address

xx x x x x x x A P




MCP47CXBXX

NOTES


MCP47CXBXX


C1 Resolution










Ideal

Measured 1

Measured 2

VLSb IDEAL VDD

2N

----------- or VREF

2N

-------------=


4032 64ndash ---------------------------------------------------------------=

VLSb


2N

1ndash-----------------------------------------------------------=

40h

3Fh

3Eh

03h

02h

01h

00h

Wip

er

Cod


VW ( Tap)

VS0

VS1

VS3

VS63

VS64


n =


MCP47CXBXX


















EFS


VLSb IDEAL ----------------------------------------------------------------=




EZS

VOUT(ZS)

VLSb(IDEAL)----------------------------=

Where





ET


--------------------------------------------------------------------------------------------------=


MCP47CXBXX







C9 Gain Error (EG)







Ideal Transfer

Actual

DAC Input Code0


Offset

Function

64 4032

VO

UT

Error (EOS)

TransferFunction

VO

UT

Ideal Transfer

Actual

DAC Input Code0


Gain Error (EG)

Function

64 4032 4095

VREF

TransferFunction

( code = 4032)


Where






EG


---------------------------------------------------------------------------------------------------- 100=


MCP47CXBXX











Where






EINL


--------------------------------------------------=

010001000

AnalogOutput(LSb)


1

2

3

4

5

6

0

7

110



INL = lt -1 LSb

INL = 05 LSb

INL = -1 LSb

Where




EDNL


------------------------------------------------------------------------------------ 1ndash=

010001000

AnalogOutput(LSb)

DAC Input Code

011 111100 101

1

2

3

4

5

6

0

7

DNL = 2 LSb

DNL = 05 LSb

110




MCP47CXBXX

C13 Settling Time







C16 -3 dB Bandwidth













Where

PSS is expressed in




55V 27Vndash 55V ----------------------------------------------------------------------------------------------------------=


MCP47CXBXX

NOTES


MCP47CXBXX





Temperature Range





Examples







PART NO X

TemperatureRange

Device

XX

Package

X(1)

Tape andReel


-


MCP47CXBXX

NOTES

















ISBN 978-1-5224-4636-1

DS20006089B-page 123































China - XianTel 86-29-8833-7252





India - PuneTel 91-20-4121-0141




































051419

Features

General Description

Applications






DC Characteristics









DC Notes

















Timing Notes



21 Electrical Data










22 Linearity Data















































































30 Pin Descriptions




32 Ground (VSS)







39 No Connect (NC)



411 Power-on Reset


412 Brown-out Reset

42 Device Memory














50 DAC Circuitry


51 Resistor Ladder















532 Output Voltage









54 Latch Pin (LAT)










61 Overview



63 PORBOR








68 Slope Control

69 Pulse Gobbler



70 Device Commands

71 Write Commands

72 Read Commands




75 Write Command










76 Read Command

761 Single Read






























EQUATION 8-4

EQUATION 8-5






























B1 Overview




B3 I2C Operation



FIGURE B-3 Data Bit









B34 Slope Control



B36 HS Mode


B37 General Call



C1 Resolution














C9 Gain Error (EG)










C13 Settling Time



C16 -3 dB Bandwidth









MCP47CXBXX





































MCP47CXBXX































MCP47CXBXX













Internal Band Gap












MCP47CXBXX










spec (at 55V)



Dynamic Performance








MCP47CXBXX






















RAM Value


mdash 3FFh 10-bit

mdash FFFh 12-bit



10-bit

12-bit



Power Requirements



mdash 10-bit

mdash 12-bit


MCP47CXBXX























MCP47CXBXX

DC Notes














MCP47CXBXX






VOUT

plusmn 05 LSb

Old Value

New Value









LATx

SCL

tLAT

Wx








MCP47CXBXX




VDD

tBORD

VOUT

VBOR

VOUT at High-Z


VPOR

tPOR2SIA = tPOR2OD

SDA

SCL

ACK Stop Start ACK

VOUT

tPDD tPDE














MCP47CXBXX


SCL

SDA

StartCondition

StopCondition

VIH

111

VIL

VIH VIHH

VIHHVC94


9091 93

92


MCP47CXBXX



Param No






























MCP47CXBXX




Param No











400 kHz mode 20 + 01Cb(4) 300 ns






400 kHz mode 20 + 01Cb 300 ns




400 kHz mode 20 + 01Cb 300 ns






9091 92

100101

103

106107

109 109 110

102

SCL

SDA In

SDA Out


MCP47CXBXX



Param No



400 kHz mode 20 + 01Cb 300 ns




































MCP47CXBXX

Timing Notes












MCP47CXBXX




Temperature Ranges









MCP47CXBXX

NOTES


MCP47CXBXX











MCP47CXBXX






MCP47CXBXX

22 Linearity Data










MCP47CXBXX










MCP47CXBXX










MCP47CXBXX








MCP47CXBXX








MCP47CXBXX








MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX










MCP47CXBXX









MCP47CXBXX




MCP47CXBXX

NOTES


MCP47CXBXX

30 PIN DESCRIPTIONS




Pin


DescriptionMSOP10L

DFN10L

QFN16L





5 5 456781415












MCP47CXBXX


Pin


DescriptionMSOP10L

DFN10L

QFN16L








mdash mdash 671415
















MCP47CXBXX




32 Ground (VSS)






















MCP47CXBXX







39 No Connect (NC)



MCP47CXBXX













bull Device Memory










411 POWER-ON RESET





MCP47CXBXX











VPOR

TPORD2OD

VDD(MIN)


VRAM


VBOR


VDD(MIN)

TPOR2OD

VBOR VPOR

VRAM

Case 1 VDD Ramp

Case 2 VDD Step

















POR Event


MCP47CXBXX

412 BROWN-OUT RESET












42 Device Memory


















MCP47CXBXX


dd

res

s

Function

Sin

gle

Du

al

Ad

dre

ss

Function

Sin

gle

(1)

Du

al(1

)

















Legend






MCP47CXBXX























MCP47CXBXX


dd

ress

Function

PORBOR Value

Ad

dre

ss

Function

PORBOR Value

8-B

it

10-B

it

12-B

it

8-B

it

10-B

it

12-B

it


7Fh 1FFh 7FFh


7Fh 1FFh 7FFh










0000h 0000h 0000h



0060h 0060h 0060h


0000h 0000h 0000h





Legend



Not Implemented




MCP47CXBXX

12-b

10-b

8-b








bit 15 bit 0

Legend



12-bit 10-bit 8-bit









MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual




powered down(2)





MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual







MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual




0 = 1x gain



0 = 1x gain














MCP47CXBXX

Sing

Du






bit 15 bit 0

Legend



Single Dual









MCP47CXBXX

Singl

Dua







bit 15 bit 0

Legend



Single Dual







MCP47CXBXX

50 DAC CIRCUITRY










RS(2)

VREF

DACOutput

RS(1)

RS(2n ndash 1)

RS(2n ndash 2)

RS(2n ndash 3)

RS(2n)

VDD

VRL

VOUT

PD1PD0

VDD

PD1PD0

VDD

VW



Selection


ResistorLadder


Power-DownOperation

Power-DownOperation

Power-DownOperation

A (RL)

B

VREF1VREF0

Where


1024 (MCP47CXB1X)

4096 (MCP47CXB2X)



VDD

(~71 k)RRL

1kΩ

100

kΩ

Gain(1x or 2x)



MCP47CXBXX

51 Resistor Ladder












VW

Analog MUX


RS(2)

DACRegister

RS(1)

RS(2n ndash 1)

RS(2n ndash 2)

RS(2n ndash 3)

RS(2n)

VRL

RRL

RW(1)

RW(1)

RW(1)

RW(1)

RW(1)

RW(1)

2n ndash 1

2n ndash 2

1

0

2

2n ndash 3

RS

RRL256

--------------=

RS

RRL1024

------------------=

8-Bit Device

10-Bit Device

RS

RRL4096

------------------= 12-Bit Device


MCP47CXBXX




1 VDD pin voltage














VRL

VDD

Buffer

Re

fere

nce

VREF1VREF0

Se

lect

ion

VREF

Band Gap


VDD

VRL

Band Gap(1)

(1214V typical)

VDD

VDD

VREF





MCP47CXBXX
























VD

D

DA

C G

ain Max DAC Code(1)










VWVOUT

PD1PD0

VDD

PD1PD0

1kΩ

100

kΩ

Gain(1x or 2x)


MCP47CXBXX



bull POR Event

bull BOR Event



532 OUTPUT VOLTAGE
















0 1


Where


1024 (MCP47CXB1X)

256 (MCP47CXB0X)

VOUT


Where


1024 (10-bit)

256 (8-bit)

VS

VRL


StepVoltage

VREF

50 27 18 15 10

VS

122 mV 659 uV 439 uV 366 uV 244 uV 12-bit

488 mV 264 mV 176 mV 146 mV 977 uV 10-bit

195 mV 105 mV 703 mV 586 mV 391 mV 8-bit



MCP47CXBXX




















Time

DACx = A

VO

UT

VOUT(A)

VOUT(B)

DACx = B


T--------------------------------------------------=


Gain

VOUT RISO

RL CL

VCL

VW


MCP47CXBXX

54 Latch Pin (LAT)













DAC Wiper x

16 Clocks

LATSYNC

Transfer

Serial Shift Reg


LAT SYNCTransfer

DataComment

1 1 0 No Transfer

1 0 0 No Transfer


0 0 0 No Transfer

Vol DAC Register x





MCP47CXBXX






Configuration bits
























PD1 PD0 Function




1 1 Open circuit















MCP47CXBXX


DeviceVolatile DAC

Register ValueVRL

(1)LSb Gain

Selection (2)

VOUT(3)


CP

47C

VB

2X (

12

-bit)

1111 1111 1111 50V 50V4096 12207 1x VRL (40954096) 1 4998779

25V 25V4096 6104 1x VRL (40954096) 1 2499390

2x(2) VRL (40954096) 2) 4998779

0111 1111 1111 50V 50V4096 12207 1x VRL (20474096) 1) 2498779

25V 25V4096 6104 1x VRL (20474096) 1) 1249390

2x(2) VRL (20474096) 2) 2498779

0011 1111 1111 50V 50V4096 12207 1x VRL (10234096) 1) 1248779

25V 25V4096 6104 1x VRL (10234096) 1) 0624390

2x(2) VRL (10234096) 2) 1248779

0000 0000 0000 50V 50V4096 12207 1x VRL (04096) 1) 0

25V 25V4096 6104 1x VRL (04096) 1) 0

2x(2) VRL (04096) 2) 0

MC

P47

CV

B1X

(1

0-b

it)

11 1111 1111 50V 50V1024 48828 1x VRL (10231024) 1 4995117

25V 25V1024 24414 1x VRL (10231024) 1 2497559

2x(2) VRL (10231024) 2 4995117

01 1111 1111 50V 50V1024 48828 1x VRL (5111024) 1 2495117

25V 25V1024 24414 1x VRL (5111024) 1 1247559

2x(2) VRL (5111024) 2 2495117

00 1111 1111 50V 50V1024 48828 1x VRL (2551024) 1 1245117

25V 25V1024 24414 1x VRL (2551024) 1 0622559

2x(2) VRL (2551024) 2 1245117

00 0000 0000 50V 50V1024 48828 1x VRL (01024) 1 0

25V 25V1024 24414 1x VRL (01024) 1 0

2x(2) VRL (01024) 1 0

MC

P4

7CV

B0X

(8

-bit)

1111 1111 50V 50V256 195313 1x VRL (255256) 1 4980469

25V 25V256 97656 1x VRL (255256) 1 2490234

2x(2) VRL (255256) 2 4980469

0111 1111 50V 50V256 195313 1x VRL (127256) 1 2480469

25V 25V256 97656 1x VRL (127256) 1 1240234

2x(2) VRL (127256) 2 2480469

0011 1111 50V 50V256 195313 1x VRL (63256) 1 1230469

25V 25V256 97656 1x VRL (63256) 1 0615234

2x(2) VRL (63256) 2 1230469

0000 0000 50V 50V256 195313 1x VRL (0256) 1 0

25V 25V256 97656 1x VRL (0256) 1 0

2x(2) VRL (0256) 2 0





MCP47CXBXX

NOTES


MCP47CXBXX






61 Overview





bull PORBOR




bull Slope Control










63 PORBOR













SCLSCL

MCP47CVBXX

SDASDA

HostController


Other Devices

(Master)(Slave)


MCP47CXBXX








68 Slope Control


69 Pulse Gobbler




Address Byte

RW ACK

Acknowledge Bit

Slave Address

A6 A5 A4 A3


A2 A1 A0













MCP47CXBXX














P


RW = ReadWrite bit

RW


FS Mode HS Mode

HS Mode Continues

FS Mode


Control Byte

Sr


MCP47CXBXX

NOTES


MCP47CXBXX

70 DEVICE COMMANDS





71 Write Commands



72 Read Commands




Command

of Bit Clocks(1)



CodeMode

C1 C0 100 kHz 400 kHz 34 MHz (3)





1 1 Last Address 29 3448 13793 117241








MCP47CXBXX











75 Write Command














MCP47CXBXX











Memory Address

I2C ACK bit(1)




SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

0 0 x A

ADn

D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA

A

P

S xSAn

0 0

I2C Start Bit

I2C Slave Address



I2C Stop Bit(3)




Legend


MCP47CXBXX








00h Yes Yes

01h No Yes

08h Yes Yes

09h Yes Yes

0Ah Yes Yes



S Slave Address

RW

AC

K

Command

AC

K

Data Byte

AC

K

Data Byte

AC

K

P

Master S

SA

6S

A5

SA

4S

A3

SA

2S

A1

SA

0

0 AA

AD

4A

D3

AD

2A

D1

AD

0C

1C

0 x AA

D15

D14

D13

D12

D11

D10

D09

D08 AA

D07

D06

D05

D04

D03

D02

D01

D00 AA P



MCP47CXBXX 0 0 0 0




MCP47CXBXX 0 1 1 1




MCP47CXBXX






D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


D15

D14

D13

D12

D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


AD4

AD3

AD2

AD1

AD0

0 0 x A

Write Command

P

AD4

AD3

AD2

AD1

AD0

0 0 x A

Write Command

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0 AAD4

AD3

AD2

AD1

AD0

0 0 x A


Memory Address

I2C ACK Bit (1)

0

ADn

A

P

S x

SAn

0 0

I2C Start Bit

I2C Slave Address



I2C Stop Bit(3)


Legend


MCP47CXBXX

76 Read Command




bull Single Read





761 SINGLE READ
















MCP47CXBXX








Memory Address(5)

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

1 1 x A

ADn

A

A

PS

x

SAn

1 1

I2C Start Bit

I2C Slave Address

I2C Write Bit

Read Command


I2C Stop Bit(3)

Dnn



Legend

Sr

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

Control Byte

A I2C ACK Bit(2)

I2C NACK Bit(4)A

1 I2C Read Bit



MCP47CXBXX









I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

1 A

A

P

S

SAn

I2C Start Bit


Control Byte

Legend

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


A I2C ACK Bit(2)



MCP47CXBXX


Read 1 Word Command

S Slave Address

RW

AC

K Command

AC

K

Master SS

A6

SA

5S

A4

SA

3S

A2

SA

1S

A0 0 1

AD

4A

D3

AD

2A

D1

AD

0C

1C

0x

1

Sr

Slave Address RW

AC

K

Data Byte AC

K

Data Byte AC

K

P


SA

6S

A5

SA

4S

A3

SA

2S

A1

SA

0

1 1

D1

5D

14

D1

3D

12

D11

D1

0D

09

D0

8 1

D0

7D

06

D0

5D

04

D0

3D

02

D0

1D

00 1 P


Master S 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 x 1

MCP47CXBXX 0 0

I2C Bus S 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 x 0





Master S 1 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 x 1

MCP47CXBXX 0 1

I2C Bus S 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 x 1







MCP47CXBXX








Memory Address(5)

I2C ACK Bit(1)

SA6

SSA5

SA4

SA3

SA2

SA1

SA0

0

0

AAD4

AD3

AD2

AD1

AD0

1 1 x A

ADn

A

A

PS

x

SAn

1 1

I2C Start Bit

I2C Slave Address

I2C Write Bit

Read Command


I2C Stop Bit(3)



Legend

Sr

0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A PA


SA6

SA5

SA4

SA3

SA2

SA1

SA0

1

Control Byte

A I2C ACK Bit(2)

I2C NACK Bit(4)A

1 I2C Read Bit


0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A


0 0 0 0 D11

D10

D09

D08

D07

D06

D05

D04

D03

D02

D01

D00

A A



MCP47CXBXX












S 0 A 0 x x 0 A


0 00 0 0 0 0 x P000


Legend

x




MCP47CXBXX















S 0 A 0 1 1 0 A


0 00 0 0 0 0 0 P000


Legend

0




S 0 A 0 0 1 0 A


0 00 0 0 0 0 1 P000


Legend

1


MCP47CXBXX







bull Motor Control








3 Send Stop bit


1 2 3 4 5 6 7 8 9SCL


Address Byte

Address Bits

RW

StopBit

Device

AC

K

Response

A3A4A5A6


MCP47CXBXX





5

Analog

VDD

1

2

3

8

6

VDD SDA

SCL

VSS

VOUT0

7

R1 R2

To MCU


R1 and R2









C2C1

MCP47CVBX2

Optional




Output

VREF

4 5

LATHVC

VOUT1

C4C3

Analog

VDD

1

2

3

8

6

VDD SDA

SCL

VSS

VOUT0

7To MCU

C2C1

MCP47CVBX2

Optional

Output

VREF

4

LATHVC

VOUT1

C5

Optional

VREF

C6

R1 R2

C4C3


MCP47CXBXX






















R1

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

VOR2 C1

RSENSE

Comp

VDD

VTRIP

Vtrip VOUT

R2R1 R2+--------------------

=


2N


MCP47CXBXX











R1

VCC+

VCC-

VO

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

VOUTR2 C1

R3

VCC+

VCC-

RSENSE

CompVTRIP

R23

R2R3

R2 R3+-------------------=

V23

VCC+R2 VCC-R3 +

R2 R3+------------------------------------------------------=

VTRIP

VOUTR23 V23R1+

R1 R23+---------------------------------------------------=

TheveninEquivalent

R1

R23

V23

VOUT VTRIP


2N

R3

VCC+

VCC-

VO

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

R2

VOUT

VIN

R1

R4 C1

VOA+

VOA+ = VOUT bull R4

R3 + R4


2N


R1

R2

R1


MCP47CXBXX








EQUATION 8-4

EQUATION 8-5






41V1 mV = 4100




R2ndash

R1---------

205ndash4096V-----------------=


R2

R1------

12---=

R4

R3 R4+ ------------------------

205V 05 4096V +15 4096V

-------------------------------------------------------23---= =

If R4 = 20 k then R3 = 10 k

R3

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

R2

VO

VIN

R1

R4C1

R5

Optional

VOA+

VCC+

VCC-

C1 = 01 microF



2N


R3 + R4


R1

R2

R1


VCC+R4 VCC-R5+

R4 R5+---------------------------------------------=

VIN+

VOUTR45 V45R3+

R3 R45+---------------------------------------------=

R45

R4R5

R4 R5+-------------------=

VO VIN+ 1R2

R1------+

VA

R2

R1------ ndash=



MCP47CXBXX

















R1

VCC+

VCC-

VOUT

I2C2-Wire

VREF

Optional

MCP47CVBX2

VDD

I2C2-Wire

VREF

Optional

MCP47CVBX2

VDD

R2

01 microF

VOUT0

VOUT1

(DAC0)

(DAC1)

VOUT =


VOUT0 R2 + VOUT1 R1

R1 + R2


Where

RSENSE

Ib

Load

IL

VCC+

VCC-

VOUT

IL

VOUT

Rsense---------------

1+-------------=

Ib

IL

----=


VDD

I2C2-Wire

VREF

Optional

MCP47CVBXX

VDD

(or VREF)


MCP47CXBXX






















Start



VDD

VDD

VSS VSS

MC

P4

7CX

BX

X

01 microFP

ICreg

Mic

roc

on

tro

lle

r

01 microF

SCL

VOUT

VREF SDA


MCP47CXBXX



bull Noise


81021 Noise








Pin

s

Type Code


Length Width

10 MSOP UN 300 490 1470

10 DFN MF 300 300 900

16 QFN MG 300 300 900



MCP47CXBXX

















Title Literature





MCP47CXBXX


0

47k






VDD SDA

SCL

(DGND) Plane

NCVOUT1 LATHVC

VSS

10 microF 47k

VOUT0

VREF

47Cx

Bxx

0

A1

A0


MCP47CXBXX






3e

3e

Part Number Code

MCP47CVB01-EMF BAJU

MCP47CVB11-EMF BAJX

MCP47CVB21-EMF BAJZ

MCP47CVB02-EMF BAJV

MCP47CVB12-EMF BAJY

MCP47CVB22-EMF BAKA

MCP47CMB01-EMF BAJV

MCP47CMB11-EMF BAJQ

MCP47CMB21-EMF BAJS

MCP47CMB02-EMF BAJP

MCP47CMB12-EMF BAJR

MCP47CMB22-EMF BAJT

XXXXXX

10-Lead MSOP

YWWNNN47CV01

Example

935256

XXXX


PIN 1

YYWWNNN

BAJU

Example

PIN 1

1935256


MCP47CXBXX

Part Number Code

MCP47CVB02-EMG AAD

MCP47CVB12-EMG AAE

MCP47CVB22-EMG AAF

MCP47CMB02-EMG AAA

MCP47CMB12-EMG AAB

MCP47CMB22-EMG AAC

XXX


PIN 1

XYYWWNNN


AAD

Example

PIN 1

1935256


MCP47CXBXX


UN


MCP47CXBXX


UN


MCP47CXBXX




MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX



MCP47CXBXX

NOTES


MCP47CXBXX

















MCP47CXBXX

NOTES


MCP47CXBXX




B1 Overview













SCL SCL

Slave

SDA SDA

Master


Other Devices



MCP47CXBXX










B3 I2C Operation





B311 Start Bit



B312 Data Bit


FIGURE B-3 Data Bit






SDA

SCL

S

1st Bit 2nd Bit



Comment

General Call A

Slave Address Valid

A


A


SDA

SCL

Data Bit

1st Bit 2nd Bit

A

8

D0

9

SDA

SCL


MCP47CXBXX





B315 Stop Bit













SDA

SCL

Sr = Repeated Start

1st Bit

SCL

SDA AA

P

1st Bit

SDA

SCL


SCL

SDA

StartCondition

StopCondition


Data orA Valid


MCP47CXBXX

B34 SLOPE CONTROL







B36 HS MODE











B361 Slope Control


B362 Pulse Gobbler




Address Byte

RW ACK

Acknowledge Bit

7-Bit Slave Address

A6 A5 A4 A3 A2 A1 A0


P

S = Start bit


A = Acknowledge bit


RW = ReadWrite bit

RW


FS Mode HS Mode

HS Mode Continues

FS Mode


Control Byte


MCP47CXBXX

B37 GENERAL CALL







00 0 0S 0 0 0 0 xx x x xA x x 0 A P


Second Byte

7-Bit Command



00 0 0S 0 0 0 0 xx x x xA x x 1 A


Second Byte

Master Address

xx x x x x x x A P




MCP47CXBXX

NOTES


MCP47CXBXX


C1 Resolution










Ideal

Measured 1

Measured 2

VLSb IDEAL VDD

2N

----------- or VREF

2N

-------------=


4032 64ndash ---------------------------------------------------------------=

VLSb


2N

1ndash-----------------------------------------------------------=

40h

3Fh

3Eh

03h

02h

01h

00h

Wip

er

Cod


VW ( Tap)

VS0

VS1

VS3

VS63

VS64


n =


MCP47CXBXX


















EFS


VLSb IDEAL ----------------------------------------------------------------=




EZS

VOUT(ZS)

VLSb(IDEAL)----------------------------=

Where





ET


--------------------------------------------------------------------------------------------------=


MCP47CXBXX







C9 Gain Error (EG)







Ideal Transfer

Actual

DAC Input Code0


Offset

Function

64 4032

VO

UT

Error (EOS)

TransferFunction

VO

UT

Ideal Transfer

Actual

DAC Input Code0


Gain Error (EG)

Function

64 4032 4095

VREF

TransferFunction

( code = 4032)


Where






EG


---------------------------------------------------------------------------------------------------- 100=


MCP47CXBXX











Where






EINL


--------------------------------------------------=

010001000

AnalogOutput(LSb)


1

2

3

4

5

6

0

7

110



INL = lt -1 LSb

INL = 05 LSb

INL = -1 LSb

Where




EDNL


------------------------------------------------------------------------------------ 1ndash=

010001000

AnalogOutput(LSb)

DAC Input Code

011 111100 101

1

2

3

4

5

6

0

7

DNL = 2 LSb

DNL = 05 LSb

110




MCP47CXBXX

C13 Settling Time







C16 -3 dB Bandwidth













Where

PSS is expressed in




55V 27Vndash 55V ----------------------------------------------------------------------------------------------------------=


MCP47CXBXX

NOTES


MCP47CXBXX





Temperature Range





Examples







PART NO X

TemperatureRange

Device

XX

Package

X(1)

Tape andReel


-


MCP47CXBXX

NOTES

















ISBN 978-1-5224-4636-1

DS20006089B-page 123































China - XianTel 86-29-8833-7252





India - PuneTel 91-20-4121-0141




































051419

Features

General Description

Applications






DC Characteristics









DC Notes

















Timing Notes



21 Electrical Data










22 Linearity Data















































































30 Pin Descriptions




32 Ground (VSS)







39 No Connect (NC)



411 Power-on Reset


412 Brown-out Reset

42 Device Memory














50 DAC Circuitry


51 Resistor Ladder















532 Output Voltage









54 Latch Pin (LAT)










61 Overview



63 PORBOR








68 Slope Control

69 Pulse Gobbler



70 Device Commands

71 Write Commands

72 Read Commands




75 Write Command










76 Read Command

761 Single Read






























EQUATION 8-4

EQUATION 8-5






























B1 Overview




B3 I2C Operation



FIGURE B-3 Data Bit









B34 Slope Control



B36 HS Mode


B37 General Call



C1 Resolution














C9 Gain Error (EG)










C13 Settling Time



C16 -3 dB Bandwidth









mcp47cxbxx data sheet - microchip technology...mcp47cxbxx ds20006089b-page 2 2018-2019 microchip...

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