meeting scalp, artemisia and premadona - tu/e · overview •in-car digital ... multi-layer ahb bus...

September 22, 2005

TU e

Farm of Streaming Engines (FaStE)

Meeting SCALP, Artemisia and PreMaDoNa

Meeting SCALP, Artemisia and PreMaDoNa, September 22, 2005. 2

TU e

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TU e

Aim and context

• Aim: to develop a multiprocessor for car infotainment where streaming and control are separated (a farm of streaming engines)

• The multiprocessor should support multiple streams/ applications (HRT/SRT)

• This implies an application driven approach (vertical slice) reusing the results of other methods driven projects (horizontal)

Aethereal

TTL

Hijdra

PreMaDoNa

FaStE


TU e

Overview

• In-car Digital Entertainment applications• Architecture characteristics• Exploration on the integration of a Aethereal network-on-chip (what is available today!)

• Proposed architecture for evaluation• Future goals


TU e

Current In-car Digital Entertainment application

Tile0

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Controller

Tile1

Tile2 Tile

3

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IIS in

IIS in

IIS in

Analog Aux

Analog Aux

Front stereo

Rear stereo

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Digital host in

RDS

Digital host out

Automatic Gain control

Tuner IF

Digital host out

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Digital host out

SPDIF in

Con

trol

Con

trol

Con

trol

Con

trol

Radio

SRC &MP3 Audio post

processing

Hard real-time requirements


TU e

Applications next generationsBroadcast

– High Definition (HD) radio– Satellite Digital Audio Radio Service (SDARS)

On demand audio service– Ripping (e.g. encoding audio)

Audio quality (for car phone)– Noise Reduction (NR)– Acoustic Echo Cancellation (AEC)

Storage media– CD/DVD– Harddisk– Removable discs (e.g. USB stick, flash card)

Connectivity– Bluethooth– USB– WiFi

NavigationVideo


TU e

Current architecture characteristics

DIO Switch

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Arbiter DSPMEM

ITCAHB if

Arbiter DSPMEM

ITCAHB if

Arbiter DSPMEM

ITCAHB if

Arbiter DSPMEM

ITCAHB if

ITC

Multi-layer AHB bus

PeripheralsAccelerators

Controller MEM

VPBDomain 0

VPBDomain 1

VPBDomain 2

MEM MEM MEM MEM MEMDMA SPICD

BlockDec.

AHB2VPB AHB2VPB AHB2VPB

ARM based subsystem

Bottleneck?

Write only / Scalability?

Predictable?


TU e

i i+1 i+2 i+3DSP program memory 2,976 Kbit 8,200 Kbit 23,000 Kbit 63,000 KbitDSP data memory 948 Kbit 2,300 Kbit 6,700 Kbit 20,000 KbitDSP coefficient memory 420 Kbit 1,000 Kbit 2,800 Kbit 8,200 KbitController program memory 6,240 Kbit x x xController data memory 1,088 Kbit x x xAverage memory per DSP tile 1,086 Kbit 1,643 Kbit 2,955 Kbit 5,365 KbitMemory content 55% 68% 77% 84%

Generation

Expected resources for next generations

DSP memory

(# processors–1)

i i+1 i+2 i+3Technology 180 nm 90 nm 90 nm 65 nmPower supply voltage core 1.8 V 1.5 V 1.5 V 1.2 VPower supply voltage ana/IO 3.3 V 2.5 V 2.5 V 2.5 VExternal connections 176 208 260 310Number of gates 1,200,000 gates 2,700,000 gates 6,000,000 gates 13,000,000 gatesNumber of flip flops 80,000 flip flops 180,000 flip flops 370,000 flip flops 800,000 flip flopsFrequency 130 MHz 195 MHz 300 MHz 430 MHzNumber of processors 5 8 12 17Number of accellerators 3 6 9 12Streaming processing power 545 MHz 1600 MHz 3000 MHz 6000 MHz

Generation

Viper≈ 9M gates


TU e

Area of a network?

Tile0

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Tile1

Tile2 Tile

3

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2@48

2@48

2@48

[email protected]

[email protected]

[email protected]

[email protected]

IIS in

IIS in

IIS in

Analog Aux

Analog Aux

Front stereo

Rear stereo

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Digital host in

[email protected]

RDS

Digital host out

Automatic Gain control

Tuner [email protected]

Digital host out

2x2@48

[email protected]

[email protected]

[email protected]

[email protected]

2@325

[email protected]

[email protected]

9x4@

325

9x2@

325

8x2@

325

8x2@

325

9x4@

325

9x2@

325

2@40

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+7@

48

9@44

.1

2@40

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Digital host [email protected]

SPDIF in

1@581@

9.17

1@58C

ontr

ol

Con

trol

Con

trol

Con

trol

1xMulti Channel + 2xStereo + 1xMono

33 streaming channels


TU e

She

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She

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Network connections

Tile 1 Tile 2

Router

I

T

T

I

NI NI

P1 P2

CfgMaster I T

ctr ctr

00

1 1

2 2

3 3

4 4P3 P4

Map each channels to a dedicated

connection

Tile 1 Tile 2

Router

I

T

T

I

NI NI

P1 P2

CfgMaster I T

ctr ctr

00

1 1

2 2P3 P4

Shared address space by sending

addresses

Data

Address & Data


TU e

Proposed architecture for evaluation

CA

DSP

MEM

Router

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NI

NININI

NI

Peripheral tile

NI

ARM based subsystem

Router

NI

NI

Chip area increase≈ 1.5%

Area numbers in CMOS12 before placement and routing

CA

DSP

MEM CA

DSP

MEM CA

DSP

MEM

2network

2routers

2interfaces

mm004.1270.0734.0Area

mm270.0Area

mm734.0Area

=+=

=

=


TU e

Latency of a GT connection

4

2Tile CordicRouter

I

T

T

I

36

18

c

c

NI

36

18

c

c

NI

Slot table size = 2 slots

125MHz 500MHz 250MHz

P1

P2

CRD

Time wheel2*3*1/500MHz

Router3*1/500MHz

6ns

NI kernel3*1/500MHz

6ns

Shell(2*1/125MHz)

16ns

ClockDomaincrossing

(2*1/500MHz)4ns 12ns

NI kernel3*1/500MHz

6ns

ClockDomaincrossing

(2*1/250MHz)8ns

Shell(2*1/250MHz)

8ns

8nsShell

(2*1/250MHz)

4nsClock

Domaincrossing

(2*1/500MHz)

12ns6nsNI kernel

3*1/500MHz

6nsRouter

3*1/500MHz

6nsNI kernel

3*1/500MHz

16nsClock

Domaincrossing

(2*1/125MHz)

16nsShell

(2*1/125MHz)

Time wheel2*3*1/500MHz

2

2

0.5 1.5 0.75

1.5

0.75 0.75 1 1

10.51.50.750.750.752

18Cordic

(36*1/250MHz)144ns

Round trip latency ≤ 37 clock cycles

4

2

Round trip latency Caracas ≤ 36 clock

cycles


TU e

Future goals

• To build the proposed architecture in a SystemC environment using parts from Bolivar and Æthereal

• Have models of the application and architecture to derive the temporal behavior of the system

• Mapping applications to do analysis on the architecture and models

• Definition of next generation architectures for In-Car Digital Entertainment that support applications like audio, wireless streaming, connectivity, navigation, video, etc.

meeting scalp, artemisia and premadona - tu/e · overview •in-car digital ... multi-layer ahb bus...

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