memory design considerations that affect price and performance bill gervasi technology analyst,...
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![Page 1: Memory Design Considerations That Affect Price and Performance Bill Gervasi Technology Analyst, Transmeta Chairman, JEDEC Memory Parametrics bilge@transmeta.com](https://reader036.vdocument.in/reader036/viewer/2022062515/56649c995503460f949553dd/html5/thumbnails/1.jpg)
Memory Design Considerations That Affect
Price and Performance
Memory Design Considerations That Affect
Price and PerformanceBill Gervasi
Technology Analyst, Transmeta
Chairman, JEDEC Memory Parametrics
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Posed at the Last ConferencePosed at the Last Conference
Why will DDR-I at 400 MHz data rate be a “boutique” solution?
Why will DDR-II at 400 MHz data rate be a “mainstream” solution?
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AgendaAgenda
JEDEC/Industry RoadmapFactors for Market AcceptanceDifficulties in Achieving 400 MHzFactors Affecting CostWild Cards – What Can Change?
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RAM EvolutionRAM Evolution
2100MB/s
2700MB/s
MainstreamMemories
DDR266
DDR333Simple,
incrementalsteps
DDR4003200MB/s DDR533
4300MB/s DDR6675400MB/s
“DDR I”
“DDR II”
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Factors for Market AcceptanceFactors for Market Acceptance
Industry FocusNumber of Competing SuppliersJEDEC standardLaws of Physics
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Industry FocusIndustry Focus
The JEDEC roadmap represents the industry focus for mainstream productsDDR-I tops out at 333 MHz data rateDDR-II starts at 400 MHz data rate
This DOES NOT mean that DDR-I at 400 MHz data rate will not ship in volume
It DOES mean that there will be price premiums for this speed bin
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What do I mean by “Focus”?What do I mean by “Focus”?
There is serious work to hit 400 MHzVendor interoperable solutionsMix and match module configurationsSignal integrity analysis
We are counting picosecondsNo JEDEC standard yet proposed for DDR-I
at 400 MHz data rate
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For Example…For Example…
How we are getting more refined in timing analysis with DDR-II…
The Charge Transfer Model for input timing measurement and derating
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DDR-I Input Timing ModelDDR-I Input Timing Model
INPUT
Setup Hold
CLOCK
CLOCK
Timing derating by input signal slew rate:
1.0V/ns = base value
0.5V/ns = base value + 50ps
0.4V/ns = base value + 100ps
This got us through DDR333…
The Old Way
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However…However…
This simplified model was good enough for DDR333 data rates, but leaves picoseconds of available timing lying around needed for 400+!!!
DDR266 Data Setup/Hold = 750 psDDR333 Data Setup/Hold = 600 psDDR400 Data Setup/Hold = 400 psDDR533 Data Setup/Hold = 350 ps
Can’t waste time!!!
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“Focus” on Input Timing“Focus” on Input Timing
INPUT
DDR-II Charge Transfer Timing ModelAll inputs have a slew rate dependent aspect tEXT
and an independent aspect tINT
Summing tEXT + tINT gives input transition time tT
Transition time tT has min and max valuesDifferential input transitions inherently different
tINTtEXT
tT
The New Way
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tEXT for Slow Slew Rate, Single EndedtEXT for Slow Slew Rate, Single Ended
VREF
VIHAC = VSAT
VIHDC
VILDC
VILAC=
VSAT
tEXT
AT = Charge to Transition
slew
At TEXT
*2
tINT
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tEXT for Fast Slew Rate, Single EndedtEXT for Fast Slew Rate, Single Ended
VREF
VIHAC =VSAT
VIHDC
VILDC
VILAC =VSAT
tEXT
tSAT
ASAT = Charge to Saturation
AADD = Charge after Saturation
AT = ASAT + AADD
SAT
SATTSATEXT V
AAtt
)(
VSAT = Saturation Voltage
tINT
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tEXT for Slow Slew Rate, DifferentialtEXT for Slow Slew Rate, Differential
VREF
VIHAC =VSAT
VIHDC
VILDC
VILAC =VSAT
AT = Charge to Transition
tEXTtINT
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tEXT for Fast Slew Rate, DifferentialtEXT for Fast Slew Rate, Differential
VREF
VIHAC =VSAT
VIHDC
VILDC
VILAC =VSAT
AT = ASAT + AADD
tEXT tINT
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“Focus” on Timing“Focus” on Timing
INPUT
Setup
CLOCK
CLOCK
DDR-II Charge Transfer Timing ModelSetup = tTmax of input - tTmin of reference
tTmax
tTmin
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“Focus” on Timing“Focus” on Timing
INPUT
Hold
CLOCK
CLOCK
DDR-II Charge Transfer Timing ModelHold = tTmax of reference - tTmin of input
tTmin
tTmax
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How does this help…?How does this help…?
The Charge Transfer Model gives a higher accuracy for setup and hold relationships
It also provides a way to accurately describe derating for input slew rate
These models are negotiated with all suppliers to define an industry standard
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DDR-II Input Derating TablesDDR-II Input Derating Tables
2.00.5
0.5
1.0
1.0
2.0
Strobe (mV/ps avg)
Dat
a (m
V/p
s)
2.00.5
0.5
1.0
1.0
2.0
Clock (mV/ps avg)
Add
r (m
V/p
s)
2.00.5
0.5
1.0
1.0
2.0
2.00.5
0.5
1.0
1.0
2.0
HOLD
SETUP SETUP
HOLD
0
0
+
+
+
+
+
+
Strobe (mV/ps avg)
Dat
a (m
V/p
s)
Clock (mV/ps avg)A
ddr
(mV
/ps)
++
0
+
+
++
0
+
+
+
+
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Derating Using Charge TransferDerating Using Charge Transfer
Accuracy from derating both signals and references Result is a two dimensional matrix relating inputs & their
references Identified inherent asymmetries in derating of setup & hold
when mixing single ended with differential signals Memory module mixes impact slew rates
The Charge Transfer model controls system cost by enabling more complex timing analysis
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Charge Transfer on DDR-I?Charge Transfer on DDR-I?
This model would also help design high speed DDR-I systems
However, the work to retrofit this to DDR-I needs to be done to benefit from it
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DDR-II ImprovementsDDR-II Improvements
DDR-II introduces technical improvements that reduce the cost of achieving high speedsPrefetch 4Differential data strobeI/O CalibrationLower I/O VoltageOn-Die Termination
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Prefetch 4Prefetch 4
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Moving to the Next LevelMoving to the Next Level
Today’s SDRAM architectures assume an inexpensive DRAM core timing
DDR I (DDR200, DDR266, and DDR333) prefetches 2 data bits: increase performance without increasing timing costs
DDR II (DDR400, DDR533, DDR667) prefetches 4 bits internally, but keeps DDR double pumped I/O
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Prefetch 2 Versus 4Prefetch 2 Versus 4CK
READ
Prefetch 2
Prefetch 4
Core access time
Costs $$$
Essentially free
data
Column cycle time
Costs $$$
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Prefetch Impact on CostPrefetch Impact on CostBy doubling the prefetch depth, cycle time for column
reads & writes relaxed, improving DRAM yields
DDR-I
DDR-II
Pre-fetch
2
2
2
4
4
4
266
333
400
400
533
667
7.5 ns
6 ns
5 ns
6 ns
7.5 ns
10 ns
DDR Family
Data Rate
Cycle Time
Starts to get REAL EXPENSIVE!
Comparable to DDR266 in cost
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Why Not Prefetch = 8?Why Not Prefetch = 8?
DIMM width = 64 bitsPCs use 64b, servers use 128b (2 DIMMs)
64 byte prefetch okay for PC, but…128 byte prefetch for servers wastes bandwidth
DDR-II must service all applications well to insure maximum volume minimum cost
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Differential Data StrobeDifferential Data Strobe
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Differential Data StrobeDifferential Data Strobe
Just as DDR added differential clock to SDRDDR II adds differential data strobe to DDR I
Transition at the crosspoint of DQS and DQS
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Differential Data StrobeDifferential Data Strobe
DQShigh time
VREF
DQSlow time
DQS
DQShigh time
VREF
DQSlow time
DQS
Normal balanced signal
Mismatched Rise & Fall signal
Error!
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Differential Data StrobeDifferential Data Strobe
DQShigh time
VREF
DQSlow time
DQS
DQShigh time
VREF
DQSlow time
DQS
Normal balanced signal
Mismatched Rise & Fall signal
DQS
DQS
Significantly reduced symmetry error
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I/O CalibrationI/O Calibration
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I/O CalibrationI/O Calibration
Balance pull-up and pull-down driver strengthReduces timing errors from signal asymmetryInsures signal rise and fall times are similar
Reference
Data
DataController
DRAM
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1.8V I/O Voltage1.8V I/O Voltage
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1.8V Signaling1.8V Signaling2.5V
SSTL_18
1.60V
0.90V
1.43V
1.07V
1.25V
0V
0.90V1.03V
0.77V0.65V
1.15V
1.8V
VSS
VDDQ
VREF
VIHac
VIHdc
VILdc
VILacVREF
VSS
VDDQ
VIHac
VIHdc
VILdc
VILac
SSTL_2
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I/O Voltage Impact on TimingI/O Voltage Impact on Timing
Assume 1mV/ps edge slew rateDDR-I = 700 mV (VILVIH) = 700 ps
DDR-II = 500 mV (VILVIH) = 500 ps
Helps meet the need for speedSignal integrity is a serious challenge at
DDR-I and 400 MHz data rate
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On-Die TerminationOn-Die Termination
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On-Die TerminationOn-Die Termination
Reduces system cost while improving signal integrity
Data
Controller
VTT =VDDQ 2
DRAM
Data
Controller
DRAM
VDDQ 2VDDQ 2
DDR-I
DDR-II
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What Can Change?What Can Change?
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Wild CardsWild Cards
100% yield of 5 ns cycle time cores (magic?)Industry gets excited about engineering
DDR-I at 400 MHzDDR-II slow transition from schedule or price
Feature creepDie penaltiesDRAM guys trying to make money for once
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ConclusionsConclusions
DDR-I at 400 will ship in volume but…not likely to cross over $/bitIndustry focus is on transition to DDR-II
for 400+ MHz data rates
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Thank YouThank You