memory devices - wellesley collegecs240/s16/slides/ram.pdfsram: static random access memory in the...

MemoryDevices

Small:Registerfile (groupofnumberedregisters)

Medium:SRAM (StaticRandomAccessMemory)

Large:DRAM (DynamicRandomAccessMemory)

Future?

1

ALU

Processor:DataPathComponents

Registers MemoryInstructionFetch andDecode

12 3

SRAM:StaticRandomAccessMemory

In the Verilog for the register fi le in Figure C.8.11, the output ports corresponding to the registers being read are assigned using a continuous assignment, but the register being written is assigned in an always block. Which of the following is the reason?

a. There is no special reason. It was simply convenient.

b. Because Data1 and Data2 are output ports and WriteData is an input port.

c. Because reading is a combinational event, while writing is a sequential event.

C.9 Memory Elements: SRAMs and DRAMs

Registers and register fi les provide the basic building blocks for small memories, but larger amounts of memory are built using either SRAMs (static random access memories) or DRAMs (dynamic random access memories). We fi rst dis cuss SRAMs, which are somewhat simpler, and then turn to DRAMs.

SRAMsSRAMs are simply integrated circuits that are memory arrays with (usually) a single access port that can provide either a read or a write. SRAMs have a fi xed access time to any datum, though the read and write access characteristics often differ. An SRAM chip has a specifi c confi guration in terms of the number of addressable locations, as well as the width of each addressable location. For example, a 4M × 8 SRAM provides 4M entries, each of which is 8 bits wide. Thus it will have 22 address lines (since 4M = 222), an 8-bit data output line, and an 8-bit single data input line. As with ROMs, the number of addressable locations is often called the height, with the number of bits per unit called the width. For a variety of technical reasons, the newest and fastest SRAMs are typically available in narrow confi gurations: × 1 and × 4. Figure C.9.1 shows the input and output signals for a 2M × 16 SRAM.

Check Yourself

static random access mem ory (SRAM) A memory where data is stored statically (as in fl ip-fl ops) rather than dynami cally (as in DRAM). SRAMs are faster than DRAMs, but less dense and more expensive per bit.

FIGURE C.9.1 A 32K × 8 SRAM showing the 21 address lines (32K = 215) and 16 data inputs, the 3 control lines, and the 16 data outputs.

SRAM2M 3 16

Dout[15–0]

Address21

Din[15–0]16

Chip select

Output enable

Write enable

16

C-58 Appendix C The Basics of Logic Design

AppendixC-9780123747501.indd 58AppendixC-9780123747501.indd 58 26/07/11 6:29 PM26/07/11 6:29 PM

3

SRAMreadport:dataoutLargeregister filesare impractical.BigMUX=significant gatedelay.

Largememories useasharedoutputline.

Nocentralgates/MUX tochooseoutput!

5

WiredORs

Danger,WillRobinson!

(don'ttrythisathome/inthe lab,kids)

6

(noninverting) tristate buffers

Control

In Out

In Control Out0 0 Z1 0 Z0 1 01 1 1

7

(activehigh)

SRAMcell

8

oneoption

QD

CD Latch

QEnable

DataIn

Clock DataOut

TristateBuffer

SRAMwriteport:

C.9 Memory Elements: SRAMs and DRAMs C-61

FIGURE C.9.3 The basic structure of a 4 × 2 SRAM consists of a decoder that selects which pair of cells to activate. The acti vated cells use a three-state output connected to the vertical bit lines that supply the requested data. The address that selects the cell is sent on one of a set of horizontal address lines, called word lines. For simplicity, the Output enable and Chip select signals have been omitted, but they could easily be added with a few AND gates.

latch

D

C

Enable

Q

D

0

2-to-4decoder

Write enable

Din[1]

latch

D

C

Enable

Q

D

Din[1]

Dout[1] Dout[0]

latch

D

C

Enable

Q

D

1

latch

D

C

Enable

Q

D

latch

D

C

Enable

Q

D

2

latch

D

C

Enable

Q

D

latch

D

C

Enable

Q

D

3

latch

D

C

Enable

Q

D

Address


Writeenable

Address

Dout[1] Dout[0]

Din[1] Din[0]

2-to-4decod

er

0

1

2

3

Writeenable

Addressselect

Din[i]

C.9 Memory Elements: SRAMs and DRAMs C-61

FIGURE C.9.3 The basic structure of a 4 × 2 SRAM consists of a decoder that selects which pair of cells to activate. The acti vated cells use a three-state output connected to the vertical bit lines that supply the requested data. The address that selects the cell is sent on one of a set of horizontal address lines, called word lines. For simplicity, the Output enable and Chip select signals have been omitted, but they could easily be added with a few AND gates.

latch

D

C

Enable

Q

D

0

2-to-4decoder

Write enable

Din[1]

latch

D

C

Enable

Q

D

Din[1]

Dout[1] Dout[0]

latch

D

C

Enable

Q

D

1

latch

D

C

Enable

Q

D

latch

D

C

Enable

Q

D

2

latch

D

C

Enable

Q

D

latch

D

C

Enable

Q

D

3

latch

D

C

Enable

Q

D

Address


Dataout:

Datain:

Dout[i]

Organizationofa16x4SRAM

10

4to16decoder

4-bitaddress

dataout

(oneoption)

Selecting location1101

4to16decoder

dataout

1101

11

4-bitaddress

Anotherorganizationofa16x4SRAM

top2bitsaddress

Mux Mux Mux Mux

bottom2bitsaddress

Split-level row/columnaddressing=physicalmultidimensional array!

(row)

(column)

12

2to4decoder

Notice thesmaller decoder...howdoesthisaffecttiming?


top2bitsaddress

Mux Mux Mux Mux

bottom2bitsaddress

(row)

(column)

13

2to4decoder

Nibbles"striped" across4smallermemories.

0010

1000

2

2

4


top2bitsaddress

Mux Mux Mux Mux

bottom2bitsaddress

(row)

(column)

14

2to4decoder

Nibbles "striped"across4smallermemories.

1101

0111

22

4

Whatvaluedoeslocation1010hold?

0 1 1 11 0 0 01 1 0 00 1 1 0

0 1 0 00 1 1 00 1 0 11 0 0 0

1 0 0 01 0 0 11 1 0 10 0 0 1

0 0 1 10 0 0 11 1 0 11 1 1 1

Mux Mux Mux Mux

15

2to4decoder

1010

22

4

Organizationofa4Mx8SRAM

FIGURE C.9.4 Typical organization of a 4M × 8 SRAM as an array of 4K × 1024 arrays. The fi rst decoder generates the addresses for eight 4K × 1024 arrays; then a set of multiplexors is used to select 1 bit from each 1024-bit-wide array. This is a much easier design than a single-level decode that would need either an enormous decoder or a gigantic multiplexor. In practice, a modern SRAM of this size would probably use an even larger number of blocks, each somewhat smaller.

12to

4096decoder

Address[21–10]

4096

4K !1024

SRAM

4K !1024

SRAM

4K !1024

SRAM

4K !1024

SRAM

4K !1024

SRAM

4K !1024

SRAM

4K !1024

SRAM

4K !1024

SRAM

Mux

Dout7

Mux

Dout6

Mux

Dout5

Mux

Dout4

Mux

Dout3

Mux

Dout2

Mux

Dout1

Mux

Dout0

1024Address[9–0]

C-62

A

ppendix C

The Basics of Logic D

esign

AppendixC

-9780123747501.indd 62A

ppendixC-9780123747501.indd 62

26/07/11 6:29 PM

26/07/11 6:29 PM

=4MBmemory, sizeofalargecacheformodern laptop

Inpractice,single setofdatalinesoftentime-shared forread(out)/write(in). 16

(oneoption)

DynamicRAM=DRAMDRAMstoresbitaschargeoncapacitor:

• 1transistor accesses storedcharge.• requires periodic refresh =read-write

(dynamicpower)

SRAM storesbitonpairofinvertinggates:• several transistors• requires continuous (static)power.

Word line

Pass transistor

Capacitor

Bit line

FIGURE C.9.5 A single-transistor DRAM cell contains a capacitor that stores the cell contents and a transistor used to access the cell.

Address[10–0]

Rowdecoder

11-to-2048

2048 ! 2048array

Column latches

Mux

Dout

FIGURE C.9.6 A 4M × 1 DRAM is built with a 2048 × 2048 array. The row access uses 11 bits to select a row, which is then latched in 2048 1-bit latches. A multiplexor chooses the output bit from these 2048 latches. The RAS and CAS signals control whether the address lines are sent to the row decoder or col umn multiplexor.



17

DRAMdesign

Word line

Pass transistor

Capacitor

Bit line

FIGURE C.9.5 A single-transistor DRAM cell contains a capacitor that stores the cell contents and a transistor used to access the cell.

Address[10–0]

Rowdecoder

11-to-2048

2048 ! 2048array

Column latches

Mux

Dout

FIGURE C.9.6 A 4M × 1 DRAM is built with a 2048 × 2048 array. The row access uses 11 bits to select a row, which is then latched in 2048 1-bit latches. A multiplexor chooses the output bit from these 2048 latches. The RAS and CAS signals control whether the address lines are sent to the row decoder or col umn multiplexor.



Accesses entire row,storesincolumnlatches.Mainlyused forrefreshing entire rowatatime.Accessingothercolumnsinsamerowagaincheaper...?

Singlesetofaddress lines,time-shared forrowaddress, columnaddress.

18

(oneoption)

64-bitDRAM

3to8row

decoder

Mux

Column latches

19

3-bitaddress

Dataout

Readingbitataddress1010111.Selectrow

3to8row

decoder

Mux

Column latches

20

3-bitaddress

101

Dataout

Readingbitataddress1010112.Copyrowtolatches

3to8row

decoder

Mux

Column latches

21

Rowisfading!

3-bitaddress

101

Dataout

Readingbitataddress1010113.Refreshrowfromlatches

3to8row

decoder

Mux

Column latches

22

Refresh.

3-bitaddress

101

Dataout

Readingbitataddress1010114.Selectcolumnfromlatches

3to8row

decoder

Mux

3-bitaddress

Column latches

23

011

Dataout

memory devices - wellesley collegecs240/s16/slides/ram.pdfsram: static random access memory in the...

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