memory em4056 and its security
DESCRIPTION
Memory EM4056 and its security. J.-D. Chatelain. 10 10 10. Laser ROM. 01. 10. 11. LSB. MSB. OTP Write protection of one word. The memory is made up of 128 words, each of 18 bits. - PowerPoint PPT PresentationTRANSCRIPT
©Contrinex 2013 - JDCPPT_LF_MemoryEM4056
Memory EM4056and its security
J.-D. Chatelain
OTP Write protection of one wordOTP Read and Write protection of one wordThe word at address 126 permits configuration of the soft protection activated by the password, which is found at address 127
000001002003004005006007008009010011
MS
B
LS
B
100%
25%
50%
75%
Laser ROM1 01 01 0
The memory is made up of 128 words, each of 18 bitsThe last two bits of each word (LSB: Least Significant Bits) are dedicated to its protection
The first three words (laser ROM) contain the transponder’s unique identification number
122123124125126127
The following three words are reserved for CONTRINEXThere remain 16 usable bits per word for data
0 00 00 00 00 00 00 00 00 00 00 00 00 0
OTP (One Time Programmable) Read protection of one word
0 1
1 0
1 1
A memory word in binary Mas
k pr
otec
ted
regi
on
Writ
e pr
otec
tion
Rea
d pr
otec
tion
Its equivalent in HEX
Reading a protected word without login
Result of a reading
Setting the « Mask protected region » bit
TAG not logged in
Reading a protected word with login
Mas
k pr
otec
ted
regi
on
Writ
e pr
otec
tion
Rea
d pr
otec
tion
Result of a reading
TAG logged in
When words are protected with a « Password », they can be accessed
only with a login.
When a word is protected by a « Read protection » bit, it may only
be compared with a known word.
Comparison
Result of reading transponder addresses 20 through to 24
Result of reading the same addresses after having protected addresses 21 and 22
Content of the memory of the transponder
Content of the memory of the transponder
The acknowledgment (error) code "0“, after the second phase, indicates that the entered data is identical to the data stored in the memory
The acknowledgment (error) code "4" after the second phase indicates that the entered data is not identical to the data stored in the memory.
Complete words are to be compared
©Contrinex 2013 - JDCPPT_LF_MemoryEM4056
End of this chapterMemory EM4056and its security
J.-D. Chatelain