memory hierarchy and cache design (4). reducing hit time 1. small and simple caches 2. avoiding...
DESCRIPTION
Small and Simple Caches Alpha AXP has –Direct-mapped 8-KB ( byte blocks) L1 instruction cache and date cache –Direct-mapped 128-KB to 8-MB L2 cache Becomes increasing important due to the pressure of a fast clock cycleTRANSCRIPT
Memory Hierarchy and Cache Design (4)
Reducing Hit Time
1. Small and Simple Caches
2. Avoiding Address Translation During Indexing of the Cache
– Using virtual caches– Accessing physical caches without address translation
3. Pipelining Writes for Write Hits
Small and Simple Caches
• Alpha AXP 21064 has – Direct-mapped 8-KB (256 32-byte blocks) L1 instruction
cache and date cache– Direct-mapped 128-KB to 8-MB L2 cache
• Becomes increasing important due to the pressure of a fast clock cycle
Using virtual caches• Cache is indexed and/or tagged with the virtual address• Cache access and MMU translation/validation done in
parallel• Physical address saved in tags for later write-back but not
used during indexing
processor datavirtual/physical address tags
main memory
address mapper
cache miss
virtual address
physical address
Using virtual caches
• Problems with virtual caches
– homonym problem
– synonym problem
Homonym problem
100 1000
100 10 100 20
process 1 translation information
process 2 translation information
process 1 writes 1000 to virtual page 100
process 2 read from virtual page 100
context-switched to process 2
tag data
100
Homonym problem
Solutions to homonym problem
1. Cache perging at each context switch
2. Using PID (process id) as an additional ta
g
3. Virtually-index physically-tagged caches
Homonym problem
Synonym problem
100200
100
100200
100200
5
55
105
1010
process 1 reads from virtual page 100
process 1 reads from virtual page 200
process 1 writes 10 to virtual page 100
process 1 reads from virtual page 200
process 1 translation information
tag data
Synonym problem
Solutions to synonym problem1. Hardware anti-aliasing2. Alignment of synonyms (require all the sy
nonyms to be identical in the lower bits of their virtual addresses assuming a direct-mapped cache)
Accessing physical caches without address translation
virtual page #
compare
cache
Latch
Address mapper
page offset
LatchLatch
compare
set index
Pipeline stage boundary
Tags Data
cache data (if cache hit)To Processor
real address
set select
k-way cache output
Pipelining Writes for Fast Write Hits
tag comparison
actual writing
tag comparison
tag comparison
actual writing
actual writing
Time
Write request i + 1Write request i
Write request i + 1Write request i
Write request i - 1
Write request i - 1
Pipelining Writes for Fast Write Hits
Summary of Cache Optimizations
Summary of Cache Optimizations