memory test updated v3 reduced

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Memory Test

Manuel d’AbreuSanta Clara University

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Outline

IntroductionMemory modelingFailure mechanisms and fault modelingTest algorithms for RAMMemory Built In Self Test (MemBIST)

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Growth Trends

1970 74 78 82 86 90 94Year

10M

100M

1M

10K

100K

1K

98 02 06 10 14

1B

10B

100B

1G

Num

ber o

f bit

per c

hip

Num

ber o

f tra

nsis

tor p

er c

hip

Microprocessors

RAMs

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IntroductionMemories (esp. RAM) are at the forefront of commercial electronic designs

DRAMs are the technology driver for the semiconductor industry

Memories are the most numerous IPs used in SOC designs (hundreds ! and >90% of an SoC in 2010)

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Main Types of Semiconductor Memory RAMs: Random Access Memories

Dynamic Random Access Memory (DRAM)Highest possible densitySlow access time (typically 20ns)Information stored as charge on capacitor and should be refreshed

Static Random Access Memory (SRAM)Fastest (typically 2ns)Information stored in cross coupled latches

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Main Types of Semiconductor Memory RAMs: Random Access Memories

Dynamic Random Acess Memory (DRAM)Highest possible densitySlow access time (typically 20ns)Information stored as charge on capacitor and should be refreshed

Static Random Acess Memory (SRAM)Fastest (typically 2ns)Information stored in cross coupled latches100k

1M

10M

100M

1G

10G

82 86 90 94 98 02 06

1G512M

256M128M

64M16M

4M

256k

Number of MemoryNumber of MemoryCells per ChipCells per Chip

1M

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Memory Architecture

Memorycell

Decoder

Sense Amplifiers/Write Drivers

Memory Data Register

Dec

oder

MemoryAddressRegister

Read/writeControls

r

c

Array of Cells

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Functional SRAM Chip Model

RefreshAddress

Address latch Column decoderRefresh logic

MemoryCell Array

Write driver

Data registerSense amplifiers

Rowdecoder

Data out Data in

R/W and CE

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Functional SRAM Chip ModelAddress

Address latch Column decoder

MemoryCell Array

Write driver


Rowdecoder

Data outData in

R/W andCE

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Functional RAM Chip Model

RefreshAddress

Address latch Column decoder Refresh logic

MemoryCell Array

Write driver


Rowdecoder

Data out Data in

R/W and CE

Vss

WL

BL BL

Vdd

6-devices SRAM cellpoly

Vss

WL

BL BL

Vdd

6-device SRAM celldepletion

VssVss

WLWL

BLBL BLBL

VddVdd

6-device SRAM cellCMOS

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Functional RAM Chip Model

RefreshAddress


MemoryCell Array

Write driver


Rowdecoder

Data out Data in

R/W and CE

RAM write circuitRAM write circuit

Data inData in

BLBL BLBL

WriteWrite

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Functional RAM Chip ModelRefreshAddress


MemoryCell Array

Write driver


Rowdecoder

Data out Data in

R/W and CE

single-device DRAM cell

WLWL

BLBLCC

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Functional RAM Chip ModelRefreshAddress


MemoryCell Array

Write driver


Rowdecoder

Data out Data in

R/W and CE

Two dimensional decoding schemeTwo dimensional decoding scheme(saves decoder and wiring area)(saves decoder and wiring area)•• row decoder select row of cells via WLrow decoder select row of cells via WL•• column decoder column decoder

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Memory Cell Designs

(b)

BL BLWL

CBL

BL

Cbit

(c)

WL

(a)

Q

Q

SET

CLR

D

NP1PL1NL1

NP2PL2NL2

Bit

Bitb

ar

Drain Drain

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Reduced Functional ModelRefreshAddress


MemoryCell Array

Write driver


Rowdecoder

Data out Data in

R/W and CE

Address decoder

Memory Cell Array

Read / Write logic

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Reduced Functional Model (cont)

Address decoder

Memory cell array

Read/write logic

Address

Data

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Memory testing

Memory testing has to prove that the circuits under test behave as designed, it consists of:

Parametric tests which concern voltage/current levels and delays on the IO pins of the chipFunctional testing including dynamic testing

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Parametric (Electrical) Testing

DC Parametric testingContact testPower consumptionLeakage testThreshold testOutput drive current testOutput short current test

AC Parametric testingRise and fall timeSetup and hold timeDelay testSpeed test

IDDQ testing (CMOS memories only)

Zero defect approachUse to detect some defects not handle by functional testing

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Functional faults

Cell stuckDriver stuckRead/write line stuckChip-select line stuckData line stuckOpen in data lineShorts between data linesCrosstalk between data lines

Address line stuckOpen in address lineShorts between address linesOpen decoderWrong accessMultiple accessCell can be set to 0 and not to 1 (or vice versa)Pattern sensitive interaction between cells

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Functional faults



Either a memory Either a memory cell or a data cell or a data

registerregister

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Functional faults



Either a memory cell or a data register

Any wiring connection in the memory

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Fault Models: Address decoder Fault AF

1. A certain address access no cell

2. A certain cell is never accessed

3. A certain address access multiple cells

4. A certain cell is accessed by multiple addresses

Ax

Cx

Cx

CyAx

Ax

Ay

Cx

4 Address decoder Faults which cannot stand alone 4 Address decoder Faults which cannot stand alone ((assuming same fault during read and write operations and no sequassuming same fault during read and write operations and no sequential ential

behavior of the faulty decoder)behavior of the faulty decoder)

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Fault Models: Address decoder Fault AF

4 Combinations of Address decoder Faults

Fault A: 1+2

Fault B: 1+3

Fault C: 2+4

Fault D: 3+4

Ax Cx

Cx

CyAy

Ax

Ax

Ay

Cx

Cy

Ax

Ay

Cx

Cy

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Conditions for detecting address faults AF

The March test should contain the two following march elements

↑(rx, … , wx)↓(rx, … , wx)

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Functional Memory FaultsA functional fault model is a non-empty set of fault primitives

A fault primitive is a difference between the observed and the expected memory behavior

A fault primitive is denoted by <S/F/R>S describes the sensitizing operation sequenceF describes the state stored in the faulty cellR describes the output of the read operation

For example <1/0/-> is a stuck-at 1 and <0w1/0/-> is a rising transition fault

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Static and Dynamic faults

Static faults: sensitization needs only one operation (Testable by common March Tests)

Static Single-Cell Faults (S1CF)Static Two-Cell Faults (S2CF)

Dynamic faults: sensitization needs more than one operation (Not testable by common March Tests)

Dynamic Single-Cell Faults (D1CF)Dynamic Two-Cell Faults (D2CF)…

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S1CF: Stuck-at fault (SAF)

The logic value of (a line or) a cell is always 0 (SA0) or 1 (SA1)To detect memory cell's SAFs:

SA0: Write 1 Read 1 (w1 r1)SA1: Write 0 Read 0 (w0 r0)

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S1CF: Transition Fault

A cell fails to undergo a 0 → 1 transition (TF

rise) or a 1 → 0 transition (TF

fall) when it is

written

To detect transition fault:TF

rise: w0 w1 r1

TFfall

: w1 w0 r0

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Basic Transitions

0 W1

W0

Stuck-at 01 W1W0

Stuck-at 1

0 1 W1

W1

W0W0

Write 0 on cell C(j)Read C(j)Write 1 on cell C(j)Read C(j)

Requires accessing each cell 4 times (2 writes and 2 reads). If access time is ta the testing time is 4Nta

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Transition Fault

0 1 W1

W1

W0W0

0 to 1 Transition Fault

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Coupling Faults

Cell i Cell j

a a

a c

Inversion

Idempotent

(a)

(b)

b

S

N

EW

(c)

b

S

N

EW

NW

SW SE

NE

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S1CF: Read Disturb Faults (RDF)

A Cell is said to have a RDF if the read operation performed on the cell returns an incorrect value while changing the contents of the cell to the wrong valueTo detect Read Disturb Fault from each cell a 1 and a 0 should be read

r0r1

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S1CF: Deceptive Read Disturb Faults (DRDF)

A Cell is said to have a DRDF if the read operation performed on the cell returns the expected value while changing the contents of the cell to the wrong value

To detect Deceptive Read Disturb Fault each cell should be read twice successively. The first read sensitize the fault and the second detects it

r0r0r1r1

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S1CF: Incorrect Read Faults (IRF)

A Cell is said to have a IRF if a read operation performed on the cell returns the incorrect value while keeping the correct stored value in the cell

To detect Incorrect Read Fault from each cell a 1 and a 0 should be read

r0r1

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S1CF: Write Disturb Faults (WDF)

A Cell is said to have a WDF if a non transition write operation causes a transition in the cell

To detect Write Disturb Fault each cell should be read after a non-transition write

0w0r01w1r1

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Fault models: Coupling Fault (2 cells)

Implies two cells: the victim cell and the aggressor cell

Different kinds of coupling faults:Inversion coupling faultsIdempotent coupling faultsState coupling faultsDynamic coupling faultsBridging faults……..

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S2CF: Inversion Coupling Fault

Inversion Coupling Fault (CFin): The content of the victim cell is inverted if the aggressor cell has a transition

According to the kind of transition (0 → 1 or 1 → 0) there is two possible CFin types:

< ↑ ; > < ↓ ; >To detect CFin between cell x (victim) and y (aggressor)

CFin (y rise → x inverted): w0x w0y w1y r0x.CFin (y fall → x inverted): w0x w1y w0y r0x.

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S2CF: Idempotent Coupling Fault

Idempotent Coupling Fault (CFid): The victim is forced to 0 or 1 if the aggressor has a 0 → 1 or 1 → 0 transition

According to the kind of transition (0 → 1 or 1 → 0) there is four possible CFid types:

< ↑ ; 0 > < ↓ ; 0 > < ↑ ; 1 > < ↓ ; 1 >To detect CFid between cell x (victim) and cell y (aggressor)

CFid (y rise → x=0): w1x w0y w1y r1xCFid (y fall → x=1): w0x w1y w0y r0xCFid (y rise → x=1): w0x w0y w1y r0xCFid (y fall → x=0): w1x w1y w0y r1x

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S2CF: State Coupling Fault

State Coupling Fault (CFst): The coupled cell (victim) is forced to 0 or 1 if the coupling cell (aggressor) is in a certain stateThere is four possible CFst types:

< 0 ; 0 > < 0 ; 1 > < 1 ; 0 > < 1 ; 1 >To detect CFst between cell x (victim) and y (aggressor)

CFst (y=0 → x=0): w1x w0y r1xCFst (y=0 → x=1): w0x w0y r0xCFst (y=1 → x=0): w1x w1y r1xCFst (y=1 → x=1): w0x w1y r0x

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S2CF: Dynamic Coupling Fault

Dynamic Coupling Fault (CFdyn): The victim is forced to 0 or 1 if the aggressor cell has a read or write operationMore general case of the Idempotent Coupling Fault (CFid) because it can be sensitized by any read or write operationThere are four CFdyn faults<r0 ⎢w0;0> <r0 ⎢w0;1> <r1 ⎢w1;0> <r1 ⎢w1;1>

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S2CF: Write (read) disturb coupling fault

Write disturb coupling (CFwd): A cell is said to have a CFwd if a non transition write perform on the victim results in a transition when the aggressor is set into a logic stateThere are four types of CFwd faultsRead disturb coupling (CFrd): Two cells are said to have a CFrd if a read performed on the victim destroys the data stored in the victim if a given state is present in the aggressorThere are four types of CFrd faults

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S2CF: Incorrect read coupling fault

Incorrect read coupling fault (CFir): Two cells are said to have an CFir if a read performed on the victim returns the incorrect logic value when the aggressor is sent into a given stateThere are four types of CFir faults

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S2CF: Deceptive read disturb coupling fault

Deceptive read disturb coupling fault (CFdr):A cells is said to have an CFdr if a read performed on the victim returns the correct logic value and changes the content of the victim, when the aggressor is sent into a given stateThere are four types of CFdr faults

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Fault models: Bridging Faults (BF)

A short between cells or lines (2 or more)This is a bidirectional fault caused by logic level rather than a transitionTwo sorts of bridging faults (BFs) exist:

AND-type (ABF): the shorted cells/lines take the AND value of their fault-free values (four possible ABFs)OR-type (OBF): the shorted cells/lines take the OR value of their fault-free values (four possible OBFs)

Can be made equivalent to a number of linked CFs, i.e."Cell x is the victim of cell y" and "Cell y is the victim of cell x"The faults are linked. It is possible that they will hide each other.

To detect a BF, it might be necessary to write a certain pattern on adjacent memory cells, see checkerboard algorithm using (“010101…”) pattern.

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Pattern Sensitive (PSF)

The victim cell is forced to 0 or 1 if a certain number of neighbors show a particular patternThe PSF is the most general k-coupling fault with k=nWith the Neighborhood Pattern Sensitive Fault (NPSF), the

neighborhood is limited to all the cells in a single position surrounding the base cell

Equivalent to an N-coupling fault involving more than one aggressor (up to 8 adjacent locations)Extremely hard to detect

For each memory cell: the effect of all the possible combinations (28) of the adjacent cells should be tested.

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Neighborhood Pattern Sensitive (NPSF)

In practice two types of NPSF are usedThe type-1 NPSF with 4 neighborhood cells (north, west, south, east)The type-2 NPSF with 8 neighborhood cells

Base cellBase cellTypeType--1 1 neighborhood neighborhood cellcell

TypeType--11

Base cellBase cellTypeType--2 2 neighborhood neighborhood cellcell

TypeType--22

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Neighborhood Pattern Sensitive (NPSF)

Active NPSF (ANPSF):change of the base cell due to a transition in the neighborhood cellsEach base cell must be read in state 0 and in state 1, for all possible changes in the neighborhood pattern

Passive NPSF (PNPSF):the change of the base cell is impossible due to a certain neighborhood cells configurationEach base cell must be written and read in state 0 and in state 1, for all permutations in the neighborhood pattern

Static NPSF (SNPSF):The content of the base cell is forced to a certain state due to a certain neighborhood patternEach base cell must be read in state 0 and in state 1, for all permutations in the neighborhood pattern

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Dynamic Fault models: examples

Sense Amplifier (SA) Recovery FaultThe SA saturates after a long sequence of 0s or 1s

Write Recovery Fault (addressing fault in the decoder)

Write followed by a read/write to another location affects the previously accessed location

Detection needs At-Speed testing !!

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Single-Cell Dynamic Fault Models: Dynamic RDF, IRF and DRDF

Definition similar to the static Read Disturb Fault, Incorrect Read Fault and Deceptive Read Disturb Faults with an initial write follows by one or more read operationdRDF: A Cell is said to have a dRDF if a write followed by one or more read performed on the cell returns (on the last read) an incorrect value while changing the contents of the cell to the wrong valuedIRF: A Cell is said to have a dIRF if a write followed by one or more read performed on the cell returns (on the last read) incorrect value while keeping the correct stored value in the celldDRDF: A Cell is said to have a dDRRF if a write followed by one or more read performed on the cell returns (on the last read) the expected value while changing the contents of the cell to the wrong value

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Fault models: Data Retention (DRF)

A cell fails to retain its logic value after some timeDue to a defective pull-up within a SRAM cellA cell loses its value due to leakage current: the cell lose its charge due to this leakage currentTwo different DRFs exist (loss of 1 and loss of 0) and may coexistTo detect DRF => a delay has to be inserted before reading back memory content (usually ~ 10-100 ms)Can be easily add to any test algorithmTest time increase dramatically !

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Fault models: linked faultsLinked faults are two or more faults (coupling faults) that affect the same cell

Can be of the same type ( i.e. CF x->y and CF z->y )or of different types ( i.e. CF x->y and TFrise y )They can hide each other (fault masking): Extremely difficult to detect

ii jj kk ll ii kk ll

<<↑↑;1>;1>

<<↑↑;0>;0> <<↑↑;0>;0><<↑↑;1>;1>

2 CF2 CFidid faultsfaults 2 CF2 CFidid linked faultslinked faults

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Relation between functional faults and fault models

SAFSAF

CF

Shorts between data linesCrosstalk between data lines

TFTFCell can be set to 0 and not to 1 (or vice versa)

AFAF

Address line stuckAddress line stuckOpen in address lineOpen in address lineShorts between address Shorts between address lineslinesOpen decoderOpen decoderWrong accessWrong accessMultiple accessMultiple access

Cell stuckDriver stuckRead/write line stuckChip-select line stuckData line stuckOpen in data line

NPSFPattern sensitive interaction between cells

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Relation between functional faults and fault models (examples)

Vss

WL

BL BL

Vdd

11

2233

44

55 66

77

1, 2, 3: SA04: AF for cells after the open5, 6: State Coupling Faults7: SAF (depending on the cell content and the technology)

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Dynamic Read Destructive Faultin the Core Cell [ETS04]

Defect 1Defect 1

Defect 1 involves a dynamic Defect 1 involves a dynamic Read Destructive FaultRead Destructive Fault

I / O DATAI / O DATA

R O

WR

O W

DEC

OD

ERD

ECO

DER

MEMORYMEMORY

ARRAYARRAY

C O L U M NC O L U M N

D E C O D E RD E C O D E R

Tn3Tn3

Tn2Tn2

Tn1Tn1

Tp2Tp2

Tp1Tp1

SS SBSB Tn4Tn4

WLWL

BLBBLBBLBL

~2000

~100

~25

~3

~8

~130

Min Res(kΩ)

TF6

IRF; TF5

TF4

RDF; DRDF3

RDF; DRDF2

dRDF1

Fault ModelDefect

Defect 1Defect 1

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Memory Built-In Self-Testing

DefinitionsCell TransitionsBasic Built-In-Self-Test ArchitectureSummary

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Definitions

Concurrent BIST – Memory test that happens concurrently with normal system operation

Transparent testing – Memory test that is non-concurrent, but preserves the original memory contents from before testing began

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Functional TestingGalpat Algorithm

1. Solid all 0 (1) pattern is written to all N cells2. For each cell C(j):

• Complement C(j)• Repeat the following sequence for k not equal to j

• Read C(j)• Read C(k)

• Restore the contests of C(j)

Looks like a sliding 1 across the arrayRequires N write operationsFor each iteration of step 2 C(j) is complemented

twiceThere are 2(N-1) read operations

Total number of operation is:N+ N[2+2(n-1)] = N+N(2N+1)

Since test is repeated for array initialized to 1,total test time is T = 2(2N2 +N)

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Marching TestSpecial version of walking 1/0 – minimizes excessive reading operations.March-C Test

Solid 0 pattern places in RAM. Contents read in ascending order.Check made to assert that content of each cell C(j) is 0 and then a 1 is written in the locationProcess repeated until all 1’s are written on all cells. The cells are then read in descending order to verify that they contain 1’sThe 1’s are then changed to 0’s

Requires 11 read/write operations. Test time is T = 11NDetects faults on decoders, transition faults (since it verifies that the cell can undergo transitions from 1 to 0 and vice versa), and some coupling faults

Variations like March C- and March C+ reduce operation times or add coverage (stuck-opens and some timing faults)

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Marches and Backgrounds

1 0 1 00 1 0 11 0 1 00 1 0 1

(d)

0 0 0 10 0 1 10 1 1 11 1 1 1

(b)

0 0 0 10 0 1 00 1 0 01 0 0 0

(a)

1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 10 1 0 0 0 0 1 0 0 0 0 1 1 0 0 00 0 1 0 0 0 0 1 1 0 0 0 0 1 0 00 0 0 1 1 0 0 0 0 1 0 0 0 0 1 0

(c)

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Memory Bist

deco

der

MemoryCell

Good/No-good

MA

R

decoder

MDR

DataGenerator

Address

Compactor &Comparator

Control &Timing

AddressCounter

Test/NormalClk

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MBIST ArchitectureMBIST insertion: after

MBISTController

Array

backgrounddata generator

comparator

BIST fail register

pass/fail

arraydata in

arraydata out

Bist_en

Bist_en

Bist_en

addressgenerator

system R/Wcontrol R/W

control

Addrsystem address

data insystem

JTAG

clock, resetetc.

Slave

Master

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LFSR and Inverse Pattern LFSR

NOR gate forces LFSR into all-0 stateGet all 2n patterns

Normal LFSR:G (x) = x3 + x + 1

Inverse LFSR:G (x) = x3 + x2 + 1

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Up / Down LFSRPreferred memory BIST pattern generator

Satisfies March test conditions

X0

D Q MUX

0

1

MUX

0

1

MUX

0

1 D Q D Q

MUX

0

1

X1 X2

Up/Down

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Up / Down LFSR Pattern Sequences

Up Counting000100110111011101010001

Down Counting000001010101011111110100

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Mutual ComparatorTest 4 or more memory arrays at same time:

Apply same test commands & addresses to all 4 arrays at same timeAssess errors when one of the di (responses) disagrees with the others

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Mutual Comparator SystemMemory BIST with mutual comparator

Benefit: Need not have good machine response stored or generated

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SummaryBIST is gaining acceptance for testability insertion due to:

Reduced chip area overhead (only 1-3 % chip area for memory BIST)Allows partitioning of testing problem

Memory BIST – widely used, < 1 % overheadRandom logic BIST, 13 to 20 % area overheads

Experimental method has only 6.5 % overheadUsed by IBM and Lucent Technologies in selected products

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SUMMARY

IntroductionMemory modelingFailure mechanisms and fault modelingTest algorithms for RAM

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Test Algorithms: notation used

↑ : indicates address ascending order

↓ : indicates address descending order

w0 : write 0 at current location

w1 : write 1 at current location

r0 : read current location, expecting a 0

r1 : read current location, expecting a 1

(….): algorithm element

{(…),(…),…,(…)}: full algorithm

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Test algorithms

Full Behavioral test is definitively too consuming (3.n.2n)Classical and early memory testing methods with test time proportional to

n (zero-one, checkerboard, …)n2 and n.log2(n) (walking1/0, ping-pong, Galpat, Galcol, …)

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Test algorithm: Zero-One

This minimal test consists of writing 0s and 1s in the memory

Step1: write 0 in all cellsStep2: read all cells (0 expected)Step3: write 1 in all cellsStep4: read all cells (1 expected)

O(n) testFault coverage:

Not all AFs detectedSAFs detected if the adress decoder is fault freeNot all TFs and CFs detected

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Test algorithm: Checkerboard

Cell are divided in two groupsStep1: write 1 in all green cells and 0

in pink cellsStep2: read all cellsStep3: write 0 in all green cells and 1 in pink cellsStep4: read all cells

O(n) testFault coverage:

Not all AFs detectedSAFs detected if the address decoder is fault freeNot all TFs and CFs detected

This test is able to detect bridging faults

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Test algorithms: GALPAT and Walking 1/0

Memory is filled with 0s (or 1s) except for the base-cell which contains a 1 (0)During the test the base cell walks through the memoryDifference between GALPAT and W 1/0 is in reading the base cell

0 0 →→ 0 0 →→ 0 0 →→ 00

0 1 0 0 1 0 →→ 00

0 0 →→ 0 0 →→ 0 0 →→ 00

Walking 1/0Walking 1/0

0 0 0 0 0 0

0 1 00 1 0

0 0 00 0 0

GALPATGALPAT

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All AFs are detected and locatedAll SAFs are detected and locatedAll TFs are detected and locatedAll CFs are also detected and locatedBut both are O(n2) testsother tests have been proposed as a shorter alternative 0(n3/2):

Sliding diagonalButterfly (only neighborhood cells of the base cell are read)GALCOL

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All AFs are detected and locatedAll SAFs are detected and locatedAll TFs are detected and locatedAll CFs are also detected and locatedBut both are O(n2) testsother tests have been proposed as a shorter alternative (0(n3/2):

Sliding diagonalButterfly (only neighborhood cells of the base cell are read)GALCOL

1 0 0 0 00 1 0 0 00 0 1 0 00 0 0 1 00 0 0 0 1

0 0 1 0 00 0 0 1 00 0 0 0 11 0 0 0 00 1 0 0 0

0 1 0 0 00 0 1 0 00 0 0 1 00 0 0 0 11 0 0 0 0

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Test algorithms test time

Number of operations

n n n.log2n n2 (hr!!)

1Mb 0.063 1.26 18.33

16Mb 1.01 24.16 4691.3

256Mb 16.11 451 1200959.9

2Gb 128.9 3994.4 76861433.7

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Test algorithms test time

Number of operations

n n n.log2n n2 (hr!!)

1Mb 0.063 1.26 18.33

16Mb 1.01 24.16 4691.3

256Mb 16.11 451 1200959.9

2Gb 128.9 3994.4 76861433.7

8774 Years !!8774 Years !!

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March tests

The test is "marching" through the memory

The test is composed of March elements represented between ()

March tests are the simplest tests (optimal ?)to detect most of the functional faults

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March tests: example of MATS++

{↑(w0); ↑(r0,w1); ↓(r1,w0,r0)}

For i=0 to n-1Write 0 in cell Ci

For i=0 to n-1Read cell Ci and check its content (0 expected)Write 1 in cell Ci

For i=n-1 to 0 Read cell Ci and check its content (1 expected)Write 0 in cell CiRead cell Ci and check its content (0 expected)

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Testing of Neighborhood Pattern-Sensitive Faults

Active NPSF (ANPSF):Each base cell must be read in state 0 and in state 1, for all possible transitions in the neighborhood pattern(k-1).2k possible patterns, (type-1: k=5, type-2: k=9)

Passive NPSF (PNPSF):Each base cell must be written and read in state 0 and in state 1, for all permutations in the neighborhood pattern2k possible patterns

Static NPSF (SNPSF):Each base cell must be read in state 0 and in state 1, for all permutations in the neighborhood pattern2k possible patterns

M. d’Abreu 81


It is essential to minimize the number of writes during NPSF testing

SNPSF patterns are produced following an Hamiltonian sequence (Hamiltonian distance of 1 between patterns, Gray code for example): k+2k-1 writes

ANPSF and PNPSF patterns are produced following an Eulerian sequence : k+k.2k

writes

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Number of writes further reduced by testing the neighborhoods simultaneously

Tilling method: number of Tilling method: number of writes divided by kwrites divided by k

TwoTwo--group method (typegroup method (type--1 1 only): number of writes only): number of writes divided by 4divided by 4

Ba

bdc

Group 1Group 1 Group 2Group 2

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Basic NPSF location algorithm

write base-cells with 0;loop

apply a pattern; {it could change the base-cell from 0 to 1}

read base-cell;endloop;write base-cells with 1;loop

apply a pattern; {it could change the base-cell from 1 to 0}

read base-cell;endloop;

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Basic NPSF detection algorithmwrite base-cells with 0;loop

apply a pattern; {it could change the base-cell from 0 to 1} read base-cell;

endloop;write base-cells with 1;loop

apply a pattern; {it could change the base-cell from 1 to 0}endloop;read base-cell;

Only valid for ANPSF or SNPSF for which no transition is Only valid for ANPSF or SNPSF for which no transition is needed in the base cellneeded in the base cellTilling method cannot be used as base cells are changingTilling method cannot be used as base cells are changing

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NPSF testing algorithm summary

Fault coverageNPSFSAF TF

A P STDANPSF1G N L D 163.5 n

TLAPNPSF1G Y L L L L L 195.5 nTLAPNPSF2T Y L L L L 5122 nTLAPNPSF1T Y L L L L 194 nTLSNPSF1G Y L L 43.5 nTLSNPSF1T Y L L 39.2 nTLSNPSF2T Y L L 569.8 nTDSNPSF1G N L D 36.125 n

Operation count

Algorithm Location

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Operation count

Algorithm LocationDDetection etection

or or LLocationocation

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Operation count


or or LLocationocationAActivectivePPassiveassiveSStatictatic

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Operation count


or or LLocationocationAActivectivePPassiveassiveSStatictatic

typetype--11oror

typetype--22TTilling or illing or 22--GGroup roup methodmethod

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Test Time Complexity (100MHz)

Size N 10N NlogN N1.5 N2

1M 0.01s 0.1s 0.2s 11s 3h

16M 0.16s 1.6s 3.9s 11m 33d

64M 0.66s 6.6s 17s 1.5h 1.43y

256M 2.62s 26s 1.23m 12h 23y

1G 10.5s 1.8m 5.3m 4d 366y

4G 42s 7m 22.4m 32d 57c

16G 2.8m 28m 1.6h 255d 915c

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Classical Test Algorithms

Checkerboard AlgorithmZero-one algorithm with checkerboard patternComplexity is 4NFor SAF and DRF

1 0 10 1 01 0 1

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Classical Test AlgorithmsGalloping Pattern (GALPAT)

Complexity is 4N**2---only for characterizationAll AFs,TFs, CFs, and SAFs are located

1. Write background 0;2. For BC = 0 to N-1

{ Complement BC;For OC = 0 to N-1, OC != BC;

{ Read BC; Read OC; }Complement BC; }

3. Write background 1;4. Repeat Step 2;

BC

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Sliding (Galloping) Row/Column/DiagonalBased on GALPAT, but instead of a bit, a complete row, column, or diagonal is shiftedComplexity is 4N**1.5

11

11

1

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Classical Test AlgorithmsButterfly Algorithm

Complexity is 5NlogN

1. Write background 0;2. For BC = 0 to N-1

{ Complement BC; dist = 1;While dist <= mdist /* mdist < 0.5 col/row length */

{ Read cell @ dist north from BC;Read cell @ dist east from BC;Read cell @ dist south from BC;Read cell @ dist west from BC;Read BC; dist *= 2; }

Complement BC; }3. Write background 1; repeat Step 2;

6

1

9 4 5,10 2 7

3

8

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Classical Test AlgorithmsMoving Inversion (MOVI) Algorithm [De Jonge & Smeulders 1976]

For functional and AC parametric testFunctional (13N): for AF, SAF, TF, and most CF

Parametric (12NlogN): for Read access time

,1();1,1,0();0,0,1();1,1,0();0({ rrwrrwrrwrw ⇓⇓

– 2 successive Reads @ 2 different addresses with different data for all 2-address sequences differing in 1 bit

– Repeat T2~T5 for each address bit– GALPAT---all 2-address sequences

)}0,0 rw⇑⇑⇓

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Classical Test AlgorithmsSurround Disturb Algorithm

Examine how the cells in a row are affected when complementary data are written into adjacent cells of neighboring rows

1. For each cell[p,q] /* row p and column q */{ Write 0 in cell[p,q-1];

Write 0 in cell[p,q];Write 0 in cell[p,q+1];Write 1 in cell[p-1,q];Read 0 from cell[p,q+1];Write 1 in cell[p+1,q];Read 0 from cell[p,q-1];Read 0 from cell[p,q]; }

2. Repeat Step 1 with complementary data;

1

0 0 0

1

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Zero-one and checkerboard algorithms do not have sufficient coverageOther algorithms are too time-consuming for large RAM

Test time is the key factor of test costComplexity ranges from N2 to NlogN

Need linear-time test algorithms with small constants

March test algorithms

memory test updated v3 reduced

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