Metal Bonding Alternatives to Frit and Anodic Technologies forAdvanced Wafer Level Packaging

James HermanowskiOctober 2010

2

Overview

Overview of frit and anodic bond processingMechanics of metal bonding optionsProcess requirement comparisonsHermetic capabilitiesEquipment requirements for metal bondingSummary

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Expanding CE (consumer electronics) market drives the Semiconductorinnovation

Push for integrationReduction in power consumptionSmaller form factor

Image sensors and memory stacking (for mobile applications) are two massvolume applications for TSVs with close time-to-market

1980‘s1950‘s TodayEnabling new devices

Advanced Wafer Level Packaging

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Fusion / Adhesive Bonding

Lithography, Adhesive Bonding

CM

OS

Imag

e Se

nsor

CMOS Image Sensor Integration (BSI)

CMOS Image Sensor Packaging

Wafer Level Optics Assembly Imprinting, UV Bonding

Kodak / Intel / Samsung

Mem

ory

Stac

king

DRAM

FLASH

NAND

Metal to Metal Bonding

Fusion bonding

Adhesive Bonding

SUSS Equipment for Advanced WLP and 3D-IC

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Materials and Process – Anodic Bonding

Anodic Bond Materials – thermal matchingGlass (sodium silicate) (8.6 x 10-6/°C)Pyrex (borosilicate) 3.25 x 10-6/°C)Si (2.6 x 10-6/°C)Spin-on glass or magnetron sputtered glasses, SOI

Smooth and clean surfaces needed for best hermetic sealingMechanical strength, ability to withstand stress

Anodic Bond Process ParametersTemperature 300+ to 450C, some research at room temperature

Lower is better for throughput, warpage, etc.Glass dependent, ion mobility important

Voltage 400V to 1000+V, 800V typical, up to 2000V possibleCurrent, maximum allowable 15mA up to 60mABond force used to hold wafers together, non-critical parameter

500N to 1000N normal

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-

+

Na+

Si+

Anodic Bonding - Theory

The Na and O ions are diffusing due to the thermal energy. Due to the applied voltage the direction of the diffusion is controlled.It is necessary to apply a negative voltage (e.g. –800Volts) on the cathode, to attract the Na+ ions. Without Na+ diffusion there is little current. The “holes” created by the Na+ diffusion leaves bonding sites on the glass lattice for the Si to occupy and bond with the glass (forming SiOx). Silicon is also positive and directed towards the interface by the bias conditions.SUSS triple stack allows user to program third electrode

Program

Grounded

Na+

+

Na+

Normal anodic bond

Triple stack anodic bond

Programmable control to

allow different process

conditions at each bond

Vacuum bond

Overpressure

bond

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Terminating the Bond Process

Three common optionsTime basedCharge basedCurrent decay based – best for production, ~20% of initial current

This is the best way to terminate the process.

This is also the best way to develop a process.

Time scale shows how each process begins to terminate

close to each other.

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Issues Encountered – Anodic Bonding

Metal ions onglass wafer

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Materials and Process – Frit Bonding

Frit Bond Materials –Frit glass materialClean surfaces needed for best hermetic sealingMechanical strength, ability to withstand stress

Frit ProcessUsually frit is screened onto wafers – a dirty processFrit must be fired after screen print to remove organics and convert it to glassy material

Frit Bond Process ParametersTemperature 400 to 450C, specific frit dependentBond force used to hold wafers together, less critical paramete

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Issues Encountered with Frit Bonding

Alignment shiftingContamination from screening processNon-planar frit coatings can damage CMOS wafer when force is applied

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Process Comparisons: Anodic, Frit, Metal

Silicon

Glass

Silicon

Silicon

Silicon

Glass

Silicon

Silicon

Silicon

Silicon

Silicon

Silicon

Ano

dic

Gla

ss F

ritM

etal

Initial Substrates

Bonded Substrates

Die Packaged

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10 um Glass seal will remain 10 um Glass seal will remain hermetic for ~1yr.hermetic for ~1yr.

10 um Metal seal will remain 10 um Metal seal will remain hermetic for ~100yrs.hermetic for ~100yrs.

1 um Metal seals will remain 1 um Metal seals will remain hermetic for years.hermetic for years.

Hermeticity, Low Temperatures & Smaller Die Drive Metal Bonding Schemes

Polymers = 10-6 cc/secGlasses = 10-10 cc/secMetals = 10-16 cc/sec

Permeation rates

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Metal Bonds Enable Better Performance and Scaling

121233338989385385Max Added Die/wfr (100Max Added Die/wfr (100µµm > 2 m > 2 µµm)m)

113181351Max Added Die/wfr (100µm > 10 µm)

<1%1%1%1%10µm wide Seals

1%1%2%3%25µm wide Seals

2%3%4%6%50µm wide Seals

4%5%7%12%100µm wide Seals

% Surface Area Consumed by Seals

10753Die Size (mm x mm)

Assumes 200mm wafer, 3mm EE, 375µm dicing street

• Over 300 Additional Die from Seal Ring Geometry Reduction

• Device Scaling (due to better hermeticity) adds additional die.

• e.g. 7mm→5mm die size adds > 500 die

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Requirements for Diffusion BondingProper materials system: Rapid Diffusion at Low Temperature

Same crystal structure bestMinimal size differenceHigh SolubilityHigh mobility and small activation energy

Diffusion Barriers to protected regionsHigh Quality films - No contamination or OxideIntimate Contact between surfaces

Process VariablesHeatPressureGas AmbientProcess Vacuum levels

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Complete Solid Solubility

• Both Cu and Ni are FCC crystals• ρ(Cu)=8.93 gm/cm3

• ρ(Ni)=8.91 gm/cm3

• Lattice Spacing a0(Cu)=3.6148Å• Lattice Spacing a0(Ni)=3.5239Å

Copper (Cu) - Nickel (Ni)

αα

liqliq

CuCu NiNi

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Microstructure DevelopmentInterface Properties

1. Generally retain elastic properties of noble metals.

2. Resistivity usually obeys Vegard’s rule - linear with % atomic concentration of mix.

3. Full layer diffusion not needed.

4. Adhesion layers may be needed for initial substrate deposition process.

5. Diffusion barrier may be incorporated with adhesion layer to prevent diffusion into substrate.

6. Wetting agents between A & B layers assists in initialization of diffusion.

Silicon

Silicon

Metal A (Ni)

Metal B (Cu)Fully mixed with

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Diffusion Bonding

1. The mechanical force of the bonder establishes intimate contact between the surfaces. Some plastic deformation may occur.

2. During heating the atoms migrate between lattice sites across the interface to establish a void free bond. RMS <2-5 nm required.

3. Vacancies and grain boundaries will exist in final interface area. Hermeticity is nearly identical to a bulk material.

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Diffusion Pathways in Crystals: Poly vs Single

Single Crystalline Fine Grain Poly-Crystalline

Dsurface > Dgrain.boundary > Dbulk

Course Grain Poly-Crystalline

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Type A Kinetics: Rapid Bulk Diffusion Rates

In Type A kinetics the lattice diffusion rates are rapid and diffusion profiles overlap between adjacent grains.

gbgb gbgb gbgbgbgbbulk bulk bulk

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In type B kinetics the grain boundary is isolated between grains. Behavior mimics bulk diffusion. Diffusion is by both grain boundaries and bulk atomic motion. Dominate pathways are related to grain size and density.

Type B Kinetics: Normal Bulk Diffusion w/ GB Effect

gbgb gbgb gbgbgbgbbulk bulk bulk

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In Type C kinetics the lattice diffusion rate is insignificant

and all atomic transport is dominated by grain boundary diffusion only For example room temperature diffusion.

Type C Kinetics: Insignificant Bulk Diffusion

gbgb gbgb gbgbgbgbbulk bulk bulk

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6420

-6-4-2

6420

-6-4-2

2 40 6 8 10 12

6420

-6-4-2

2 40 6 8 10 12

Log

[1/g

.s.(c

m) ]

Log ρd (cm-2) Log ρd (cm-2)

Log

[1/g

.s.(c

m) ]

T/Tm = 0.3T/Tm = 0.4

T/Tm = 0.6 T/Tm = 0.5

gbgb

gbgbgbgb

gbgb

ll ll

ll ll

dddd

dddd

• Regimes of grain size (g.s.) and dislocation density ρdover which (l) lattice diffusion, (gb) grain boundary diffusion of (d) dislocation diffusion is the dominate mechanism for atomic motion.

• All data is normalized to the melting point and applies for a thin film fcc metal at steady state.

• Shaded area is typical of thin film dislocation density 108

to 1012 lines/cm2.

Low Temperature Diffusion Relies on Defects

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164°C8.5e-131.5e-22210°C7.8e-121.4e-20268°C7.5e-111.4e-18444°C3.7e-91.8e-18

Temperature Dgb (cm2/sec)Dl (cm2/sec)

Gold Lattice and Grain Boundary Diffusivities6420

-6-4-2

2 40 6 8 10 12

Log

[1/g

.s.(c

m) ]

Log ρd (cm-2)

gbgb

ll dd Grain Boundary Diffusion Distance (um)

0

5

10

15

20

25

30

35

0 10 20 30 40 50Time (minutes)

Diff

usio

n D

ista

nce

(um

)444C268C210C164C

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Metal Bonding Options

ReactionType

Metal †Bond Temp Oxidizes CMOS Compatible

Cu-Cu >350°C No YesAu-Au >300°C Yes NoAl-Ge >419°C No YesAu-Si >363°C Yes No

Au-Ge >361°C Yes NoAu-Sn >278°C No NoCu-Sn >231°C No Yes

†Eutectic bonds are done ~15°C above the listed eutectic tempereature. Diffusion bonds lower limit expressed.

Diffusion

Eutectic

CMOS compatibility –barrier layers are often used to prevent metal migration to the CMOS structure.

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Key Different Requirements for Metal Bonds

Surface roughness is important to allow the metal surfaces to come into intimate contact, especially for diffusion bondingMetal oxide formation can prevent strong bond formation

Preventive actions and process controls need to be establishedForce requirements are much tougher

Structural issues with bond chamber will become much more apparent during metal bondingFor example, the chamber shape may change with the application of high heat and force causing unbonded areas to form in the devices

Temperature controls will be pushed harderTo obtain the tighter overlay possible with metal bonding, it isimportant to control both wafers to tight temperature tolerancesTo prevent oxide formation, it is more desireable to load wafers at lower temperatures into the bond chamber

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Gold-Gold bond at 300°C for 30 min. Au layer is 350nm, Cr is 50nm thick

0.5μm

AuAu

AuAu

CrCr

CrCrSiSi

SiSi

InterfaceInterface

0.5μm

AuAu

AuAu

CrCr

CrCrSiSi

SiSi

InterfaceInterface

Surface roughness is important

to maintain intimate contact and

good bonds.

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Thin (400nm) Cu/Cu bonds at 300°C for 30 min.

1μm

Si

Si

Cu

Cu

Interface Interface

1μm1μm

Si

Si

Cu

Cu

Interface Interface

Ultra smooth surfaces allow

better molecular intermixing

and deliver good bond quality

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SUSS Coater for 3D Packaging

Main ApplicationsRedistribution Layers (RDL)

Main Market: Memory and WLCSPfor memory center to edge rerouting, mainly for wire bonded stacksInverse to typical WLCSPs -> edge to center for best distribution & lowest DNP (distance to neutral point) -> lowest stress for direct board attach

Redistributed Chip PackagesWafer level (or better “substrate level”) package formationFan-out option (contact grid larger than die size)Cheaper (parallel) package formation (encapsulation)Well suited for POP applications

Image Sensor IntegrationVia contact from the back

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SUSS Aligner for 3D Packaging Applications

CIS (Image sensor packaging)Back Side Alignment, Infra-Red Alignment, Warped Wafer Handling, high topography lithography

Memory StackingResolution for TSV manufacturing, Infra-Red Alignment, RDL with tight overlay control, tight CD control

WLP of Optical Devices UV-Bonding, Micro lens imprinting

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SUSS Bonders for 3D Packaging Applications

CIS – CMOS Image Sensors CMOS Image sensor Packaging and Integration (BSI)Wafer Level Optics Assembly

Memory Stacking

Memory to Logic Integration

Mixed Signal/Analog to Digital Integration

Die to Wafer Stacking

Wafer to Wafer Stacking Source: OmniVision Technologies

Equipment for Permanent & Temporary Bonding for Advanced WLP

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Permanent BondingCu-Cu Bonding

Polymer / Hybrid Bonding

Fusion Bonding

Temporary Bonding/De-bonding capability

Thermoplastics Process (eg. HT10.10)

3M WSS Process

Dupont / HD Process

Thin Materials AG (TMAT) Process

Total Process Flexibility for 3D Applications

XBC300 Standardized Platform

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XBC300 Configuration Examples

SC300For

adhesive coating

Module 3

PL300

(TMAT)Laser

moduleDB300

Tape onframe

LF300SC300

for cleaning(optional)

Temporary Bonding De-bonding

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True Modular Design

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True Modular Design

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True Modular Design

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True Modular Design

True Modular Design

Lowers investment riskIdeal for changing technology requirements

Lowers COOSmall footprint, high throughput

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BA300UHP Aligner

CB300 Bonder

CP300 Cool Plate

SC300 Spin Coater

PL300T Surface Prep

LF300 Low Force Bonder

DB300 Debonder

Temporary Bonding

Permanent BondingCL300 Wafer Cleaning

PL300 Plasma Activation

Process Flexibility: Complete Line of Process Modules

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Permanent Bonding Configurations

BA300UHP

Aligner

CB300

Bonder

CP300

Cool Plate

Fusion Bond Configuration Cu-Cu and Polymer Bond Configuration*

BA300UHP

Aligner (if alignment

with keys required)

PL300

Plasma Activation

CL300

Wafer Cleaning

*Optional Die to Wafer Collective Bonding

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Permanent Bond Configurations

BA300UHP Bond Aligner – submicron alignment accuracyCB300 Bond Chamber – temperature & force uniformityCP300 Cool Plate – controlled cool rate

*Optional Die to Wafer Collective Bonding

Cu-Cu and Polymer Bond Configuration*

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Sub Micron Alignment AccuracyPath to 350nm PBA for Cu-Cu bondingPath to 150nm PBA for Fusion bondingISA alignment mode for face to face alignmentAllows smaller via diameters and higher via densities

Built in Wedge Error Compensation (WEC) to make upper and lower wafers parallel prior to alignment

Eliminates wafer shift during wafer clamping

Closed loop optical tracking of mechanical movements

Void free bonding in the BA with RPP™Patent pending RPP™ creates an engineered bond wave for propagationEliminates need for bond module

BA300UHP Bond Aligner Module

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Fusion Bonding in the BA300UHP

Wafers are loaded and vacuum held against SiC chucks

Chucks and the vacuum or pressure, that can be controlled between the chuck and the backside of the wafer, “engineers” the shape of the bonding surface

The chucks are used to align and bring the wafers into contact

The chucks are also used to engineer the bond wave from center to edge using RPP (Radial Pressure Propagation).

Click icon forRPP Presentation

XBC300 Wafer Bonder RPP (Radial Pressure Propagation)

in the BA300UHP Aligner Module

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Si C Chuck & Tool Fixture (Patent Pending)

Transports aligned pair from BA300 to CB300

Delivers reproducible submicron alignment capabilities

Maintains wafer to wafer alignment throughout all process and transfer steps

No exclusion zone required for clamping

Maintains alignment accuracy through temperature ramp

Chuck CTE matches Si CTE

Increases throughput by reduction of thermal mass

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CB300 Bond Chamber ModuleProduction Requirement Closed Bond ChamberContamination Free

Open chamber lid introduces air-turbulence and particles into bond chamber

Uniform heatOpen chamber lid causes temperature gradient between the front and back

3 Post Superstructure takes force, not bond chamber

Chamber lid is the structural force carrying element in clam shell design–this causes force distortion

SafetyOpening chamber lid exposes user to high temperatures

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CB Chamber Force Uniformity

Excellent Force UniformityWithin ±5% pressure uniformityPatented Pressure Column Technology for up to 90kN of bond forceLoad Cell VerificationBond Force options

Standard: 3kN to 60kNHigh Force Option: 3kN to 90kN

Traditional PistonTraditional Piston

Bond-Interface

SUSS Pressure Column TechnologySUSS Pressure Column Technology

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CB Chamber Thermal Design

Superior Thermal PerformanceWithin ±1.5% temperature uniformityFast ramp (to 30°C/min) and cool rate (to 20°C/min)Matched top and bottom stack assemblies

Perfect symmetryMulti-zone, vacuum-isolated heaters

Dramatically reduces hot spots and burnoutsEliminates edge effects

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CB Chamber Structural Design

Best-in-Class Post Bond Alignment

±1.5µm post bond alignment for metal bonds

Rigid superstructureSolid alignment stability

High planarity silicon carbide chucksMaintains long term planarity for superior post-bond alignment accuracy

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CP300 Cool Plate Module

Fixture and wafer coolingUnclamp, unload, and optional fixture load

Queuing and buffer station for fixtures and wafers

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CL300 Wafer Cleaning Module for Fusion Bonding

Wet spin process for wafer cleaning

Twin ultrasonic headIR Assisted DryingNH4OH chemistry

Simultaneous clean, mechanical align and bond two wafers

Bond initiation integrated into CL300

Closed process chamber for maximum particle protection

Rated for particle sizes down to 100nm

Design based on CFD(computational fluid dynamic) modeling

Example of KLA data w/ no adders down to 100nm

CFD modeling of chamber

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PL300 Plasma Activation Module for Fusion Bonding

Cleaning & surface conditioning for fusion bonding

Simple operation with plasma activation times in <30 seconds

Enables high bond strength at low annealing temperatures

Vacuum chamber based plasma system

Uniform glow plasmaPower supply options for frequency and power level

Ex: 100kHz/300W; 13.56MHz; 2.4GHzAutomatic tuningInput gases with up to 4 MFCsRadially designed high conductance plenum and vacuum system

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Summary

Anodic and Frit based bond processes are not suitable for advanced wafer level packaging processes

Challenges with mobile ions (anodic) and footprint, accuracy (frit)Metal bonding processes are being implemented as the next generation solutionAlthough metal bonding processes have many advantages over frit and anodic approaches they also require much more from the process equipment

For example much more stringent specs for force and thermal controlProcess equipment proven to satisfy these requirements has been presented