methods for access verification of dramdevices by ... · pdf file12/2/2009 ·...

© GOEPEL electronic 2009

Methods for Access Verification of

dRAM devices by Emulation Test

Presenter: Jan Heiber ([email protected])

TEST FORUM 2009Dec 1-2, 2009, Stockholm, Sweden

12/2/2009 2NTF 20091 2 3 4


1

2

3

Intro – dRAM Test Problems

Emulation Test: top or flop?

Available System Solutions

Presentation contents

4 Summary and Outlook

1 2 43

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Facts on RAM Access Testing by BScan

Boundary Scan is well proven for access test of Memories

Access to all Memory signals from Boundary Scan side needed

ATPG Tools enabling predictive test coverage calculation

Automated Pin Failure Diagnostics for static detectable faults

Use of special Library Models to describe Memory access behaviour

RAM banks can typically be tested on the base of individual chip activation

AccessSignals

Background Information

1

Address

TAPControl

DataRAM

BScan

IC

IEEE1149.1 Signals

12/2/2009 4NTF 20091 2 3 4


Fault Coverage trends via IEEE 1149.1

Fault coverage for Memory Access on modern boards via IEEE1149.1 has been declining continuously for several years.

This is caused by use of modern DRAM‘s

200x199x 201x

Average real world BScan Fault coverage Quality for Memory Access

Critical Trend

Situation

Fau

lt c

overag

e

1

12/2/2009 5NTF 20091 2 3 4


Searching for answers…

Current Test Problems

1

DRAM devices getting continuously higher data rates (DDR2, DDR3…)

Routing of DDR signals during layout is critical to avoid skews (Design Errors)

Boundary Scan is to slow to keep the necessary vector rate

Some processors don‘t have BScan on the Memory Bus pins anymore

Missing access to all Memory signals or non controllable clocks

New Standard IEEE 1581 could solve the problem but is not available yet

12/2/2009 6NTF 20091 2 3 4


Some thoughts …

Conclusions

BScan test becomes difficult due to the increased speed of the memory chips

Key challenge is to keep a deep test coverage also for high dynamic structures

Features like predictive fault coverage, ATPG and pin level diagnostics are needed

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12/2/2009 7NTF 20091 2 3 4


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Where is the future?


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12/2/2009 8NTF 20091 2 3 4


BScan Test versus Emulation Test

JTAG Emulation Test

2

Boundary Scan Test

• Static pin electronics • BScan cells define vectors• Serially controlled pin interface • Scalable number of pins• Arbitrary static signal timing• Arbitrary vector definition per pin

• Dynamic pin electronics• µP defines vectors• Parallel controlled pin interface• Fixed number of pins• Rigid dynamic signal timing• just Address / Data bus controllable

12/2/2009 9NTF 20091 2 3 4


Interconnection of µP Core and DRAM

On-Chip Resources

JTAG TAP

µP Core

Embedded Flash

Complex Bus I/F

Legacy Bus I/F

Legacy I/O PortsSystem Bus I/F

External Bus Devices

Flash Components

SRAM / DRAM

Peripheral I/O Ports

Peripheral Bus I/F

Aux Resources

Control Hardware

Control Hardware

Test Access ready by design

No special DfT rules necessary

Free running clocks: no issue

Real Time functional Test

Advanced structural emulation Test methods possible

Pro‘sPro‘s

2

12/2/2009 10NTF 20091 2 3 4


New methods by emerging standards

Address

Control

DataDRAM

IEEE1149.1 / IEEE1687 Access

IEEE P1581IEEE P1687

IEEE1687 controlled Test Instrument (IP)

Access Verification of DRAM by embedded Test Instrumentation

compliant to IEEE1687

Access Verification of DRAM by embedded Test Instrumentation

compliant to IEEE1687

Address

Control

Data

IEEE1149.1 Access

IEEE1581 compliant Device

Access Verification of DRAM by Boundary Scan in conjunction

with IEEE1581 activation

Access Verification of DRAM by Boundary Scan in conjunction

with IEEE1581 activation

TAP TAP

BScan

IC

IEEE1581 Access

DRAM

2

12/2/2009 11NTF 20091 2 3 4


Progress with handicaps …

Conclusions

Emulation Test offers the needed test speed but has limits driving control signal

Achievable Fault coverage is identical to BScan Test but diagnostics quality is lower

Need for System solutions to support advanced Emulation Test and emerging standards

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12/2/2009 12NTF 20091 2 3 4


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2

3




One Target – Different ways


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12/2/2009 13NTF 20091 2 3 4


Solution #1: Special coded Test Routine

3

On-Chip Resources

JTAG TAP

µP Core

Embedded Flash

Complex Bus I/F

Legacy Bus I/F



Flash Components

SRAM / DRAM


Peripheral Bus I/F

Aux Resources

JTAG Emulator

JTAG Emulator

Executable

Test Routine Development with native s/w Tool chain

Test Routine Development with native s/w Tool chain

Debugging of s/w and h/w via Emulator

Debugging of s/w and h/w via Emulator

Download into Flash and Program Execution

Download into Flash and Program Execution

12/2/2009 14NTF 20091 2 3 4


Solution #2: Configurable Test Routine

3

On-Chip Resources

JTAG TAP

µP Core

Embedded Flash

Complex Bus I/F

Legacy Bus I/F



Flash Components

SRAM / DRAM


Peripheral Bus I/F

Aux Resources

JTAG/ BScan Hardware


Executable

Configuration of standard Test IP by parameters

Configuration of standard Test IP by parameters

GO/NOGO and Failed Vector level Diagnostics

GO/NOGO and Failed Vector level Diagnostics

Program Execution using just the µP Core


12/2/2009 15NTF 20091 2 3 4


Solution #3: Automated Testing (ATPG)

3

On-Chip Resources

JTAG TAP

µP Core

Embedded Flash

Complex Bus I/F

Legacy Bus I/F



Flash Components

SRAM / DRAM


Peripheral Bus I/F

Aux Resources



Test Program

ATPG for structural Test Vector Generation

ATPG for structural Test Vector Generation

Pin Failure Diagnostics by system software

Pin Failure Diagnostics by system software



12/2/2009 16NTF 20091 2 3 4


Comparison of System Solutions Placeholder

Features

Unified BScan/Emulation test commands

True Interlaced BScan/Emulation operations

Predictive Fault coverage calculation

Automated Vector Generation

Use of native MCU tool chain

Manually s/w Source coding

Truth Table visualization of test execution

Pin Level Diagnostics

Unified hardware for BScan and Emulation

Total Programming and Test execution time

Flash firmware programming needed

System class

Special coded

Test RoutineATPG

Configured

Test Routine

no

no

yes

yes

no

no

no

possible

High

yes

no

yes

yes

no

no

possible

possible

yes

yes

low

no

yes

Semi automated

no

no

no

no

no

possible

Vector level

low

no

no

3

12/2/2009 17NTF 20091 2 3 4


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Technology Status


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12/2/2009 18NTF 20091 2 3 4


Quo Vadis Memory Access Test…

Conclusions and forecast

BScan by IEEE1149.1 is not able to cover memory access tests for high speed dRAM

Emulation Test is an excellent problem solution. Key is the used system architecture.

New standards like IEEE1581 and IEEE1687 will close the test coverage gap further

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12/2/2009 19NTF 20091 2 3 4


More information…

Further readings and References

[1] Jan Heiber – Boundary Scan versus Emulation Test Proceedings of the Nordic Test Forum 2008, Tallinn

[2] Heiko Ehrenberg and Thomas Wenzel – combining Boundary Scan and JTAG Emulation for advanced structural test and diagnostics

White Paper, GOEPEL electronics, 2009

[3] IEEE P1581 - Static Component InterconnectionTest Protocol and architecture

[4] IEEE P1687 – Access and Control of Instrumentation Embedded within a Semiconductor Device.

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12/2/2009 20NTF 20091 2 3 4


Thank you for your attention.

Any Questions?

For further information please use

the following contact information

Jan Heiber [email protected] www.goepel.com

Scandinavia +45-8748-0608 Germany +49-3641-6896-0

methods for access verification of dramdevices by ... · pdf file12/2/2009 ·...

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